xref: /linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi (revision 7b26feb436d2ef5db1e8ba82c7ecb4c1cc869502)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 OR MIT
2724ba675SRob Herring//
3724ba675SRob Herring// Copyright 2019 Armadeus Systems <support@armadeus.com>
4724ba675SRob Herring
5724ba675SRob Herring/ {
6724ba675SRob Herring	memory@80000000 {
7724ba675SRob Herring		device_type = "memory";
8724ba675SRob Herring		reg = <0x80000000 0>; /* will be filled by U-Boot */
9724ba675SRob Herring	};
10724ba675SRob Herring
11724ba675SRob Herring	reg_3v3: regulator-3v3 {
12724ba675SRob Herring		compatible = "regulator-fixed";
13724ba675SRob Herring		regulator-name = "3V3";
14724ba675SRob Herring		regulator-min-microvolt = <3300000>;
15724ba675SRob Herring		regulator-max-microvolt = <3300000>;
16724ba675SRob Herring	};
17724ba675SRob Herring
18724ba675SRob Herring	usdhc3_pwrseq: usdhc3-pwrseq {
19724ba675SRob Herring		compatible = "mmc-pwrseq-simple";
20724ba675SRob Herring		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
21724ba675SRob Herring	};
22724ba675SRob Herring};
23724ba675SRob Herring
24724ba675SRob Herring&fec1 {
25724ba675SRob Herring	pinctrl-names = "default";
26724ba675SRob Herring	pinctrl-0 = <&pinctrl_enet1>;
27724ba675SRob Herring	phy-mode = "rmii";
28724ba675SRob Herring	phy-reset-duration = <1>;
29724ba675SRob Herring	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
30724ba675SRob Herring	phy-handle = <&ethphy1>;
31724ba675SRob Herring	phy-supply = <&reg_3v3>;
32724ba675SRob Herring	status = "okay";
33724ba675SRob Herring
34724ba675SRob Herring	mdio: mdio {
35724ba675SRob Herring		#address-cells = <1>;
36724ba675SRob Herring		#size-cells = <0>;
37724ba675SRob Herring
38724ba675SRob Herring		ethphy1: ethernet-phy@1 {
39724ba675SRob Herring			compatible = "ethernet-phy-ieee802.3-c22";
40724ba675SRob Herring			reg = <1>;
41724ba675SRob Herring			interrupt-parent = <&gpio4>;
42724ba675SRob Herring			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
43*6e1a7bc8SSébastien Szymanski			micrel,led-mode = <1>;
44*6e1a7bc8SSébastien Szymanski			clocks = <&clks IMX6UL_CLK_ENET_REF>;
45*6e1a7bc8SSébastien Szymanski			clock-names = "rmii-ref";
46724ba675SRob Herring			status = "okay";
47724ba675SRob Herring		};
48724ba675SRob Herring	};
49724ba675SRob Herring};
50724ba675SRob Herring
51724ba675SRob Herring/* Bluetooth */
52724ba675SRob Herring&uart8 {
53724ba675SRob Herring	pinctrl-names = "default";
54724ba675SRob Herring	pinctrl-0 = <&pinctrl_uart8>;
55724ba675SRob Herring	uart-has-rtscts;
56724ba675SRob Herring	status = "okay";
57724ba675SRob Herring};
58724ba675SRob Herring
59724ba675SRob Herring/* eMMC */
60724ba675SRob Herring&usdhc1 {
61724ba675SRob Herring	pinctrl-names = "default";
62724ba675SRob Herring	pinctrl-0 = <&pinctrl_usdhc1>;
63724ba675SRob Herring	bus-width = <8>;
64724ba675SRob Herring	no-1-8-v;
65724ba675SRob Herring	non-removable;
66724ba675SRob Herring	status = "okay";
67724ba675SRob Herring};
68724ba675SRob Herring
69724ba675SRob Herring/* WiFi */
70724ba675SRob Herring&usdhc2 {
71724ba675SRob Herring	pinctrl-names = "default";
72724ba675SRob Herring	pinctrl-0 = <&pinctrl_usdhc2>;
73724ba675SRob Herring	bus-width = <4>;
74724ba675SRob Herring	no-1-8-v;
75724ba675SRob Herring	non-removable;
76724ba675SRob Herring	mmc-pwrseq = <&usdhc3_pwrseq>;
77724ba675SRob Herring	status = "okay";
78724ba675SRob Herring
79724ba675SRob Herring	#address-cells = <1>;
80724ba675SRob Herring	#size-cells = <0>;
81724ba675SRob Herring
82724ba675SRob Herring	brcmf: wifi@1 {
83724ba675SRob Herring		compatible = "brcm,bcm4329-fmac";
84724ba675SRob Herring		reg = <1>;
85724ba675SRob Herring		interrupt-parent = <&gpio2>;
86724ba675SRob Herring		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
87724ba675SRob Herring		interrupt-names = "host-wake";
88724ba675SRob Herring	};
89724ba675SRob Herring};
90724ba675SRob Herring
91724ba675SRob Herring&iomuxc {
92724ba675SRob Herring	pinctrl_enet1: enet1grp {
93724ba675SRob Herring		fsl,pins = <
94724ba675SRob Herring			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
95724ba675SRob Herring			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
96724ba675SRob Herring			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
97724ba675SRob Herring			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
98724ba675SRob Herring			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
99724ba675SRob Herring			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
100724ba675SRob Herring			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
101724ba675SRob Herring			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
102724ba675SRob Herring			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
103724ba675SRob Herring			/* INT# */
104724ba675SRob Herring			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
105724ba675SRob Herring			/* RST# */
106724ba675SRob Herring			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
107724ba675SRob Herring			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
108724ba675SRob Herring		>;
109724ba675SRob Herring	};
110724ba675SRob Herring
111724ba675SRob Herring	pinctrl_uart8: uart8grp {
112724ba675SRob Herring		fsl,pins = <
113724ba675SRob Herring			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
114724ba675SRob Herring			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
115724ba675SRob Herring			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
116724ba675SRob Herring			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
117724ba675SRob Herring			/* BT_REG_ON */
118724ba675SRob Herring			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
119724ba675SRob Herring		>;
120724ba675SRob Herring	};
121724ba675SRob Herring
122724ba675SRob Herring	pinctrl_usdhc1: usdhc1grp {
123724ba675SRob Herring		fsl,pins = <
124724ba675SRob Herring			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
125724ba675SRob Herring			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
126724ba675SRob Herring			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
127724ba675SRob Herring			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
128724ba675SRob Herring			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
129724ba675SRob Herring			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
130724ba675SRob Herring			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
131724ba675SRob Herring			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
132724ba675SRob Herring			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
133724ba675SRob Herring			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
134724ba675SRob Herring		>;
135724ba675SRob Herring	};
136724ba675SRob Herring
137724ba675SRob Herring	pinctrl_usdhc2: usdhc2grp {
138724ba675SRob Herring		fsl,pins = <
139724ba675SRob Herring			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
140724ba675SRob Herring			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
141724ba675SRob Herring			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
142724ba675SRob Herring			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
143724ba675SRob Herring			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
144724ba675SRob Herring			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
145724ba675SRob Herring			/* WL_REG_ON */
146724ba675SRob Herring			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
147724ba675SRob Herring			/* WL_IRQ */
148724ba675SRob Herring			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
149724ba675SRob Herring		>;
150724ba675SRob Herring	};
151724ba675SRob Herring};
152