1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*724ba675SRob Herring// 3*724ba675SRob Herring// Copyright 2016 Freescale Semiconductor, Inc. 4*724ba675SRob Herring 5*724ba675SRob Herring/dts-v1/; 6*724ba675SRob Herring 7*724ba675SRob Herring#include "imx6qp.dtsi" 8*724ba675SRob Herring#include "imx6qdl-sabreauto.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; 12*724ba675SRob Herring compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; 13*724ba675SRob Herring}; 14*724ba675SRob Herring 15*724ba675SRob Herring&i2c2 { 16*724ba675SRob Herring max7322: gpio@68 { 17*724ba675SRob Herring compatible = "maxim,max7322"; 18*724ba675SRob Herring reg = <0x68>; 19*724ba675SRob Herring gpio-controller; 20*724ba675SRob Herring #gpio-cells = <2>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring}; 23*724ba675SRob Herring 24*724ba675SRob Herring&iomuxc { 25*724ba675SRob Herring pinctrl_enet: enetgrp { 26*724ba675SRob Herring fsl,pins = < 27*724ba675SRob Herring MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 28*724ba675SRob Herring MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 29*724ba675SRob Herring MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 30*724ba675SRob Herring MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 31*724ba675SRob Herring MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 32*724ba675SRob Herring MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 33*724ba675SRob Herring MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 34*724ba675SRob Herring MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 35*724ba675SRob Herring MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 36*724ba675SRob Herring MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 37*724ba675SRob Herring MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 38*724ba675SRob Herring MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 39*724ba675SRob Herring MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 40*724ba675SRob Herring MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 41*724ba675SRob Herring MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 42*724ba675SRob Herring MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 43*724ba675SRob Herring >; 44*724ba675SRob Herring }; 45*724ba675SRob Herring}; 46*724ba675SRob Herring 47*724ba675SRob Herring&pcie { 48*724ba675SRob Herring reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; 49*724ba675SRob Herring status = "okay"; 50*724ba675SRob Herring}; 51*724ba675SRob Herring 52*724ba675SRob Herring&sata { 53*724ba675SRob Herring status = "okay"; 54*724ba675SRob Herring}; 55*724ba675SRob Herring 56*724ba675SRob Herring&vgen3_reg { 57*724ba675SRob Herring regulator-always-on; 58*724ba675SRob Herring}; 59