1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013 Pavel Machek <pavel@denx.de> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring#include "imx6q.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring model = "MicroSys sbc6x board"; 11*724ba675SRob Herring compatible = "microsys,sbc6x", "fsl,imx6q"; 12*724ba675SRob Herring 13*724ba675SRob Herring memory@10000000 { 14*724ba675SRob Herring device_type = "memory"; 15*724ba675SRob Herring reg = <0x10000000 0x80000000>; 16*724ba675SRob Herring }; 17*724ba675SRob Herring}; 18*724ba675SRob Herring 19*724ba675SRob Herring 20*724ba675SRob Herring&fec { 21*724ba675SRob Herring pinctrl-names = "default"; 22*724ba675SRob Herring pinctrl-0 = <&pinctrl_enet>; 23*724ba675SRob Herring phy-mode = "rgmii"; 24*724ba675SRob Herring status = "okay"; 25*724ba675SRob Herring}; 26*724ba675SRob Herring 27*724ba675SRob Herring&iomuxc { 28*724ba675SRob Herring pinctrl_enet: enetgrp { 29*724ba675SRob Herring fsl,pins = < 30*724ba675SRob Herring MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 31*724ba675SRob Herring MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 32*724ba675SRob Herring MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 33*724ba675SRob Herring MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 34*724ba675SRob Herring MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 35*724ba675SRob Herring MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 36*724ba675SRob Herring MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 37*724ba675SRob Herring MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 38*724ba675SRob Herring MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 39*724ba675SRob Herring MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 40*724ba675SRob Herring MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 41*724ba675SRob Herring MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 42*724ba675SRob Herring MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 43*724ba675SRob Herring MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 44*724ba675SRob Herring MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 45*724ba675SRob Herring MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 46*724ba675SRob Herring >; 47*724ba675SRob Herring }; 48*724ba675SRob Herring 49*724ba675SRob Herring pinctrl_uart1: uart1grp { 50*724ba675SRob Herring fsl,pins = < 51*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 52*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 53*724ba675SRob Herring >; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring pinctrl_usbotg: usbotggrp { 57*724ba675SRob Herring fsl,pins = < 58*724ba675SRob Herring MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 59*724ba675SRob Herring >; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring pinctrl_usdhc3: usdhc3grp { 63*724ba675SRob Herring fsl,pins = < 64*724ba675SRob Herring MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 65*724ba675SRob Herring MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 66*724ba675SRob Herring MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 67*724ba675SRob Herring MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 68*724ba675SRob Herring MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 69*724ba675SRob Herring MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 70*724ba675SRob Herring >; 71*724ba675SRob Herring }; 72*724ba675SRob Herring}; 73*724ba675SRob Herring 74*724ba675SRob Herring&uart1 { 75*724ba675SRob Herring pinctrl-names = "default"; 76*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart1>; 77*724ba675SRob Herring status = "okay"; 78*724ba675SRob Herring}; 79*724ba675SRob Herring 80*724ba675SRob Herring&usbotg { 81*724ba675SRob Herring pinctrl-names = "default"; 82*724ba675SRob Herring pinctrl-0 = <&pinctrl_usbotg>; 83*724ba675SRob Herring disable-over-current; 84*724ba675SRob Herring status = "okay"; 85*724ba675SRob Herring}; 86*724ba675SRob Herring 87*724ba675SRob Herring&usdhc3 { 88*724ba675SRob Herring pinctrl-names = "default"; 89*724ba675SRob Herring pinctrl-0 = <&pinctrl_usdhc3>; 90*724ba675SRob Herring status = "okay"; 91*724ba675SRob Herring}; 92