1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2014 Protonic Holland 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring#include "imx6dl.dtsi" 8*724ba675SRob Herring#include "imx6qdl-prti6q.dtsi" 9*724ba675SRob Herring#include <dt-bindings/leds/common.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "Protonic RVT board"; 13*724ba675SRob Herring compatible = "prt,prtrvt", "fsl,imx6dl"; 14*724ba675SRob Herring 15*724ba675SRob Herring memory@10000000 { 16*724ba675SRob Herring device_type = "memory"; 17*724ba675SRob Herring reg = <0x10000000 0x10000000>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring leds { 21*724ba675SRob Herring compatible = "gpio-leds"; 22*724ba675SRob Herring pinctrl-names = "default"; 23*724ba675SRob Herring pinctrl-0 = <&pinctrl_leds>; 24*724ba675SRob Herring 25*724ba675SRob Herring led-debug0 { 26*724ba675SRob Herring function = LED_FUNCTION_STATUS; 27*724ba675SRob Herring gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 28*724ba675SRob Herring linux,default-trigger = "heartbeat"; 29*724ba675SRob Herring }; 30*724ba675SRob Herring }; 31*724ba675SRob Herring}; 32*724ba675SRob Herring 33*724ba675SRob Herring&can1 { 34*724ba675SRob Herring pinctrl-names = "default"; 35*724ba675SRob Herring pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring}; 38*724ba675SRob Herring 39*724ba675SRob Herring&ecspi1 { 40*724ba675SRob Herring cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 41*724ba675SRob Herring pinctrl-names = "default"; 42*724ba675SRob Herring pinctrl-0 = <&pinctrl_ecspi1>; 43*724ba675SRob Herring status = "okay"; 44*724ba675SRob Herring 45*724ba675SRob Herring flash@0 { 46*724ba675SRob Herring compatible = "jedec,spi-nor"; 47*724ba675SRob Herring reg = <0>; 48*724ba675SRob Herring spi-max-frequency = <20000000>; 49*724ba675SRob Herring #address-cells = <1>; 50*724ba675SRob Herring #size-cells = <1>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring}; 53*724ba675SRob Herring 54*724ba675SRob Herring&ecspi3 { 55*724ba675SRob Herring cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 56*724ba675SRob Herring pinctrl-names = "default"; 57*724ba675SRob Herring pinctrl-0 = <&pinctrl_ecspi3>; 58*724ba675SRob Herring status = "okay"; 59*724ba675SRob Herring 60*724ba675SRob Herring nfc@0 { 61*724ba675SRob Herring compatible = "ti,trf7970a"; 62*724ba675SRob Herring reg = <0>; 63*724ba675SRob Herring pinctrl-names = "default"; 64*724ba675SRob Herring pinctrl-0 = <&pinctrl_nfc>; 65*724ba675SRob Herring spi-max-frequency = <2000000>; 66*724ba675SRob Herring interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; 67*724ba675SRob Herring ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, 68*724ba675SRob Herring <&gpio5 11 GPIO_ACTIVE_LOW>; 69*724ba675SRob Herring vin-supply = <®_3v3>; 70*724ba675SRob Herring autosuspend-delay = <30000>; 71*724ba675SRob Herring irq-status-read-quirk; 72*724ba675SRob Herring en2-rf-quirk; 73*724ba675SRob Herring status = "okay"; 74*724ba675SRob Herring }; 75*724ba675SRob Herring}; 76*724ba675SRob Herring 77*724ba675SRob Herring&i2c3 { 78*724ba675SRob Herring adc@49 { 79*724ba675SRob Herring compatible = "ti,ads1015"; 80*724ba675SRob Herring reg = <0x49>; 81*724ba675SRob Herring #address-cells = <1>; 82*724ba675SRob Herring #size-cells = <0>; 83*724ba675SRob Herring 84*724ba675SRob Herring /* nc */ 85*724ba675SRob Herring channel@4 { 86*724ba675SRob Herring reg = <4>; 87*724ba675SRob Herring ti,gain = <3>; 88*724ba675SRob Herring ti,datarate = <3>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring /* nc */ 92*724ba675SRob Herring channel@5 { 93*724ba675SRob Herring reg = <5>; 94*724ba675SRob Herring ti,gain = <3>; 95*724ba675SRob Herring ti,datarate = <3>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring /* can1_l */ 99*724ba675SRob Herring channel@6 { 100*724ba675SRob Herring reg = <6>; 101*724ba675SRob Herring ti,gain = <3>; 102*724ba675SRob Herring ti,datarate = <3>; 103*724ba675SRob Herring }; 104*724ba675SRob Herring 105*724ba675SRob Herring /* can1_h */ 106*724ba675SRob Herring channel@7 { 107*724ba675SRob Herring reg = <7>; 108*724ba675SRob Herring ti,gain = <3>; 109*724ba675SRob Herring ti,datarate = <3>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring }; 112*724ba675SRob Herring 113*724ba675SRob Herring rtc@51 { 114*724ba675SRob Herring compatible = "nxp,pcf8563"; 115*724ba675SRob Herring reg = <0x51>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring}; 118*724ba675SRob Herring 119*724ba675SRob Herring&pcie { 120*724ba675SRob Herring status = "okay"; 121*724ba675SRob Herring}; 122*724ba675SRob Herring 123*724ba675SRob Herring&usbh1 { 124*724ba675SRob Herring status = "disabled"; 125*724ba675SRob Herring}; 126*724ba675SRob Herring 127*724ba675SRob Herring&usbotg { 128*724ba675SRob Herring disable-over-current; 129*724ba675SRob Herring}; 130*724ba675SRob Herring 131*724ba675SRob Herring&vpu { 132*724ba675SRob Herring status = "disabled"; 133*724ba675SRob Herring}; 134*724ba675SRob Herring 135*724ba675SRob Herring&iomuxc { 136*724ba675SRob Herring pinctrl_can1phy: can1phy { 137*724ba675SRob Herring fsl,pins = < 138*724ba675SRob Herring /* CAN1_SR */ 139*724ba675SRob Herring MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 140*724ba675SRob Herring /* CAN1_TERM */ 141*724ba675SRob Herring MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 142*724ba675SRob Herring >; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring pinctrl_ecspi1: ecspi1grp { 146*724ba675SRob Herring fsl,pins = < 147*724ba675SRob Herring MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 148*724ba675SRob Herring MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 149*724ba675SRob Herring MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 150*724ba675SRob Herring /* CS */ 151*724ba675SRob Herring MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 152*724ba675SRob Herring >; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring pinctrl_ecspi3: ecspi3grp { 156*724ba675SRob Herring fsl,pins = < 157*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 158*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 159*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 160*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 161*724ba675SRob Herring >; 162*724ba675SRob Herring }; 163*724ba675SRob Herring 164*724ba675SRob Herring pinctrl_leds: ledsgrp { 165*724ba675SRob Herring fsl,pins = < 166*724ba675SRob Herring MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 167*724ba675SRob Herring >; 168*724ba675SRob Herring }; 169*724ba675SRob Herring 170*724ba675SRob Herring pinctrl_nfc: nfcgrp { 171*724ba675SRob Herring fsl,pins = < 172*724ba675SRob Herring /* NFC_ASK_OOK */ 173*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 174*724ba675SRob Herring /* NFC_PWR_EN */ 175*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 176*724ba675SRob Herring /* NFC_EN2 */ 177*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 178*724ba675SRob Herring /* NFC_EN */ 179*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 180*724ba675SRob Herring /* NFC_MOD */ 181*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 182*724ba675SRob Herring /* NFC_IRQ */ 183*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 184*724ba675SRob Herring >; 185*724ba675SRob Herring }; 186*724ba675SRob Herring}; 187