1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h> 5*724ba675SRob Herring#include <dt-bindings/input/input.h> 6*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 7*724ba675SRob Herring 8*724ba675SRob Herring#include "tegra30.dtsi" 9*724ba675SRob Herring#include "tegra30-cpu-opp.dtsi" 10*724ba675SRob Herring#include "tegra30-cpu-opp-microvolt.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring model = "Ouya Game Console"; 14*724ba675SRob Herring compatible = "ouya,ouya", "nvidia,tegra30"; 15*724ba675SRob Herring 16*724ba675SRob Herring aliases { 17*724ba675SRob Herring mmc0 = &sdmmc4; /* eMMC */ 18*724ba675SRob Herring mmc1 = &sdmmc3; /* WiFi */ 19*724ba675SRob Herring rtc0 = &pmic; 20*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 21*724ba675SRob Herring serial0 = &uartd; /* Debug Port */ 22*724ba675SRob Herring serial1 = &uartc; /* Bluetooth */ 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring chosen { 26*724ba675SRob Herring stdout-path = "serial0:115200n8"; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring firmware { 30*724ba675SRob Herring trusted-foundations { 31*724ba675SRob Herring compatible = "tlm,trusted-foundations"; 32*724ba675SRob Herring tlm,version-major = <0x0>; 33*724ba675SRob Herring tlm,version-minor = <0x0>; 34*724ba675SRob Herring }; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring memory@80000000 { 38*724ba675SRob Herring reg = <0x80000000 0x40000000>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring reserved-memory { 42*724ba675SRob Herring #address-cells = <1>; 43*724ba675SRob Herring #size-cells = <1>; 44*724ba675SRob Herring ranges; 45*724ba675SRob Herring 46*724ba675SRob Herring linux,cma@80000000 { 47*724ba675SRob Herring compatible = "shared-dma-pool"; 48*724ba675SRob Herring alloc-ranges = <0x80000000 0x30000000>; 49*724ba675SRob Herring size = <0x10000000>; /* 256MiB */ 50*724ba675SRob Herring linux,cma-default; 51*724ba675SRob Herring reusable; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring ramoops@bfdf0000 { 55*724ba675SRob Herring compatible = "ramoops"; 56*724ba675SRob Herring reg = <0xbfdf0000 0x10000>; /* 64kB */ 57*724ba675SRob Herring console-size = <0x8000>; /* 32kB */ 58*724ba675SRob Herring record-size = <0x400>; /* 1kB */ 59*724ba675SRob Herring ecc-size = <16>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring trustzone@bfe00000 { 63*724ba675SRob Herring reg = <0xbfe00000 0x200000>; 64*724ba675SRob Herring no-map; 65*724ba675SRob Herring }; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring host1x@50000000 { 69*724ba675SRob Herring hdmi@54280000 { 70*724ba675SRob Herring status = "okay"; 71*724ba675SRob Herring vdd-supply = <&vdd_vid_reg>; 72*724ba675SRob Herring pll-supply = <&ldo7_reg>; 73*724ba675SRob Herring hdmi-supply = <&sys_3v3_reg>; 74*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 75*724ba675SRob Herring nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring pinmux@70000868 { 80*724ba675SRob Herring pinctrl-names = "default"; 81*724ba675SRob Herring pinctrl-0 = <&state_default>; 82*724ba675SRob Herring 83*724ba675SRob Herring state_default: pinmux { 84*724ba675SRob Herring clk_32k_out_pa0 { 85*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 86*724ba675SRob Herring nvidia,function = "blink"; 87*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 88*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 89*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring 92*724ba675SRob Herring uart3_cts_n_pa1 { 93*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1"; 94*724ba675SRob Herring nvidia,function = "uartc"; 95*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 96*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 97*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring dap2_fs_pa2 { 101*724ba675SRob Herring nvidia,pins = "dap2_fs_pa2"; 102*724ba675SRob Herring nvidia,function = "i2s1"; 103*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 104*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 105*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring 108*724ba675SRob Herring dap2_sclk_pa3 { 109*724ba675SRob Herring nvidia,pins = "dap2_sclk_pa3"; 110*724ba675SRob Herring nvidia,function = "i2s1"; 111*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 112*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 113*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring dap2_din_pa4 { 117*724ba675SRob Herring nvidia,pins = "dap2_din_pa4"; 118*724ba675SRob Herring nvidia,function = "i2s1"; 119*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 121*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122*724ba675SRob Herring }; 123*724ba675SRob Herring 124*724ba675SRob Herring dap2_dout_pa5 { 125*724ba675SRob Herring nvidia,pins = "dap2_dout_pa5"; 126*724ba675SRob Herring nvidia,function = "i2s1"; 127*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 128*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 129*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 130*724ba675SRob Herring }; 131*724ba675SRob Herring 132*724ba675SRob Herring sdmmc3_clk_pa6 { 133*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 134*724ba675SRob Herring nvidia,function = "sdmmc3"; 135*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 136*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 137*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring sdmmc3_cmd_pa7 { 141*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7"; 142*724ba675SRob Herring nvidia,function = "sdmmc3"; 143*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 144*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 145*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring 148*724ba675SRob Herring gmi_a17_pb0 { 149*724ba675SRob Herring nvidia,pins = "gmi_a17_pb0"; 150*724ba675SRob Herring nvidia,function = "spi4"; 151*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 152*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 153*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 154*724ba675SRob Herring }; 155*724ba675SRob Herring 156*724ba675SRob Herring gmi_a18_pb1 { 157*724ba675SRob Herring nvidia,pins = "gmi_a18_pb1"; 158*724ba675SRob Herring nvidia,function = "spi4"; 159*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 160*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 161*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 162*724ba675SRob Herring }; 163*724ba675SRob Herring 164*724ba675SRob Herring lcd_pwr0_pb2 { 165*724ba675SRob Herring nvidia,pins = "lcd_pwr0_pb2"; 166*724ba675SRob Herring nvidia,function = "displaya"; 167*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 168*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 169*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 170*724ba675SRob Herring }; 171*724ba675SRob Herring 172*724ba675SRob Herring lcd_pclk_pb3 { 173*724ba675SRob Herring nvidia,pins = "lcd_pclk_pb3"; 174*724ba675SRob Herring nvidia,function = "displaya"; 175*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 177*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring 180*724ba675SRob Herring sdmmc3_dat3_pb4 { 181*724ba675SRob Herring nvidia,pins = "sdmmc3_dat3_pb4"; 182*724ba675SRob Herring nvidia,function = "sdmmc3"; 183*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 184*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 185*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 186*724ba675SRob Herring }; 187*724ba675SRob Herring 188*724ba675SRob Herring sdmmc3_dat2_pb5 { 189*724ba675SRob Herring nvidia,pins = "sdmmc3_dat2_pb5"; 190*724ba675SRob Herring nvidia,function = "sdmmc3"; 191*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 192*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 193*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring sdmmc3_dat1_pb6 { 197*724ba675SRob Herring nvidia,pins = "sdmmc3_dat1_pb6"; 198*724ba675SRob Herring nvidia,function = "sdmmc3"; 199*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 200*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 201*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 202*724ba675SRob Herring }; 203*724ba675SRob Herring 204*724ba675SRob Herring sdmmc3_dat0_pb7 { 205*724ba675SRob Herring nvidia,pins = "sdmmc3_dat0_pb7"; 206*724ba675SRob Herring nvidia,function = "sdmmc3"; 207*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 208*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 209*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring uart3_rts_n_pc0 { 213*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0"; 214*724ba675SRob Herring nvidia,function = "uartc"; 215*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 217*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring lcd_pwr1_pc1 { 221*724ba675SRob Herring nvidia,pins = "lcd_pwr1_pc1"; 222*724ba675SRob Herring nvidia,function = "displaya"; 223*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 224*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 225*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 226*724ba675SRob Herring }; 227*724ba675SRob Herring 228*724ba675SRob Herring uart2_txd_pc2 { 229*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2"; 230*724ba675SRob Herring nvidia,function = "uartb"; 231*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 232*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 233*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 234*724ba675SRob Herring }; 235*724ba675SRob Herring 236*724ba675SRob Herring uart2_rxd_pc3 { 237*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3"; 238*724ba675SRob Herring nvidia,function = "uartb"; 239*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 240*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 241*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring gen1_i2c_scl_pc4 { 245*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4"; 246*724ba675SRob Herring nvidia,function = "i2c1"; 247*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 248*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 249*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 250*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring gen1_i2c_sda_pc5 { 254*724ba675SRob Herring nvidia,pins = "gen1_i2c_sda_pc5"; 255*724ba675SRob Herring nvidia,function = "i2c1"; 256*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 257*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 258*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 259*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 260*724ba675SRob Herring }; 261*724ba675SRob Herring 262*724ba675SRob Herring lcd_pwr2_pc6 { 263*724ba675SRob Herring nvidia,pins = "lcd_pwr2_pc6"; 264*724ba675SRob Herring nvidia,function = "displaya"; 265*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 266*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 267*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 268*724ba675SRob Herring }; 269*724ba675SRob Herring 270*724ba675SRob Herring gmi_wp_n_pc7 { 271*724ba675SRob Herring nvidia,pins = "gmi_wp_n_pc7"; 272*724ba675SRob Herring nvidia,function = "gmi"; 273*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 274*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 275*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring sdmmc3_dat5_pd0 { 279*724ba675SRob Herring nvidia,pins = "sdmmc3_dat5_pd0"; 280*724ba675SRob Herring nvidia,function = "sdmmc3"; 281*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 282*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 283*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring sdmmc3_dat4_pd1 { 287*724ba675SRob Herring nvidia,pins = "sdmmc3_dat4_pd1"; 288*724ba675SRob Herring nvidia,function = "sdmmc3"; 289*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 290*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 291*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring 294*724ba675SRob Herring lcd_dc1_pd2 { 295*724ba675SRob Herring nvidia,pins = "lcd_dc1_pd2"; 296*724ba675SRob Herring nvidia,function = "displaya"; 297*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 298*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 299*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 300*724ba675SRob Herring }; 301*724ba675SRob Herring 302*724ba675SRob Herring sdmmc3_dat6_pd3 { 303*724ba675SRob Herring nvidia,pins = "sdmmc3_dat6_pd3"; 304*724ba675SRob Herring nvidia,function = "spi4"; 305*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 306*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 307*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 308*724ba675SRob Herring }; 309*724ba675SRob Herring 310*724ba675SRob Herring sdmmc3_dat7_pd4 { 311*724ba675SRob Herring nvidia,pins = "sdmmc3_dat7_pd4"; 312*724ba675SRob Herring nvidia,function = "spi4"; 313*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 314*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 315*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring vi_d1_pd5 { 319*724ba675SRob Herring nvidia,pins = "vi_d1_pd5"; 320*724ba675SRob Herring nvidia,function = "sdmmc2"; 321*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 322*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 323*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 324*724ba675SRob Herring }; 325*724ba675SRob Herring 326*724ba675SRob Herring vi_vsync_pd6 { 327*724ba675SRob Herring nvidia,pins = "vi_vsync_pd6"; 328*724ba675SRob Herring nvidia,function = "ddr"; 329*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 330*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 331*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 332*724ba675SRob Herring }; 333*724ba675SRob Herring 334*724ba675SRob Herring vi_hsync_pd7 { 335*724ba675SRob Herring nvidia,pins = "vi_hsync_pd7"; 336*724ba675SRob Herring nvidia,function = "ddr"; 337*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 338*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 339*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring lcd_d0_pe0 { 343*724ba675SRob Herring nvidia,pins = "lcd_d0_pe0"; 344*724ba675SRob Herring nvidia,function = "displaya"; 345*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 346*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 347*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 348*724ba675SRob Herring }; 349*724ba675SRob Herring 350*724ba675SRob Herring lcd_d1_pe1 { 351*724ba675SRob Herring nvidia,pins = "lcd_d1_pe1"; 352*724ba675SRob Herring nvidia,function = "displaya"; 353*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 354*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 355*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 356*724ba675SRob Herring }; 357*724ba675SRob Herring 358*724ba675SRob Herring lcd_d2_pe2 { 359*724ba675SRob Herring nvidia,pins = "lcd_d2_pe2"; 360*724ba675SRob Herring nvidia,function = "displaya"; 361*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 363*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 364*724ba675SRob Herring }; 365*724ba675SRob Herring 366*724ba675SRob Herring lcd_d3_pe3 { 367*724ba675SRob Herring nvidia,pins = "lcd_d3_pe3"; 368*724ba675SRob Herring nvidia,function = "displaya"; 369*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 370*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 371*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring lcd_d4_pe4 { 375*724ba675SRob Herring nvidia,pins = "lcd_d4_pe4"; 376*724ba675SRob Herring nvidia,function = "displaya"; 377*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 378*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 379*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring lcd_d5_pe5 { 383*724ba675SRob Herring nvidia,pins = "lcd_d5_pe5"; 384*724ba675SRob Herring nvidia,function = "displaya"; 385*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 386*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 387*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 388*724ba675SRob Herring }; 389*724ba675SRob Herring 390*724ba675SRob Herring lcd_d6_pe6 { 391*724ba675SRob Herring nvidia,pins = "lcd_d6_pe6"; 392*724ba675SRob Herring nvidia,function = "displaya"; 393*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 394*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 395*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring lcd_d7_pe7 { 399*724ba675SRob Herring nvidia,pins = "lcd_d7_pe7"; 400*724ba675SRob Herring nvidia,function = "displaya"; 401*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 402*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 403*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 404*724ba675SRob Herring }; 405*724ba675SRob Herring 406*724ba675SRob Herring lcd_d8_pf0 { 407*724ba675SRob Herring nvidia,pins = "lcd_d8_pf0"; 408*724ba675SRob Herring nvidia,function = "displaya"; 409*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 410*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 411*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 412*724ba675SRob Herring }; 413*724ba675SRob Herring 414*724ba675SRob Herring lcd_d9_pf1 { 415*724ba675SRob Herring nvidia,pins = "lcd_d9_pf1"; 416*724ba675SRob Herring nvidia,function = "displaya"; 417*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 419*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 420*724ba675SRob Herring }; 421*724ba675SRob Herring 422*724ba675SRob Herring lcd_d10_pf2 { 423*724ba675SRob Herring nvidia,pins = "lcd_d10_pf2"; 424*724ba675SRob Herring nvidia,function = "displaya"; 425*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 426*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 427*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 428*724ba675SRob Herring }; 429*724ba675SRob Herring 430*724ba675SRob Herring lcd_d11_pf3 { 431*724ba675SRob Herring nvidia,pins = "lcd_d11_pf3"; 432*724ba675SRob Herring nvidia,function = "displaya"; 433*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 434*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 435*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 436*724ba675SRob Herring }; 437*724ba675SRob Herring 438*724ba675SRob Herring lcd_d12_pf4 { 439*724ba675SRob Herring nvidia,pins = "lcd_d12_pf4"; 440*724ba675SRob Herring nvidia,function = "displaya"; 441*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 442*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 443*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 444*724ba675SRob Herring }; 445*724ba675SRob Herring 446*724ba675SRob Herring lcd_d13_pf5 { 447*724ba675SRob Herring nvidia,pins = "lcd_d13_pf5"; 448*724ba675SRob Herring nvidia,function = "displaya"; 449*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 450*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 451*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 452*724ba675SRob Herring }; 453*724ba675SRob Herring 454*724ba675SRob Herring lcd_d14_pf6 { 455*724ba675SRob Herring nvidia,pins = "lcd_d14_pf6"; 456*724ba675SRob Herring nvidia,function = "displaya"; 457*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 458*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 459*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 460*724ba675SRob Herring }; 461*724ba675SRob Herring 462*724ba675SRob Herring lcd_d15_pf7 { 463*724ba675SRob Herring nvidia,pins = "lcd_d15_pf7"; 464*724ba675SRob Herring nvidia,function = "displaya"; 465*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 466*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 467*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring gmi_ad0_pg0 { 471*724ba675SRob Herring nvidia,pins = "gmi_ad0_pg0"; 472*724ba675SRob Herring nvidia,function = "nand"; 473*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 474*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 475*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 476*724ba675SRob Herring }; 477*724ba675SRob Herring 478*724ba675SRob Herring gmi_ad1_pg1 { 479*724ba675SRob Herring nvidia,pins = "gmi_ad1_pg1"; 480*724ba675SRob Herring nvidia,function = "nand"; 481*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 482*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 483*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 484*724ba675SRob Herring }; 485*724ba675SRob Herring 486*724ba675SRob Herring gmi_ad2_pg2 { 487*724ba675SRob Herring nvidia,pins = "gmi_ad2_pg2"; 488*724ba675SRob Herring nvidia,function = "nand"; 489*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 490*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 491*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 492*724ba675SRob Herring }; 493*724ba675SRob Herring 494*724ba675SRob Herring gmi_ad3_pg3 { 495*724ba675SRob Herring nvidia,pins = "gmi_ad3_pg3"; 496*724ba675SRob Herring nvidia,function = "nand"; 497*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 498*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 499*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 500*724ba675SRob Herring }; 501*724ba675SRob Herring 502*724ba675SRob Herring gmi_ad4_pg4 { 503*724ba675SRob Herring nvidia,pins = "gmi_ad4_pg4"; 504*724ba675SRob Herring nvidia,function = "nand"; 505*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 506*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 507*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring gmi_ad5_pg5 { 511*724ba675SRob Herring nvidia,pins = "gmi_ad5_pg5"; 512*724ba675SRob Herring nvidia,function = "nand"; 513*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 514*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 515*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring gmi_ad6_pg6 { 519*724ba675SRob Herring nvidia,pins = "gmi_ad6_pg6"; 520*724ba675SRob Herring nvidia,function = "nand"; 521*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 522*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 523*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring gmi_ad7_pg7 { 527*724ba675SRob Herring nvidia,pins = "gmi_ad7_pg7"; 528*724ba675SRob Herring nvidia,function = "nand"; 529*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 530*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 531*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 532*724ba675SRob Herring }; 533*724ba675SRob Herring 534*724ba675SRob Herring gmi_ad8_ph0 { 535*724ba675SRob Herring nvidia,pins = "gmi_ad8_ph0"; 536*724ba675SRob Herring nvidia,function = "pwm0"; 537*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 538*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 539*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540*724ba675SRob Herring }; 541*724ba675SRob Herring 542*724ba675SRob Herring gmi_ad9_ph1 { 543*724ba675SRob Herring nvidia,pins = "gmi_ad9_ph1"; 544*724ba675SRob Herring nvidia,function = "pwm1"; 545*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 546*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 547*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 548*724ba675SRob Herring }; 549*724ba675SRob Herring 550*724ba675SRob Herring gmi_ad10_ph2 { 551*724ba675SRob Herring nvidia,pins = "gmi_ad10_ph2"; 552*724ba675SRob Herring nvidia,function = "pwm2"; 553*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 554*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 555*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 556*724ba675SRob Herring }; 557*724ba675SRob Herring 558*724ba675SRob Herring gmi_ad11_ph3 { 559*724ba675SRob Herring nvidia,pins = "gmi_ad11_ph3"; 560*724ba675SRob Herring nvidia,function = "nand"; 561*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 562*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 563*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 564*724ba675SRob Herring }; 565*724ba675SRob Herring 566*724ba675SRob Herring gmi_ad12_ph4 { 567*724ba675SRob Herring nvidia,pins = "gmi_ad12_ph4"; 568*724ba675SRob Herring nvidia,function = "nand"; 569*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 570*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 571*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 572*724ba675SRob Herring }; 573*724ba675SRob Herring 574*724ba675SRob Herring gmi_ad13_ph5 { 575*724ba675SRob Herring nvidia,pins = "gmi_ad13_ph5"; 576*724ba675SRob Herring nvidia,function = "nand"; 577*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 578*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 579*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring gmi_ad14_ph6 { 583*724ba675SRob Herring nvidia,pins = "gmi_ad14_ph6"; 584*724ba675SRob Herring nvidia,function = "nand"; 585*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 586*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 587*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 588*724ba675SRob Herring }; 589*724ba675SRob Herring 590*724ba675SRob Herring gmi_wr_n_pi0 { 591*724ba675SRob Herring nvidia,pins = "gmi_wr_n_pi0"; 592*724ba675SRob Herring nvidia,function = "nand"; 593*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 594*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 595*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring gmi_oe_n_pi1 { 599*724ba675SRob Herring nvidia,pins = "gmi_oe_n_pi1"; 600*724ba675SRob Herring nvidia,function = "nand"; 601*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 602*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 603*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 604*724ba675SRob Herring }; 605*724ba675SRob Herring 606*724ba675SRob Herring gmi_dqs_pi2 { 607*724ba675SRob Herring nvidia,pins = "gmi_dqs_pi2"; 608*724ba675SRob Herring nvidia,function = "nand"; 609*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 610*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 611*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring gmi_iordy_pi5 { 615*724ba675SRob Herring nvidia,pins = "gmi_iordy_pi5"; 616*724ba675SRob Herring nvidia,function = "rsvd1"; 617*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 618*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 619*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 620*724ba675SRob Herring }; 621*724ba675SRob Herring 622*724ba675SRob Herring gmi_cs7_n_pi6 { 623*724ba675SRob Herring nvidia,pins = "gmi_cs7_n_pi6"; 624*724ba675SRob Herring nvidia,function = "nand"; 625*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 626*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 627*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 628*724ba675SRob Herring }; 629*724ba675SRob Herring 630*724ba675SRob Herring gmi_wait_pi7 { 631*724ba675SRob Herring nvidia,pins = "gmi_wait_pi7"; 632*724ba675SRob Herring nvidia,function = "nand"; 633*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 634*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 635*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 636*724ba675SRob Herring }; 637*724ba675SRob Herring 638*724ba675SRob Herring lcd_de_pj1 { 639*724ba675SRob Herring nvidia,pins = "lcd_de_pj1"; 640*724ba675SRob Herring nvidia,function = "displaya"; 641*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 643*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 644*724ba675SRob Herring }; 645*724ba675SRob Herring 646*724ba675SRob Herring gmi_cs1_n_pj2 { 647*724ba675SRob Herring nvidia,pins = "gmi_cs1_n_pj2"; 648*724ba675SRob Herring nvidia,function = "rsvd1"; 649*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 650*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 651*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 652*724ba675SRob Herring }; 653*724ba675SRob Herring 654*724ba675SRob Herring lcd_hsync_pj3 { 655*724ba675SRob Herring nvidia,pins = "lcd_hsync_pj3"; 656*724ba675SRob Herring nvidia,function = "displaya"; 657*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 658*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 659*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 660*724ba675SRob Herring }; 661*724ba675SRob Herring 662*724ba675SRob Herring lcd_vsync_pj4 { 663*724ba675SRob Herring nvidia,pins = "lcd_vsync_pj4"; 664*724ba675SRob Herring nvidia,function = "displaya"; 665*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 666*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 667*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 668*724ba675SRob Herring }; 669*724ba675SRob Herring 670*724ba675SRob Herring uart2_cts_n_pj5 { 671*724ba675SRob Herring nvidia,pins = "uart2_cts_n_pj5"; 672*724ba675SRob Herring nvidia,function = "uartb"; 673*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 674*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 675*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 676*724ba675SRob Herring }; 677*724ba675SRob Herring 678*724ba675SRob Herring uart2_rts_n_pj6 { 679*724ba675SRob Herring nvidia,pins = "uart2_rts_n_pj6"; 680*724ba675SRob Herring nvidia,function = "uartb"; 681*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 682*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 683*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring gmi_a16_pj7 { 687*724ba675SRob Herring nvidia,pins = "gmi_a16_pj7"; 688*724ba675SRob Herring nvidia,function = "spi4"; 689*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 690*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 691*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 692*724ba675SRob Herring }; 693*724ba675SRob Herring 694*724ba675SRob Herring gmi_adv_n_pk0 { 695*724ba675SRob Herring nvidia,pins = "gmi_adv_n_pk0"; 696*724ba675SRob Herring nvidia,function = "nand"; 697*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 698*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 699*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 700*724ba675SRob Herring }; 701*724ba675SRob Herring 702*724ba675SRob Herring gmi_clk_pk1 { 703*724ba675SRob Herring nvidia,pins = "gmi_clk_pk1"; 704*724ba675SRob Herring nvidia,function = "nand"; 705*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 706*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 707*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 708*724ba675SRob Herring }; 709*724ba675SRob Herring 710*724ba675SRob Herring gmi_cs2_n_pk3 { 711*724ba675SRob Herring nvidia,pins = "gmi_cs2_n_pk3"; 712*724ba675SRob Herring nvidia,function = "rsvd1"; 713*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 714*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 715*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 716*724ba675SRob Herring }; 717*724ba675SRob Herring 718*724ba675SRob Herring gmi_cs3_n_pk4 { 719*724ba675SRob Herring nvidia,pins = "gmi_cs3_n_pk4"; 720*724ba675SRob Herring nvidia,function = "nand"; 721*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 722*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 723*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 724*724ba675SRob Herring }; 725*724ba675SRob Herring 726*724ba675SRob Herring spdif_out_pk5 { 727*724ba675SRob Herring nvidia,pins = "spdif_out_pk5"; 728*724ba675SRob Herring nvidia,function = "spdif"; 729*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 730*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 731*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 732*724ba675SRob Herring }; 733*724ba675SRob Herring 734*724ba675SRob Herring spdif_in_pk6 { 735*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 736*724ba675SRob Herring nvidia,function = "spdif"; 737*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 738*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 739*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring gmi_a19_pk7 { 743*724ba675SRob Herring nvidia,pins = "gmi_a19_pk7"; 744*724ba675SRob Herring nvidia,function = "spi4"; 745*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 746*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 747*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 748*724ba675SRob Herring }; 749*724ba675SRob Herring 750*724ba675SRob Herring vi_d2_pl0 { 751*724ba675SRob Herring nvidia,pins = "vi_d2_pl0"; 752*724ba675SRob Herring nvidia,function = "sdmmc2"; 753*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 754*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 755*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 756*724ba675SRob Herring }; 757*724ba675SRob Herring 758*724ba675SRob Herring vi_d3_pl1 { 759*724ba675SRob Herring nvidia,pins = "vi_d3_pl1"; 760*724ba675SRob Herring nvidia,function = "sdmmc2"; 761*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 762*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 763*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 764*724ba675SRob Herring }; 765*724ba675SRob Herring 766*724ba675SRob Herring vi_d4_pl2 { 767*724ba675SRob Herring nvidia,pins = "vi_d4_pl2"; 768*724ba675SRob Herring nvidia,function = "vi"; 769*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 770*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 771*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 772*724ba675SRob Herring }; 773*724ba675SRob Herring 774*724ba675SRob Herring vi_d5_pl3 { 775*724ba675SRob Herring nvidia,pins = "vi_d5_pl3"; 776*724ba675SRob Herring nvidia,function = "sdmmc2"; 777*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 778*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 779*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 780*724ba675SRob Herring }; 781*724ba675SRob Herring 782*724ba675SRob Herring vi_d6_pl4 { 783*724ba675SRob Herring nvidia,pins = "vi_d6_pl4"; 784*724ba675SRob Herring nvidia,function = "vi"; 785*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 786*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 787*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 788*724ba675SRob Herring }; 789*724ba675SRob Herring 790*724ba675SRob Herring vi_d7_pl5 { 791*724ba675SRob Herring nvidia,pins = "vi_d7_pl5"; 792*724ba675SRob Herring nvidia,function = "sdmmc2"; 793*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 794*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 795*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 796*724ba675SRob Herring }; 797*724ba675SRob Herring 798*724ba675SRob Herring vi_d8_pl6 { 799*724ba675SRob Herring nvidia,pins = "vi_d8_pl6"; 800*724ba675SRob Herring nvidia,function = "sdmmc2"; 801*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 802*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 803*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 804*724ba675SRob Herring }; 805*724ba675SRob Herring 806*724ba675SRob Herring vi_d9_pl7 { 807*724ba675SRob Herring nvidia,pins = "vi_d9_pl7"; 808*724ba675SRob Herring nvidia,function = "sdmmc2"; 809*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 810*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 811*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 812*724ba675SRob Herring }; 813*724ba675SRob Herring 814*724ba675SRob Herring lcd_d16_pm0 { 815*724ba675SRob Herring nvidia,pins = "lcd_d16_pm0"; 816*724ba675SRob Herring nvidia,function = "displaya"; 817*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 818*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 819*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 820*724ba675SRob Herring }; 821*724ba675SRob Herring 822*724ba675SRob Herring lcd_d17_pm1 { 823*724ba675SRob Herring nvidia,pins = "lcd_d17_pm1"; 824*724ba675SRob Herring nvidia,function = "displaya"; 825*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 826*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 827*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 828*724ba675SRob Herring }; 829*724ba675SRob Herring 830*724ba675SRob Herring lcd_d18_pm2 { 831*724ba675SRob Herring nvidia,pins = "lcd_d18_pm2"; 832*724ba675SRob Herring nvidia,function = "displaya"; 833*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 834*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 835*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 836*724ba675SRob Herring }; 837*724ba675SRob Herring 838*724ba675SRob Herring lcd_d19_pm3 { 839*724ba675SRob Herring nvidia,pins = "lcd_d19_pm3"; 840*724ba675SRob Herring nvidia,function = "displaya"; 841*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 842*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 843*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 844*724ba675SRob Herring }; 845*724ba675SRob Herring 846*724ba675SRob Herring lcd_d20_pm4 { 847*724ba675SRob Herring nvidia,pins = "lcd_d20_pm4"; 848*724ba675SRob Herring nvidia,function = "displaya"; 849*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 850*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 851*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 852*724ba675SRob Herring }; 853*724ba675SRob Herring 854*724ba675SRob Herring lcd_d21_pm5 { 855*724ba675SRob Herring nvidia,pins = "lcd_d21_pm5"; 856*724ba675SRob Herring nvidia,function = "displaya"; 857*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 858*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 859*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 860*724ba675SRob Herring }; 861*724ba675SRob Herring 862*724ba675SRob Herring lcd_d22_pm6 { 863*724ba675SRob Herring nvidia,pins = "lcd_d22_pm6"; 864*724ba675SRob Herring nvidia,function = "displaya"; 865*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 866*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 867*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 868*724ba675SRob Herring }; 869*724ba675SRob Herring 870*724ba675SRob Herring lcd_d23_pm7 { 871*724ba675SRob Herring nvidia,pins = "lcd_d23_pm7"; 872*724ba675SRob Herring nvidia,function = "displaya"; 873*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 874*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 875*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 876*724ba675SRob Herring }; 877*724ba675SRob Herring 878*724ba675SRob Herring dap1_fs_pn0 { 879*724ba675SRob Herring nvidia,pins = "dap1_fs_pn0"; 880*724ba675SRob Herring nvidia,function = "i2s0"; 881*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 882*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 883*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 884*724ba675SRob Herring }; 885*724ba675SRob Herring 886*724ba675SRob Herring dap1_din_pn1 { 887*724ba675SRob Herring nvidia,pins = "dap1_din_pn1"; 888*724ba675SRob Herring nvidia,function = "i2s0"; 889*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 890*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 891*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 892*724ba675SRob Herring }; 893*724ba675SRob Herring 894*724ba675SRob Herring dap1_dout_pn2 { 895*724ba675SRob Herring nvidia,pins = "dap1_dout_pn2"; 896*724ba675SRob Herring nvidia,function = "i2s0"; 897*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 898*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 899*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 900*724ba675SRob Herring }; 901*724ba675SRob Herring 902*724ba675SRob Herring dap1_sclk_pn3 { 903*724ba675SRob Herring nvidia,pins = "dap1_sclk_pn3"; 904*724ba675SRob Herring nvidia,function = "i2s0"; 905*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 906*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 907*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 908*724ba675SRob Herring }; 909*724ba675SRob Herring 910*724ba675SRob Herring lcd_cs0_n_pn4 { 911*724ba675SRob Herring nvidia,pins = "lcd_cs0_n_pn4"; 912*724ba675SRob Herring nvidia,function = "displaya"; 913*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 914*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 915*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 916*724ba675SRob Herring }; 917*724ba675SRob Herring 918*724ba675SRob Herring lcd_sdout_pn5 { 919*724ba675SRob Herring nvidia,pins = "lcd_sdout_pn5"; 920*724ba675SRob Herring nvidia,function = "displaya"; 921*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 922*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 923*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 924*724ba675SRob Herring }; 925*724ba675SRob Herring 926*724ba675SRob Herring lcd_dc0_pn6 { 927*724ba675SRob Herring nvidia,pins = "lcd_dc0_pn6"; 928*724ba675SRob Herring nvidia,function = "displaya"; 929*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 930*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 931*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 932*724ba675SRob Herring }; 933*724ba675SRob Herring 934*724ba675SRob Herring hdmi_int_pn7 { 935*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 936*724ba675SRob Herring nvidia,function = "hdmi"; 937*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 938*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 939*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 940*724ba675SRob Herring }; 941*724ba675SRob Herring 942*724ba675SRob Herring ulpi_data7_po0 { 943*724ba675SRob Herring nvidia,pins = "ulpi_data7_po0"; 944*724ba675SRob Herring nvidia,function = "uarta"; 945*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 946*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 947*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 948*724ba675SRob Herring }; 949*724ba675SRob Herring 950*724ba675SRob Herring ulpi_data0_po1 { 951*724ba675SRob Herring nvidia,pins = "ulpi_data0_po1"; 952*724ba675SRob Herring nvidia,function = "uarta"; 953*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 954*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 955*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 956*724ba675SRob Herring }; 957*724ba675SRob Herring 958*724ba675SRob Herring ulpi_data1_po2 { 959*724ba675SRob Herring nvidia,pins = "ulpi_data1_po2"; 960*724ba675SRob Herring nvidia,function = "uarta"; 961*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 962*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 963*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 964*724ba675SRob Herring }; 965*724ba675SRob Herring 966*724ba675SRob Herring ulpi_data2_po3 { 967*724ba675SRob Herring nvidia,pins = "ulpi_data2_po3"; 968*724ba675SRob Herring nvidia,function = "uarta"; 969*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 970*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 971*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 972*724ba675SRob Herring }; 973*724ba675SRob Herring 974*724ba675SRob Herring ulpi_data3_po4 { 975*724ba675SRob Herring nvidia,pins = "ulpi_data3_po4"; 976*724ba675SRob Herring nvidia,function = "uarta"; 977*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 978*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 979*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 980*724ba675SRob Herring }; 981*724ba675SRob Herring 982*724ba675SRob Herring ulpi_data4_po5 { 983*724ba675SRob Herring nvidia,pins = "ulpi_data4_po5"; 984*724ba675SRob Herring nvidia,function = "uarta"; 985*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 986*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 987*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 988*724ba675SRob Herring }; 989*724ba675SRob Herring 990*724ba675SRob Herring ulpi_data5_po6 { 991*724ba675SRob Herring nvidia,pins = "ulpi_data5_po6"; 992*724ba675SRob Herring nvidia,function = "uarta"; 993*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 994*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 995*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 996*724ba675SRob Herring }; 997*724ba675SRob Herring 998*724ba675SRob Herring ulpi_data6_po7 { 999*724ba675SRob Herring nvidia,pins = "ulpi_data6_po7"; 1000*724ba675SRob Herring nvidia,function = "uarta"; 1001*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1002*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1003*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1004*724ba675SRob Herring }; 1005*724ba675SRob Herring 1006*724ba675SRob Herring dap3_fs_pp0 { 1007*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0"; 1008*724ba675SRob Herring nvidia,function = "i2s2"; 1009*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1010*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1011*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1012*724ba675SRob Herring }; 1013*724ba675SRob Herring 1014*724ba675SRob Herring dap3_din_pp1 { 1015*724ba675SRob Herring nvidia,pins = "dap3_din_pp1"; 1016*724ba675SRob Herring nvidia,function = "i2s2"; 1017*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1018*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1019*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1020*724ba675SRob Herring }; 1021*724ba675SRob Herring 1022*724ba675SRob Herring dap3_dout_pp2 { 1023*724ba675SRob Herring nvidia,pins = "dap3_dout_pp2"; 1024*724ba675SRob Herring nvidia,function = "i2s2"; 1025*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1026*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1027*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1028*724ba675SRob Herring }; 1029*724ba675SRob Herring 1030*724ba675SRob Herring dap3_sclk_pp3 { 1031*724ba675SRob Herring nvidia,pins = "dap3_sclk_pp3"; 1032*724ba675SRob Herring nvidia,function = "i2s2"; 1033*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1034*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1035*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1036*724ba675SRob Herring }; 1037*724ba675SRob Herring 1038*724ba675SRob Herring dap4_fs_pp4 { 1039*724ba675SRob Herring nvidia,pins = "dap4_fs_pp4"; 1040*724ba675SRob Herring nvidia,function = "i2s3"; 1041*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1042*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1043*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1044*724ba675SRob Herring }; 1045*724ba675SRob Herring 1046*724ba675SRob Herring dap4_din_pp5 { 1047*724ba675SRob Herring nvidia,pins = "dap4_din_pp5"; 1048*724ba675SRob Herring nvidia,function = "i2s3"; 1049*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1050*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1051*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1052*724ba675SRob Herring }; 1053*724ba675SRob Herring 1054*724ba675SRob Herring dap4_dout_pp6 { 1055*724ba675SRob Herring nvidia,pins = "dap4_dout_pp6"; 1056*724ba675SRob Herring nvidia,function = "i2s3"; 1057*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1058*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1059*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1060*724ba675SRob Herring }; 1061*724ba675SRob Herring 1062*724ba675SRob Herring dap4_sclk_pp7 { 1063*724ba675SRob Herring nvidia,pins = "dap4_sclk_pp7"; 1064*724ba675SRob Herring nvidia,function = "i2s3"; 1065*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1066*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1067*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1068*724ba675SRob Herring }; 1069*724ba675SRob Herring 1070*724ba675SRob Herring kb_col0_pq0 { 1071*724ba675SRob Herring nvidia,pins = "kb_col0_pq0"; 1072*724ba675SRob Herring nvidia,function = "kbc"; 1073*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1074*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1075*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1076*724ba675SRob Herring }; 1077*724ba675SRob Herring 1078*724ba675SRob Herring kb_col1_pq1 { 1079*724ba675SRob Herring nvidia,pins = "kb_col1_pq1"; 1080*724ba675SRob Herring nvidia,function = "kbc"; 1081*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1082*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1083*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1084*724ba675SRob Herring }; 1085*724ba675SRob Herring 1086*724ba675SRob Herring kb_col2_pq2 { 1087*724ba675SRob Herring nvidia,pins = "kb_col2_pq2"; 1088*724ba675SRob Herring nvidia,function = "kbc"; 1089*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1090*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1091*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1092*724ba675SRob Herring }; 1093*724ba675SRob Herring 1094*724ba675SRob Herring kb_col3_pq3 { 1095*724ba675SRob Herring nvidia,pins = "kb_col3_pq3"; 1096*724ba675SRob Herring nvidia,function = "kbc"; 1097*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1098*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1099*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1100*724ba675SRob Herring }; 1101*724ba675SRob Herring 1102*724ba675SRob Herring kb_col4_pq4 { 1103*724ba675SRob Herring nvidia,pins = "kb_col4_pq4"; 1104*724ba675SRob Herring nvidia,function = "kbc"; 1105*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1106*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1107*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1108*724ba675SRob Herring }; 1109*724ba675SRob Herring 1110*724ba675SRob Herring kb_col5_pq5 { 1111*724ba675SRob Herring nvidia,pins = "kb_col5_pq5"; 1112*724ba675SRob Herring nvidia,function = "kbc"; 1113*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1114*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1115*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1116*724ba675SRob Herring }; 1117*724ba675SRob Herring 1118*724ba675SRob Herring kb_col6_pq6 { 1119*724ba675SRob Herring nvidia,pins = "kb_col6_pq6"; 1120*724ba675SRob Herring nvidia,function = "kbc"; 1121*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1122*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1123*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1124*724ba675SRob Herring }; 1125*724ba675SRob Herring 1126*724ba675SRob Herring kb_col7_pq7 { 1127*724ba675SRob Herring nvidia,pins = "kb_col7_pq7"; 1128*724ba675SRob Herring nvidia,function = "kbc"; 1129*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1130*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1131*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1132*724ba675SRob Herring }; 1133*724ba675SRob Herring 1134*724ba675SRob Herring kb_row0_pr0 { 1135*724ba675SRob Herring nvidia,pins = "kb_row0_pr0"; 1136*724ba675SRob Herring nvidia,function = "kbc"; 1137*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1138*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1139*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1140*724ba675SRob Herring }; 1141*724ba675SRob Herring 1142*724ba675SRob Herring kb_row1_pr1 { 1143*724ba675SRob Herring nvidia,pins = "kb_row1_pr1"; 1144*724ba675SRob Herring nvidia,function = "kbc"; 1145*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1146*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1147*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1148*724ba675SRob Herring }; 1149*724ba675SRob Herring 1150*724ba675SRob Herring kb_row2_pr2 { 1151*724ba675SRob Herring nvidia,pins = "kb_row2_pr2"; 1152*724ba675SRob Herring nvidia,function = "kbc"; 1153*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1154*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1155*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1156*724ba675SRob Herring }; 1157*724ba675SRob Herring 1158*724ba675SRob Herring kb_row3_pr3 { 1159*724ba675SRob Herring nvidia,pins = "kb_row3_pr3"; 1160*724ba675SRob Herring nvidia,function = "kbc"; 1161*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1162*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1163*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1164*724ba675SRob Herring }; 1165*724ba675SRob Herring 1166*724ba675SRob Herring kb_row4_pr4 { 1167*724ba675SRob Herring nvidia,pins = "kb_row4_pr4"; 1168*724ba675SRob Herring nvidia,function = "kbc"; 1169*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1170*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1171*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring 1174*724ba675SRob Herring kb_row5_pr5 { 1175*724ba675SRob Herring nvidia,pins = "kb_row5_pr5"; 1176*724ba675SRob Herring nvidia,function = "kbc"; 1177*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1178*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1179*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1180*724ba675SRob Herring }; 1181*724ba675SRob Herring 1182*724ba675SRob Herring kb_row6_pr6 { 1183*724ba675SRob Herring nvidia,pins = "kb_row6_pr6"; 1184*724ba675SRob Herring nvidia,function = "kbc"; 1185*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1186*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1187*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1188*724ba675SRob Herring }; 1189*724ba675SRob Herring 1190*724ba675SRob Herring kb_row7_pr7 { 1191*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 1192*724ba675SRob Herring nvidia,function = "kbc"; 1193*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1194*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1195*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1196*724ba675SRob Herring }; 1197*724ba675SRob Herring 1198*724ba675SRob Herring kb_row8_ps0 { 1199*724ba675SRob Herring nvidia,pins = "kb_row8_ps0"; 1200*724ba675SRob Herring nvidia,function = "kbc"; 1201*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1202*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1203*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1204*724ba675SRob Herring }; 1205*724ba675SRob Herring 1206*724ba675SRob Herring kb_row9_ps1 { 1207*724ba675SRob Herring nvidia,pins = "kb_row9_ps1"; 1208*724ba675SRob Herring nvidia,function = "kbc"; 1209*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1210*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1211*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1212*724ba675SRob Herring }; 1213*724ba675SRob Herring 1214*724ba675SRob Herring kb_row10_ps2 { 1215*724ba675SRob Herring nvidia,pins = "kb_row10_ps2"; 1216*724ba675SRob Herring nvidia,function = "kbc"; 1217*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1218*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1219*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1220*724ba675SRob Herring }; 1221*724ba675SRob Herring 1222*724ba675SRob Herring kb_row11_ps3 { 1223*724ba675SRob Herring nvidia,pins = "kb_row11_ps3"; 1224*724ba675SRob Herring nvidia,function = "kbc"; 1225*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1226*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1227*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1228*724ba675SRob Herring }; 1229*724ba675SRob Herring 1230*724ba675SRob Herring kb_row12_ps4 { 1231*724ba675SRob Herring nvidia,pins = "kb_row12_ps4"; 1232*724ba675SRob Herring nvidia,function = "kbc"; 1233*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1234*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1235*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1236*724ba675SRob Herring }; 1237*724ba675SRob Herring 1238*724ba675SRob Herring kb_row13_ps5 { 1239*724ba675SRob Herring nvidia,pins = "kb_row13_ps5"; 1240*724ba675SRob Herring nvidia,function = "kbc"; 1241*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1242*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1243*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1244*724ba675SRob Herring }; 1245*724ba675SRob Herring 1246*724ba675SRob Herring kb_row14_ps6 { 1247*724ba675SRob Herring nvidia,pins = "kb_row14_ps6"; 1248*724ba675SRob Herring nvidia,function = "kbc"; 1249*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1250*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1251*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1252*724ba675SRob Herring }; 1253*724ba675SRob Herring 1254*724ba675SRob Herring kb_row15_ps7 { 1255*724ba675SRob Herring nvidia,pins = "kb_row15_ps7"; 1256*724ba675SRob Herring nvidia,function = "kbc"; 1257*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1258*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1259*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1260*724ba675SRob Herring }; 1261*724ba675SRob Herring 1262*724ba675SRob Herring vi_pclk_pt0 { 1263*724ba675SRob Herring nvidia,pins = "vi_pclk_pt0"; 1264*724ba675SRob Herring nvidia,function = "rsvd1"; 1265*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1266*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1267*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1268*724ba675SRob Herring }; 1269*724ba675SRob Herring 1270*724ba675SRob Herring vi_mclk_pt1 { 1271*724ba675SRob Herring nvidia,pins = "vi_mclk_pt1"; 1272*724ba675SRob Herring nvidia,function = "vi"; 1273*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1274*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1275*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1276*724ba675SRob Herring }; 1277*724ba675SRob Herring 1278*724ba675SRob Herring vi_d10_pt2 { 1279*724ba675SRob Herring nvidia,pins = "vi_d10_pt2"; 1280*724ba675SRob Herring nvidia,function = "ddr"; 1281*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1282*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1283*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1284*724ba675SRob Herring }; 1285*724ba675SRob Herring 1286*724ba675SRob Herring vi_d11_pt3 { 1287*724ba675SRob Herring nvidia,pins = "vi_d11_pt3"; 1288*724ba675SRob Herring nvidia,function = "ddr"; 1289*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1290*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1291*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1292*724ba675SRob Herring }; 1293*724ba675SRob Herring 1294*724ba675SRob Herring vi_d0_pt4 { 1295*724ba675SRob Herring nvidia,pins = "vi_d0_pt4"; 1296*724ba675SRob Herring nvidia,function = "ddr"; 1297*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1298*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1299*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1300*724ba675SRob Herring }; 1301*724ba675SRob Herring 1302*724ba675SRob Herring gen2_i2c_scl_pt5 { 1303*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5"; 1304*724ba675SRob Herring nvidia,function = "i2c2"; 1305*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1306*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1307*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1308*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1309*724ba675SRob Herring }; 1310*724ba675SRob Herring 1311*724ba675SRob Herring gen2_i2c_sda_pt6 { 1312*724ba675SRob Herring nvidia,pins = "gen2_i2c_sda_pt6"; 1313*724ba675SRob Herring nvidia,function = "i2c2"; 1314*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1315*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1316*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1317*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1318*724ba675SRob Herring }; 1319*724ba675SRob Herring 1320*724ba675SRob Herring sdmmc4_cmd_pt7 { 1321*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7"; 1322*724ba675SRob Herring nvidia,function = "sdmmc4"; 1323*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1324*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1325*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1326*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1327*724ba675SRob Herring }; 1328*724ba675SRob Herring 1329*724ba675SRob Herring pu0 { 1330*724ba675SRob Herring nvidia,pins = "pu0"; 1331*724ba675SRob Herring nvidia,function = "owr"; 1332*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1333*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1334*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1335*724ba675SRob Herring }; 1336*724ba675SRob Herring 1337*724ba675SRob Herring pu1 { 1338*724ba675SRob Herring nvidia,pins = "pu1"; 1339*724ba675SRob Herring nvidia,function = "rsvd1"; 1340*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1341*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1342*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1343*724ba675SRob Herring }; 1344*724ba675SRob Herring 1345*724ba675SRob Herring pu2 { 1346*724ba675SRob Herring nvidia,pins = "pu2"; 1347*724ba675SRob Herring nvidia,function = "rsvd1"; 1348*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1349*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1350*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1351*724ba675SRob Herring }; 1352*724ba675SRob Herring 1353*724ba675SRob Herring pu3 { 1354*724ba675SRob Herring nvidia,pins = "pu3"; 1355*724ba675SRob Herring nvidia,function = "pwm0"; 1356*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1357*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1358*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1359*724ba675SRob Herring }; 1360*724ba675SRob Herring 1361*724ba675SRob Herring pu4 { 1362*724ba675SRob Herring nvidia,pins = "pu4"; 1363*724ba675SRob Herring nvidia,function = "pwm1"; 1364*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1365*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1366*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1367*724ba675SRob Herring }; 1368*724ba675SRob Herring 1369*724ba675SRob Herring pu5 { 1370*724ba675SRob Herring nvidia,pins = "pu5"; 1371*724ba675SRob Herring nvidia,function = "rsvd4"; 1372*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1373*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1374*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1375*724ba675SRob Herring }; 1376*724ba675SRob Herring 1377*724ba675SRob Herring pu6 { 1378*724ba675SRob Herring nvidia,pins = "pu6"; 1379*724ba675SRob Herring nvidia,function = "pwm3"; 1380*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1381*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1382*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1383*724ba675SRob Herring }; 1384*724ba675SRob Herring 1385*724ba675SRob Herring jtag_rtck_pu7 { 1386*724ba675SRob Herring nvidia,pins = "jtag_rtck_pu7"; 1387*724ba675SRob Herring nvidia,function = "rtck"; 1388*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1389*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1390*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1391*724ba675SRob Herring }; 1392*724ba675SRob Herring 1393*724ba675SRob Herring pv0 { 1394*724ba675SRob Herring nvidia,pins = "pv0"; 1395*724ba675SRob Herring nvidia,function = "rsvd1"; 1396*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1397*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1398*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1399*724ba675SRob Herring }; 1400*724ba675SRob Herring 1401*724ba675SRob Herring pv1 { 1402*724ba675SRob Herring nvidia,pins = "pv1"; 1403*724ba675SRob Herring nvidia,function = "rsvd1"; 1404*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1405*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1406*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1407*724ba675SRob Herring }; 1408*724ba675SRob Herring 1409*724ba675SRob Herring pv2 { 1410*724ba675SRob Herring nvidia,pins = "pv2"; 1411*724ba675SRob Herring nvidia,function = "owr"; 1412*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1413*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1414*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1415*724ba675SRob Herring }; 1416*724ba675SRob Herring 1417*724ba675SRob Herring pv3 { 1418*724ba675SRob Herring nvidia,pins = "pv3"; 1419*724ba675SRob Herring nvidia,function = "clk_12m_out"; 1420*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1421*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1422*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1423*724ba675SRob Herring }; 1424*724ba675SRob Herring 1425*724ba675SRob Herring ddc_scl_pv4 { 1426*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4"; 1427*724ba675SRob Herring nvidia,function = "i2c4"; 1428*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1429*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1430*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1431*724ba675SRob Herring }; 1432*724ba675SRob Herring 1433*724ba675SRob Herring ddc_sda_pv5 { 1434*724ba675SRob Herring nvidia,pins = "ddc_sda_pv5"; 1435*724ba675SRob Herring nvidia,function = "i2c4"; 1436*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1437*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1438*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1439*724ba675SRob Herring }; 1440*724ba675SRob Herring 1441*724ba675SRob Herring crt_hsync_pv6 { 1442*724ba675SRob Herring nvidia,pins = "crt_hsync_pv6"; 1443*724ba675SRob Herring nvidia,function = "crt"; 1444*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1445*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1446*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1447*724ba675SRob Herring }; 1448*724ba675SRob Herring 1449*724ba675SRob Herring crt_vsync_pv7 { 1450*724ba675SRob Herring nvidia,pins = "crt_vsync_pv7"; 1451*724ba675SRob Herring nvidia,function = "crt"; 1452*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1453*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1454*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1455*724ba675SRob Herring }; 1456*724ba675SRob Herring 1457*724ba675SRob Herring lcd_cs1_n_pw0 { 1458*724ba675SRob Herring nvidia,pins = "lcd_cs1_n_pw0"; 1459*724ba675SRob Herring nvidia,function = "displaya"; 1460*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1461*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1462*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1463*724ba675SRob Herring }; 1464*724ba675SRob Herring 1465*724ba675SRob Herring lcd_m1_pw1 { 1466*724ba675SRob Herring nvidia,pins = "lcd_m1_pw1"; 1467*724ba675SRob Herring nvidia,function = "displaya"; 1468*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1469*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1470*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1471*724ba675SRob Herring }; 1472*724ba675SRob Herring 1473*724ba675SRob Herring spi2_cs1_n_pw2 { 1474*724ba675SRob Herring nvidia,pins = "spi2_cs1_n_pw2"; 1475*724ba675SRob Herring nvidia,function = "spi2"; 1476*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1477*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1478*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1479*724ba675SRob Herring }; 1480*724ba675SRob Herring 1481*724ba675SRob Herring clk1_out_pw4 { 1482*724ba675SRob Herring nvidia,pins = "clk1_out_pw4"; 1483*724ba675SRob Herring nvidia,function = "extperiph1"; 1484*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1485*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1486*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1487*724ba675SRob Herring }; 1488*724ba675SRob Herring 1489*724ba675SRob Herring clk2_out_pw5 { 1490*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 1491*724ba675SRob Herring nvidia,function = "extperiph2"; 1492*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1493*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1494*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1495*724ba675SRob Herring }; 1496*724ba675SRob Herring 1497*724ba675SRob Herring uart3_txd_pw6 { 1498*724ba675SRob Herring nvidia,pins = "uart3_txd_pw6"; 1499*724ba675SRob Herring nvidia,function = "uartc"; 1500*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1501*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1502*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1503*724ba675SRob Herring }; 1504*724ba675SRob Herring 1505*724ba675SRob Herring uart3_rxd_pw7 { 1506*724ba675SRob Herring nvidia,pins = "uart3_rxd_pw7"; 1507*724ba675SRob Herring nvidia,function = "uartc"; 1508*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1509*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1510*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1511*724ba675SRob Herring }; 1512*724ba675SRob Herring 1513*724ba675SRob Herring spi2_sck_px2 { 1514*724ba675SRob Herring nvidia,pins = "spi2_sck_px2"; 1515*724ba675SRob Herring nvidia,function = "gmi"; 1516*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1517*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1518*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1519*724ba675SRob Herring }; 1520*724ba675SRob Herring 1521*724ba675SRob Herring spi1_mosi_px4 { 1522*724ba675SRob Herring nvidia,pins = "spi1_mosi_px4"; 1523*724ba675SRob Herring nvidia,function = "spi1"; 1524*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1525*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1526*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1527*724ba675SRob Herring }; 1528*724ba675SRob Herring 1529*724ba675SRob Herring spi1_sck_px5 { 1530*724ba675SRob Herring nvidia,pins = "spi1_sck_px5"; 1531*724ba675SRob Herring nvidia,function = "spi1"; 1532*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1533*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1534*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1535*724ba675SRob Herring }; 1536*724ba675SRob Herring 1537*724ba675SRob Herring spi1_cs0_n_px6 { 1538*724ba675SRob Herring nvidia,pins = "spi1_cs0_n_px6"; 1539*724ba675SRob Herring nvidia,function = "spi1"; 1540*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1541*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1542*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1543*724ba675SRob Herring }; 1544*724ba675SRob Herring 1545*724ba675SRob Herring spi1_miso_px7 { 1546*724ba675SRob Herring nvidia,pins = "spi1_miso_px7"; 1547*724ba675SRob Herring nvidia,function = "spi1"; 1548*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1549*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1550*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1551*724ba675SRob Herring }; 1552*724ba675SRob Herring 1553*724ba675SRob Herring ulpi_clk_py0 { 1554*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0"; 1555*724ba675SRob Herring nvidia,function = "uartd"; 1556*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1557*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1558*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1559*724ba675SRob Herring }; 1560*724ba675SRob Herring 1561*724ba675SRob Herring ulpi_dir_py1 { 1562*724ba675SRob Herring nvidia,pins = "ulpi_dir_py1"; 1563*724ba675SRob Herring nvidia,function = "uartd"; 1564*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1565*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1566*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1567*724ba675SRob Herring }; 1568*724ba675SRob Herring 1569*724ba675SRob Herring ulpi_nxt_py2 { 1570*724ba675SRob Herring nvidia,pins = "ulpi_nxt_py2"; 1571*724ba675SRob Herring nvidia,function = "uartd"; 1572*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1573*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1574*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1575*724ba675SRob Herring }; 1576*724ba675SRob Herring 1577*724ba675SRob Herring ulpi_stp_py3 { 1578*724ba675SRob Herring nvidia,pins = "ulpi_stp_py3"; 1579*724ba675SRob Herring nvidia,function = "uartd"; 1580*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1581*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1582*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1583*724ba675SRob Herring }; 1584*724ba675SRob Herring 1585*724ba675SRob Herring sdmmc1_dat3_py4 { 1586*724ba675SRob Herring nvidia,pins = "sdmmc1_dat3_py4"; 1587*724ba675SRob Herring nvidia,function = "sdmmc1"; 1588*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1589*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1590*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1591*724ba675SRob Herring }; 1592*724ba675SRob Herring 1593*724ba675SRob Herring sdmmc1_dat2_py5 { 1594*724ba675SRob Herring nvidia,pins = "sdmmc1_dat2_py5"; 1595*724ba675SRob Herring nvidia,function = "sdmmc1"; 1596*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1597*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1598*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1599*724ba675SRob Herring }; 1600*724ba675SRob Herring 1601*724ba675SRob Herring sdmmc1_dat1_py6 { 1602*724ba675SRob Herring nvidia,pins = "sdmmc1_dat1_py6"; 1603*724ba675SRob Herring nvidia,function = "sdmmc1"; 1604*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1605*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1606*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1607*724ba675SRob Herring }; 1608*724ba675SRob Herring 1609*724ba675SRob Herring sdmmc1_dat0_py7 { 1610*724ba675SRob Herring nvidia,pins = "sdmmc1_dat0_py7"; 1611*724ba675SRob Herring nvidia,function = "sdmmc1"; 1612*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1613*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1614*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1615*724ba675SRob Herring }; 1616*724ba675SRob Herring 1617*724ba675SRob Herring sdmmc1_clk_pz0 { 1618*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 1619*724ba675SRob Herring nvidia,function = "sdmmc1"; 1620*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1621*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1622*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1623*724ba675SRob Herring }; 1624*724ba675SRob Herring 1625*724ba675SRob Herring sdmmc1_cmd_pz1 { 1626*724ba675SRob Herring nvidia,pins = "sdmmc1_cmd_pz1"; 1627*724ba675SRob Herring nvidia,function = "sdmmc1"; 1628*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1629*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1630*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1631*724ba675SRob Herring }; 1632*724ba675SRob Herring 1633*724ba675SRob Herring lcd_sdin_pz2 { 1634*724ba675SRob Herring nvidia,pins = "lcd_sdin_pz2"; 1635*724ba675SRob Herring nvidia,function = "displaya"; 1636*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1637*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1638*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1639*724ba675SRob Herring }; 1640*724ba675SRob Herring 1641*724ba675SRob Herring lcd_wr_n_pz3 { 1642*724ba675SRob Herring nvidia,pins = "lcd_wr_n_pz3"; 1643*724ba675SRob Herring nvidia,function = "displaya"; 1644*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1645*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1646*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1647*724ba675SRob Herring }; 1648*724ba675SRob Herring 1649*724ba675SRob Herring lcd_sck_pz4 { 1650*724ba675SRob Herring nvidia,pins = "lcd_sck_pz4"; 1651*724ba675SRob Herring nvidia,function = "displaya"; 1652*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1653*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1654*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1655*724ba675SRob Herring }; 1656*724ba675SRob Herring 1657*724ba675SRob Herring sys_clk_req_pz5 { 1658*724ba675SRob Herring nvidia,pins = "sys_clk_req_pz5"; 1659*724ba675SRob Herring nvidia,function = "sysclk"; 1660*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1661*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1662*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1663*724ba675SRob Herring }; 1664*724ba675SRob Herring 1665*724ba675SRob Herring pwr_i2c_scl_pz6 { 1666*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6"; 1667*724ba675SRob Herring nvidia,function = "i2cpwr"; 1668*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1669*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1670*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1671*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1672*724ba675SRob Herring }; 1673*724ba675SRob Herring 1674*724ba675SRob Herring pwr_i2c_sda_pz7 { 1675*724ba675SRob Herring nvidia,pins = "pwr_i2c_sda_pz7"; 1676*724ba675SRob Herring nvidia,function = "i2cpwr"; 1677*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1678*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1679*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1680*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1681*724ba675SRob Herring }; 1682*724ba675SRob Herring 1683*724ba675SRob Herring sdmmc4_dat0_paa0 { 1684*724ba675SRob Herring nvidia,pins = "sdmmc4_dat0_paa0"; 1685*724ba675SRob Herring nvidia,function = "sdmmc4"; 1686*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1687*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1688*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1689*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1690*724ba675SRob Herring }; 1691*724ba675SRob Herring 1692*724ba675SRob Herring sdmmc4_dat1_paa1 { 1693*724ba675SRob Herring nvidia,pins = "sdmmc4_dat1_paa1"; 1694*724ba675SRob Herring nvidia,function = "sdmmc4"; 1695*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1696*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1697*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1698*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1699*724ba675SRob Herring }; 1700*724ba675SRob Herring 1701*724ba675SRob Herring sdmmc4_dat2_paa2 { 1702*724ba675SRob Herring nvidia,pins = "sdmmc4_dat2_paa2"; 1703*724ba675SRob Herring nvidia,function = "sdmmc4"; 1704*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1705*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1706*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1707*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1708*724ba675SRob Herring }; 1709*724ba675SRob Herring 1710*724ba675SRob Herring sdmmc4_dat3_paa3 { 1711*724ba675SRob Herring nvidia,pins = "sdmmc4_dat3_paa3"; 1712*724ba675SRob Herring nvidia,function = "sdmmc4"; 1713*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1714*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1715*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1716*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1717*724ba675SRob Herring }; 1718*724ba675SRob Herring 1719*724ba675SRob Herring sdmmc4_dat4_paa4 { 1720*724ba675SRob Herring nvidia,pins = "sdmmc4_dat4_paa4"; 1721*724ba675SRob Herring nvidia,function = "sdmmc4"; 1722*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1723*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1724*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1725*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1726*724ba675SRob Herring }; 1727*724ba675SRob Herring 1728*724ba675SRob Herring sdmmc4_dat5_paa5 { 1729*724ba675SRob Herring nvidia,pins = "sdmmc4_dat5_paa5"; 1730*724ba675SRob Herring nvidia,function = "sdmmc4"; 1731*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1732*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1733*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1734*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1735*724ba675SRob Herring }; 1736*724ba675SRob Herring 1737*724ba675SRob Herring sdmmc4_dat6_paa6 { 1738*724ba675SRob Herring nvidia,pins = "sdmmc4_dat6_paa6"; 1739*724ba675SRob Herring nvidia,function = "sdmmc4"; 1740*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1741*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1742*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1743*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1744*724ba675SRob Herring }; 1745*724ba675SRob Herring 1746*724ba675SRob Herring sdmmc4_dat7_paa7 { 1747*724ba675SRob Herring nvidia,pins = "sdmmc4_dat7_paa7"; 1748*724ba675SRob Herring nvidia,function = "sdmmc4"; 1749*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1750*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1751*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1752*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1753*724ba675SRob Herring }; 1754*724ba675SRob Herring 1755*724ba675SRob Herring pbb0 { 1756*724ba675SRob Herring nvidia,pins = "pbb0"; 1757*724ba675SRob Herring nvidia,function = "i2s4"; 1758*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1759*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1760*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1761*724ba675SRob Herring }; 1762*724ba675SRob Herring 1763*724ba675SRob Herring cam_i2c_scl_pbb1 { 1764*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1"; 1765*724ba675SRob Herring nvidia,function = "i2c3"; 1766*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1767*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1768*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1769*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1770*724ba675SRob Herring }; 1771*724ba675SRob Herring 1772*724ba675SRob Herring cam_i2c_sda_pbb2 { 1773*724ba675SRob Herring nvidia,pins = "cam_i2c_sda_pbb2"; 1774*724ba675SRob Herring nvidia,function = "i2c3"; 1775*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1776*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1777*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1778*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1779*724ba675SRob Herring }; 1780*724ba675SRob Herring 1781*724ba675SRob Herring pbb3 { 1782*724ba675SRob Herring nvidia,pins = "pbb3"; 1783*724ba675SRob Herring nvidia,function = "vgp3"; 1784*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1785*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1786*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1787*724ba675SRob Herring }; 1788*724ba675SRob Herring 1789*724ba675SRob Herring pbb4 { 1790*724ba675SRob Herring nvidia,pins = "pbb4"; 1791*724ba675SRob Herring nvidia,function = "vgp4"; 1792*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1793*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1794*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1795*724ba675SRob Herring }; 1796*724ba675SRob Herring 1797*724ba675SRob Herring pbb5 { 1798*724ba675SRob Herring nvidia,pins = "pbb5"; 1799*724ba675SRob Herring nvidia,function = "vgp5"; 1800*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1801*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1802*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1803*724ba675SRob Herring }; 1804*724ba675SRob Herring 1805*724ba675SRob Herring pbb6 { 1806*724ba675SRob Herring nvidia,pins = "pbb6"; 1807*724ba675SRob Herring nvidia,function = "vgp6"; 1808*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1809*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1810*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1811*724ba675SRob Herring }; 1812*724ba675SRob Herring 1813*724ba675SRob Herring pbb7 { 1814*724ba675SRob Herring nvidia,pins = "pbb7"; 1815*724ba675SRob Herring nvidia,function = "i2s4"; 1816*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1817*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1818*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1819*724ba675SRob Herring }; 1820*724ba675SRob Herring 1821*724ba675SRob Herring cam_mclk_pcc0 { 1822*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0"; 1823*724ba675SRob Herring nvidia,function = "vi_alt3"; 1824*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1825*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1826*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1827*724ba675SRob Herring }; 1828*724ba675SRob Herring 1829*724ba675SRob Herring pcc1 { 1830*724ba675SRob Herring nvidia,pins = "pcc1"; 1831*724ba675SRob Herring nvidia,function = "i2s4"; 1832*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1833*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1834*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1835*724ba675SRob Herring }; 1836*724ba675SRob Herring 1837*724ba675SRob Herring pcc2 { 1838*724ba675SRob Herring nvidia,pins = "pcc2"; 1839*724ba675SRob Herring nvidia,function = "i2s4"; 1840*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1841*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1842*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1843*724ba675SRob Herring }; 1844*724ba675SRob Herring 1845*724ba675SRob Herring sdmmc4_rst_n_pcc3 { 1846*724ba675SRob Herring nvidia,pins = "sdmmc4_rst_n_pcc3"; 1847*724ba675SRob Herring nvidia,function = "sdmmc4"; 1848*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1849*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1850*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1851*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1852*724ba675SRob Herring }; 1853*724ba675SRob Herring 1854*724ba675SRob Herring sdmmc4_clk_pcc4 { 1855*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 1856*724ba675SRob Herring nvidia,function = "sdmmc4"; 1857*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1858*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1859*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1860*724ba675SRob Herring nvidia,io-reset = <TEGRA_PIN_DISABLE>; 1861*724ba675SRob Herring }; 1862*724ba675SRob Herring 1863*724ba675SRob Herring clk2_req_pcc5 { 1864*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 1865*724ba675SRob Herring nvidia,function = "dap"; 1866*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1867*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1868*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1869*724ba675SRob Herring }; 1870*724ba675SRob Herring 1871*724ba675SRob Herring pex_l2_rst_n_pcc6 { 1872*724ba675SRob Herring nvidia,pins = "pex_l2_rst_n_pcc6"; 1873*724ba675SRob Herring nvidia,function = "pcie"; 1874*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1875*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1876*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1877*724ba675SRob Herring }; 1878*724ba675SRob Herring 1879*724ba675SRob Herring pex_l2_clkreq_n_pcc7 { 1880*724ba675SRob Herring nvidia,pins = "pex_l2_clkreq_n_pcc7"; 1881*724ba675SRob Herring nvidia,function = "pcie"; 1882*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1883*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1884*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1885*724ba675SRob Herring }; 1886*724ba675SRob Herring 1887*724ba675SRob Herring pex_l0_prsnt_n_pdd0 { 1888*724ba675SRob Herring nvidia,pins = "pex_l0_prsnt_n_pdd0"; 1889*724ba675SRob Herring nvidia,function = "pcie"; 1890*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1891*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1892*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1893*724ba675SRob Herring }; 1894*724ba675SRob Herring 1895*724ba675SRob Herring pex_l0_rst_n_pdd1 { 1896*724ba675SRob Herring nvidia,pins = "pex_l0_rst_n_pdd1"; 1897*724ba675SRob Herring nvidia,function = "pcie"; 1898*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1899*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1900*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1901*724ba675SRob Herring }; 1902*724ba675SRob Herring 1903*724ba675SRob Herring pex_l0_clkreq_n_pdd2 { 1904*724ba675SRob Herring nvidia,pins = "pex_l0_clkreq_n_pdd2"; 1905*724ba675SRob Herring nvidia,function = "pcie"; 1906*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1907*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1908*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1909*724ba675SRob Herring }; 1910*724ba675SRob Herring 1911*724ba675SRob Herring pex_wake_n_pdd3 { 1912*724ba675SRob Herring nvidia,pins = "pex_wake_n_pdd3"; 1913*724ba675SRob Herring nvidia,function = "pcie"; 1914*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1915*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1916*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1917*724ba675SRob Herring }; 1918*724ba675SRob Herring 1919*724ba675SRob Herring pex_l1_prsnt_n_pdd4 { 1920*724ba675SRob Herring nvidia,pins = "pex_l1_prsnt_n_pdd4"; 1921*724ba675SRob Herring nvidia,function = "pcie"; 1922*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1923*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1924*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1925*724ba675SRob Herring }; 1926*724ba675SRob Herring 1927*724ba675SRob Herring pex_l1_rst_n_pdd5 { 1928*724ba675SRob Herring nvidia,pins = "pex_l1_rst_n_pdd5"; 1929*724ba675SRob Herring nvidia,function = "pcie"; 1930*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1931*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1932*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1933*724ba675SRob Herring }; 1934*724ba675SRob Herring 1935*724ba675SRob Herring pex_l1_clkreq_n_pdd6 { 1936*724ba675SRob Herring nvidia,pins = "pex_l1_clkreq_n_pdd6"; 1937*724ba675SRob Herring nvidia,function = "pcie"; 1938*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1939*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1940*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1941*724ba675SRob Herring }; 1942*724ba675SRob Herring 1943*724ba675SRob Herring pex_l2_prsnt_n_pdd7 { 1944*724ba675SRob Herring nvidia,pins = "pex_l2_prsnt_n_pdd7"; 1945*724ba675SRob Herring nvidia,function = "pcie"; 1946*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1947*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1948*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1949*724ba675SRob Herring }; 1950*724ba675SRob Herring 1951*724ba675SRob Herring clk3_out_pee0 { 1952*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 1953*724ba675SRob Herring nvidia,function = "extperiph3"; 1954*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1955*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1956*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1957*724ba675SRob Herring }; 1958*724ba675SRob Herring 1959*724ba675SRob Herring clk3_req_pee1 { 1960*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 1961*724ba675SRob Herring nvidia,function = "dev3"; 1962*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1963*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1964*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1965*724ba675SRob Herring }; 1966*724ba675SRob Herring 1967*724ba675SRob Herring clk1_req_pee2 { 1968*724ba675SRob Herring nvidia,pins = "clk1_req_pee2"; 1969*724ba675SRob Herring nvidia,function = "dap"; 1970*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1971*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1972*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1973*724ba675SRob Herring }; 1974*724ba675SRob Herring 1975*724ba675SRob Herring hdmi_cec_pee3 { 1976*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 1977*724ba675SRob Herring nvidia,function = "cec"; 1978*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1979*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1980*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1981*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1982*724ba675SRob Herring }; 1983*724ba675SRob Herring 1984*724ba675SRob Herring owr { 1985*724ba675SRob Herring nvidia,pins = "owr"; 1986*724ba675SRob Herring nvidia,function = "owr"; 1987*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1988*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1989*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1990*724ba675SRob Herring }; 1991*724ba675SRob Herring 1992*724ba675SRob Herring drive_groups { 1993*724ba675SRob Herring nvidia,pins = "drive_gma", 1994*724ba675SRob Herring "drive_gmb", 1995*724ba675SRob Herring "drive_gmc", 1996*724ba675SRob Herring "drive_gmd"; 1997*724ba675SRob Herring nvidia,pull-down-strength = <9>; 1998*724ba675SRob Herring nvidia,pull-up-strength = <9>; 1999*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 2000*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 2001*724ba675SRob Herring }; 2002*724ba675SRob Herring }; 2003*724ba675SRob Herring }; 2004*724ba675SRob Herring 2005*724ba675SRob Herring uartc: serial@70006200 { 2006*724ba675SRob Herring compatible = "nvidia,tegra30-hsuart"; 2007*724ba675SRob Herring /delete-property/ reg-shift; 2008*724ba675SRob Herring status = "okay"; 2009*724ba675SRob Herring 2010*724ba675SRob Herring nvidia,adjust-baud-rates = <0 9600 100>, 2011*724ba675SRob Herring <9600 115200 200>, 2012*724ba675SRob Herring <1000000 4000000 136>; 2013*724ba675SRob Herring 2014*724ba675SRob Herring /* Azurewave AW-NH660 BCM4330B1 */ 2015*724ba675SRob Herring bluetooth { 2016*724ba675SRob Herring compatible = "brcm,bcm4330-bt"; 2017*724ba675SRob Herring 2018*724ba675SRob Herring interrupt-parent = <&gpio>; 2019*724ba675SRob Herring interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 2020*724ba675SRob Herring interrupt-names = "host-wakeup"; 2021*724ba675SRob Herring 2022*724ba675SRob Herring max-speed = <4000000>; 2023*724ba675SRob Herring 2024*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 2025*724ba675SRob Herring clock-names = "txco"; 2026*724ba675SRob Herring 2027*724ba675SRob Herring vbat-supply = <&sys_3v3_reg>; 2028*724ba675SRob Herring vddio-supply = <&vdd_1v8>; 2029*724ba675SRob Herring 2030*724ba675SRob Herring shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 2031*724ba675SRob Herring device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 2032*724ba675SRob Herring }; 2033*724ba675SRob Herring }; 2034*724ba675SRob Herring 2035*724ba675SRob Herring uartd: serial@70006300 { 2036*724ba675SRob Herring status = "okay"; 2037*724ba675SRob Herring }; 2038*724ba675SRob Herring 2039*724ba675SRob Herring hdmi_ddc: i2c@7000c700 { 2040*724ba675SRob Herring status = "okay"; 2041*724ba675SRob Herring clock-frequency = <100000>; 2042*724ba675SRob Herring }; 2043*724ba675SRob Herring 2044*724ba675SRob Herring i2c@7000d000 { 2045*724ba675SRob Herring status = "okay"; 2046*724ba675SRob Herring clock-frequency = <400000>; 2047*724ba675SRob Herring 2048*724ba675SRob Herring pmic: pmic@2d { 2049*724ba675SRob Herring compatible = "ti,tps65911"; 2050*724ba675SRob Herring reg = <0x2d>; 2051*724ba675SRob Herring 2052*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2053*724ba675SRob Herring #interrupt-cells = <2>; 2054*724ba675SRob Herring interrupt-controller; 2055*724ba675SRob Herring wakeup-source; 2056*724ba675SRob Herring 2057*724ba675SRob Herring ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; 2058*724ba675SRob Herring ti,system-power-controller; 2059*724ba675SRob Herring ti,sleep-keep-ck32k; 2060*724ba675SRob Herring ti,sleep-enable; 2061*724ba675SRob Herring 2062*724ba675SRob Herring #gpio-cells = <2>; 2063*724ba675SRob Herring gpio-controller; 2064*724ba675SRob Herring 2065*724ba675SRob Herring vcc1-supply = <&vdd_5v0_reg>; 2066*724ba675SRob Herring vcc2-supply = <&vdd_5v0_reg>; 2067*724ba675SRob Herring vcc3-supply = <&vdd_1v8>; 2068*724ba675SRob Herring vcc4-supply = <&vdd_5v0_reg>; 2069*724ba675SRob Herring vcc5-supply = <&vdd_5v0_reg>; 2070*724ba675SRob Herring vcc6-supply = <&vdd2_reg>; 2071*724ba675SRob Herring vcc7-supply = <&vdd_5v0_reg>; 2072*724ba675SRob Herring vccio-supply = <&vdd_5v0_reg>; 2073*724ba675SRob Herring 2074*724ba675SRob Herring regulators { 2075*724ba675SRob Herring vdd1_reg: vdd1 { 2076*724ba675SRob Herring regulator-name = "vddio_ddr_1v2"; 2077*724ba675SRob Herring regulator-min-microvolt = <1200000>; 2078*724ba675SRob Herring regulator-max-microvolt = <1200000>; 2079*724ba675SRob Herring regulator-always-on; 2080*724ba675SRob Herring }; 2081*724ba675SRob Herring 2082*724ba675SRob Herring vdd2_reg: vdd2 { 2083*724ba675SRob Herring regulator-name = "vdd_1v5_gen"; 2084*724ba675SRob Herring regulator-min-microvolt = <1500000>; 2085*724ba675SRob Herring regulator-max-microvolt = <1500000>; 2086*724ba675SRob Herring regulator-always-on; 2087*724ba675SRob Herring }; 2088*724ba675SRob Herring 2089*724ba675SRob Herring vdd_cpu: vddctrl { 2090*724ba675SRob Herring regulator-name = "vdd_cpu,vdd_sys"; 2091*724ba675SRob Herring regulator-min-microvolt = <800000>; 2092*724ba675SRob Herring regulator-max-microvolt = <1270000>; 2093*724ba675SRob Herring regulator-coupled-with = <&vdd_core>; 2094*724ba675SRob Herring regulator-coupled-max-spread = <300000>; 2095*724ba675SRob Herring regulator-max-step-microvolt = <100000>; 2096*724ba675SRob Herring regulator-always-on; 2097*724ba675SRob Herring 2098*724ba675SRob Herring nvidia,tegra-cpu-regulator; 2099*724ba675SRob Herring }; 2100*724ba675SRob Herring 2101*724ba675SRob Herring vdd_1v8: vio { 2102*724ba675SRob Herring regulator-name = "vdd_1v8_gen"; 2103*724ba675SRob Herring regulator-min-microvolt = <1800000>; 2104*724ba675SRob Herring regulator-max-microvolt = <1800000>; 2105*724ba675SRob Herring regulator-always-on; 2106*724ba675SRob Herring }; 2107*724ba675SRob Herring 2108*724ba675SRob Herring ldo1_reg: ldo1 { 2109*724ba675SRob Herring regulator-name = "vdd_pexa,vdd_pexb"; 2110*724ba675SRob Herring regulator-min-microvolt = <1050000>; 2111*724ba675SRob Herring regulator-max-microvolt = <1050000>; 2112*724ba675SRob Herring regulator-always-on; 2113*724ba675SRob Herring }; 2114*724ba675SRob Herring 2115*724ba675SRob Herring ldo2_reg: ldo2 { 2116*724ba675SRob Herring regulator-name = "vdd_sata,avdd_plle"; 2117*724ba675SRob Herring regulator-min-microvolt = <1050000>; 2118*724ba675SRob Herring regulator-max-microvolt = <1050000>; 2119*724ba675SRob Herring regulator-always-on; 2120*724ba675SRob Herring }; 2121*724ba675SRob Herring 2122*724ba675SRob Herring /* LDO3 is not connected to anything */ 2123*724ba675SRob Herring 2124*724ba675SRob Herring ldo4_reg: ldo4 { 2125*724ba675SRob Herring regulator-name = "vdd_rtc"; 2126*724ba675SRob Herring regulator-min-microvolt = <1200000>; 2127*724ba675SRob Herring regulator-max-microvolt = <1200000>; 2128*724ba675SRob Herring regulator-always-on; 2129*724ba675SRob Herring }; 2130*724ba675SRob Herring 2131*724ba675SRob Herring ldo5_reg: ldo5 { 2132*724ba675SRob Herring regulator-name = "vddio_sdmmc,avdd_vdac"; 2133*724ba675SRob Herring regulator-min-microvolt = <1800000>; 2134*724ba675SRob Herring regulator-max-microvolt = <3300000>; 2135*724ba675SRob Herring regulator-always-on; 2136*724ba675SRob Herring }; 2137*724ba675SRob Herring 2138*724ba675SRob Herring ldo6_reg: ldo6 { 2139*724ba675SRob Herring regulator-name = "avdd_dsi_csi,pwrdet_mipi"; 2140*724ba675SRob Herring regulator-min-microvolt = <1200000>; 2141*724ba675SRob Herring regulator-max-microvolt = <1200000>; 2142*724ba675SRob Herring regulator-always-on; 2143*724ba675SRob Herring }; 2144*724ba675SRob Herring 2145*724ba675SRob Herring ldo7_reg: ldo7 { 2146*724ba675SRob Herring regulator-name = "vdd_pllm,x,u,a_p_c_s"; 2147*724ba675SRob Herring regulator-min-microvolt = <1200000>; 2148*724ba675SRob Herring regulator-max-microvolt = <1200000>; 2149*724ba675SRob Herring regulator-always-on; 2150*724ba675SRob Herring }; 2151*724ba675SRob Herring 2152*724ba675SRob Herring ldo8_reg: ldo8 { 2153*724ba675SRob Herring regulator-name = "vdd_ddr_hs"; 2154*724ba675SRob Herring regulator-min-microvolt = <1000000>; 2155*724ba675SRob Herring regulator-max-microvolt = <1000000>; 2156*724ba675SRob Herring regulator-always-on; 2157*724ba675SRob Herring }; 2158*724ba675SRob Herring }; 2159*724ba675SRob Herring }; 2160*724ba675SRob Herring 2161*724ba675SRob Herring cpu_temp: nct1008@4c { 2162*724ba675SRob Herring compatible = "onnn,nct1008"; 2163*724ba675SRob Herring reg = <0x4c>; 2164*724ba675SRob Herring vcc-supply = <&sys_3v3_reg>; 2165*724ba675SRob Herring 2166*724ba675SRob Herring interrupt-parent = <&gpio>; 2167*724ba675SRob Herring interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; 2168*724ba675SRob Herring 2169*724ba675SRob Herring #thermal-sensor-cells = <1>; 2170*724ba675SRob Herring }; 2171*724ba675SRob Herring 2172*724ba675SRob Herring vdd_core: tps62361@60 { 2173*724ba675SRob Herring compatible = "ti,tps62361"; 2174*724ba675SRob Herring reg = <0x60>; 2175*724ba675SRob Herring 2176*724ba675SRob Herring regulator-name = "vdd_core"; 2177*724ba675SRob Herring regulator-min-microvolt = <950000>; 2178*724ba675SRob Herring regulator-max-microvolt = <1350000>; 2179*724ba675SRob Herring regulator-coupled-with = <&vdd_cpu>; 2180*724ba675SRob Herring regulator-coupled-max-spread = <300000>; 2181*724ba675SRob Herring regulator-max-step-microvolt = <100000>; 2182*724ba675SRob Herring regulator-boot-on; 2183*724ba675SRob Herring regulator-always-on; 2184*724ba675SRob Herring ti,vsel0-state-high; 2185*724ba675SRob Herring ti,vsel1-state-high; 2186*724ba675SRob Herring ti,enable-vout-discharge; 2187*724ba675SRob Herring 2188*724ba675SRob Herring nvidia,tegra-core-regulator; 2189*724ba675SRob Herring }; 2190*724ba675SRob Herring }; 2191*724ba675SRob Herring 2192*724ba675SRob Herring pmc@7000e400 { 2193*724ba675SRob Herring status = "okay"; 2194*724ba675SRob Herring nvidia,invert-interrupt; 2195*724ba675SRob Herring nvidia,suspend-mode = <1>; 2196*724ba675SRob Herring nvidia,cpu-pwr-good-time = <2000>; 2197*724ba675SRob Herring nvidia,cpu-pwr-off-time = <200>; 2198*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 2199*724ba675SRob Herring nvidia,core-pwr-off-time = <458>; 2200*724ba675SRob Herring nvidia,core-power-req-active-high; 2201*724ba675SRob Herring nvidia,sys-clock-req-active-high; 2202*724ba675SRob Herring core-supply = <&vdd_core>; 2203*724ba675SRob Herring }; 2204*724ba675SRob Herring 2205*724ba675SRob Herring memory-controller@7000f000 { 2206*724ba675SRob Herring emc-timings-0 { 2207*724ba675SRob Herring nvidia,ram-code = <0>; /* Samsung RAM */ 2208*724ba675SRob Herring 2209*724ba675SRob Herring timing-25500000 { 2210*724ba675SRob Herring clock-frequency = <25500000>; 2211*724ba675SRob Herring nvidia,emem-configuration = < 2212*724ba675SRob Herring 0x00030003 /* MC_EMEM_ARB_CFG */ 2213*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2214*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2215*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2216*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2217*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2218*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2219*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2220*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2221*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2222*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2223*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2224*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2225*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2226*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2227*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2228*724ba675SRob Herring 0x75830303 /* MC_EMEM_ARB_MISC0 */ 2229*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2230*724ba675SRob Herring >; 2231*724ba675SRob Herring }; 2232*724ba675SRob Herring 2233*724ba675SRob Herring timing-51000000 { 2234*724ba675SRob Herring clock-frequency = <51000000>; 2235*724ba675SRob Herring nvidia,emem-configuration = < 2236*724ba675SRob Herring 0x00010003 /* MC_EMEM_ARB_CFG */ 2237*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2238*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2239*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2240*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2241*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2242*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2243*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2244*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2245*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2246*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2247*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2248*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2249*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2250*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2251*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2252*724ba675SRob Herring 0x74630303 /* MC_EMEM_ARB_MISC0 */ 2253*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2254*724ba675SRob Herring >; 2255*724ba675SRob Herring }; 2256*724ba675SRob Herring 2257*724ba675SRob Herring timing-102000000 { 2258*724ba675SRob Herring clock-frequency = <102000000>; 2259*724ba675SRob Herring nvidia,emem-configuration = < 2260*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_CFG */ 2261*724ba675SRob Herring 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2262*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2263*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2264*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ 2265*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2266*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 2267*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2268*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2269*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2270*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2271*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2272*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2273*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2274*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2275*724ba675SRob Herring 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ 2276*724ba675SRob Herring 0x73c30504 /* MC_EMEM_ARB_MISC0 */ 2277*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2278*724ba675SRob Herring >; 2279*724ba675SRob Herring }; 2280*724ba675SRob Herring 2281*724ba675SRob Herring timing-204000000 { 2282*724ba675SRob Herring clock-frequency = <204000000>; 2283*724ba675SRob Herring nvidia,emem-configuration = < 2284*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_CFG */ 2285*724ba675SRob Herring 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2286*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2287*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2288*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ 2289*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ 2290*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ 2291*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2292*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2293*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2294*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2295*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2296*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2297*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2298*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2299*724ba675SRob Herring 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ 2300*724ba675SRob Herring 0x73840a06 /* MC_EMEM_ARB_MISC0 */ 2301*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2302*724ba675SRob Herring >; 2303*724ba675SRob Herring }; 2304*724ba675SRob Herring 2305*724ba675SRob Herring timing-400000000 { 2306*724ba675SRob Herring clock-frequency = <400000000>; 2307*724ba675SRob Herring nvidia,emem-configuration = < 2308*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_CFG */ 2309*724ba675SRob Herring 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2310*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2311*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ 2312*724ba675SRob Herring 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ 2313*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ 2314*724ba675SRob Herring 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ 2315*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2316*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2317*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2318*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2319*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2320*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ 2321*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2322*724ba675SRob Herring 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ 2323*724ba675SRob Herring 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ 2324*724ba675SRob Herring 0x7086120a /* MC_EMEM_ARB_MISC0 */ 2325*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2326*724ba675SRob Herring >; 2327*724ba675SRob Herring }; 2328*724ba675SRob Herring 2329*724ba675SRob Herring timing-800000000 { 2330*724ba675SRob Herring clock-frequency = <800000000>; 2331*724ba675SRob Herring nvidia,emem-configuration = < 2332*724ba675SRob Herring 0x00000018 /* MC_EMEM_ARB_CFG */ 2333*724ba675SRob Herring 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2334*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ 2335*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ 2336*724ba675SRob Herring 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ 2337*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ 2338*724ba675SRob Herring 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ 2339*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ 2340*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2341*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2342*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2343*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2344*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ 2345*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ 2346*724ba675SRob Herring 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ 2347*724ba675SRob Herring 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ 2348*724ba675SRob Herring 0x712c2414 /* MC_EMEM_ARB_MISC0 */ 2349*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2350*724ba675SRob Herring >; 2351*724ba675SRob Herring }; 2352*724ba675SRob Herring }; 2353*724ba675SRob Herring 2354*724ba675SRob Herring emc-timings-1 { 2355*724ba675SRob Herring nvidia,ram-code = <1>; /* Hynix M RAM */ 2356*724ba675SRob Herring 2357*724ba675SRob Herring timing-25500000 { 2358*724ba675SRob Herring clock-frequency = <25500000>; 2359*724ba675SRob Herring nvidia,emem-configuration = < 2360*724ba675SRob Herring 0x00030003 /* MC_EMEM_ARB_CFG */ 2361*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2362*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2363*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2364*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2365*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2366*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2367*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2368*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2369*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2370*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2371*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2372*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2373*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2374*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2375*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2376*724ba675SRob Herring 0x75830303 /* MC_EMEM_ARB_MISC0 */ 2377*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2378*724ba675SRob Herring >; 2379*724ba675SRob Herring }; 2380*724ba675SRob Herring 2381*724ba675SRob Herring timing-51000000 { 2382*724ba675SRob Herring clock-frequency = <51000000>; 2383*724ba675SRob Herring nvidia,emem-configuration = < 2384*724ba675SRob Herring 0x00010003 /* MC_EMEM_ARB_CFG */ 2385*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2386*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2387*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2388*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2389*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2390*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2391*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2392*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2393*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2394*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2395*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2396*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2397*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2398*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2399*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2400*724ba675SRob Herring 0x74630303 /* MC_EMEM_ARB_MISC0 */ 2401*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2402*724ba675SRob Herring >; 2403*724ba675SRob Herring }; 2404*724ba675SRob Herring 2405*724ba675SRob Herring timing-102000000 { 2406*724ba675SRob Herring clock-frequency = <102000000>; 2407*724ba675SRob Herring nvidia,emem-configuration = < 2408*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_CFG */ 2409*724ba675SRob Herring 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2410*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2411*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2412*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ 2413*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2414*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 2415*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2416*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2417*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2418*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2419*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2420*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2421*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2422*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2423*724ba675SRob Herring 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ 2424*724ba675SRob Herring 0x73c30504 /* MC_EMEM_ARB_MISC0 */ 2425*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2426*724ba675SRob Herring >; 2427*724ba675SRob Herring }; 2428*724ba675SRob Herring 2429*724ba675SRob Herring timing-204000000 { 2430*724ba675SRob Herring clock-frequency = <204000000>; 2431*724ba675SRob Herring nvidia,emem-configuration = < 2432*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_CFG */ 2433*724ba675SRob Herring 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2434*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2435*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2436*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ 2437*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ 2438*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ 2439*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2440*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2441*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2442*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2443*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2444*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2445*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2446*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2447*724ba675SRob Herring 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ 2448*724ba675SRob Herring 0x73840a06 /* MC_EMEM_ARB_MISC0 */ 2449*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2450*724ba675SRob Herring >; 2451*724ba675SRob Herring }; 2452*724ba675SRob Herring 2453*724ba675SRob Herring timing-400000000 { 2454*724ba675SRob Herring clock-frequency = <400000000>; 2455*724ba675SRob Herring nvidia,emem-configuration = < 2456*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_CFG */ 2457*724ba675SRob Herring 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2458*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2459*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ 2460*724ba675SRob Herring 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ 2461*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ 2462*724ba675SRob Herring 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ 2463*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2464*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2465*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2466*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2467*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2468*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ 2469*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2470*724ba675SRob Herring 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ 2471*724ba675SRob Herring 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ 2472*724ba675SRob Herring 0x7086120a /* MC_EMEM_ARB_MISC0 */ 2473*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2474*724ba675SRob Herring >; 2475*724ba675SRob Herring }; 2476*724ba675SRob Herring 2477*724ba675SRob Herring timing-800000000 { 2478*724ba675SRob Herring clock-frequency = <800000000>; 2479*724ba675SRob Herring nvidia,emem-configuration = < 2480*724ba675SRob Herring 0x00000018 /* MC_EMEM_ARB_CFG */ 2481*724ba675SRob Herring 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2482*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ 2483*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ 2484*724ba675SRob Herring 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ 2485*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ 2486*724ba675SRob Herring 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ 2487*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ 2488*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2489*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2490*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2491*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2492*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ 2493*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ 2494*724ba675SRob Herring 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ 2495*724ba675SRob Herring 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ 2496*724ba675SRob Herring 0x712c2414 /* MC_EMEM_ARB_MISC0 */ 2497*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2498*724ba675SRob Herring >; 2499*724ba675SRob Herring }; 2500*724ba675SRob Herring }; 2501*724ba675SRob Herring 2502*724ba675SRob Herring emc-timings-2 { 2503*724ba675SRob Herring nvidia,ram-code = <2>; /* Hynix A RAM */ 2504*724ba675SRob Herring 2505*724ba675SRob Herring timing-25500000 { 2506*724ba675SRob Herring clock-frequency = <25500000>; 2507*724ba675SRob Herring nvidia,emem-configuration = < 2508*724ba675SRob Herring 0x00030003 /* MC_EMEM_ARB_CFG */ 2509*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2510*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2511*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2512*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2513*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2514*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2515*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2516*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2517*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2518*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2519*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2520*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2521*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2522*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2523*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2524*724ba675SRob Herring 0x75e30303 /* MC_EMEM_ARB_MISC0 */ 2525*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2526*724ba675SRob Herring >; 2527*724ba675SRob Herring }; 2528*724ba675SRob Herring 2529*724ba675SRob Herring timing-51000000 { 2530*724ba675SRob Herring clock-frequency = <51000000>; 2531*724ba675SRob Herring nvidia,emem-configuration = < 2532*724ba675SRob Herring 0x00010003 /* MC_EMEM_ARB_CFG */ 2533*724ba675SRob Herring 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2534*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2535*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2536*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 2537*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2538*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 2539*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2540*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2541*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2542*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2543*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2544*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2545*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2546*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2547*724ba675SRob Herring 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ 2548*724ba675SRob Herring 0x74e30303 /* MC_EMEM_ARB_MISC0 */ 2549*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2550*724ba675SRob Herring >; 2551*724ba675SRob Herring }; 2552*724ba675SRob Herring 2553*724ba675SRob Herring timing-102000000 { 2554*724ba675SRob Herring clock-frequency = <102000000>; 2555*724ba675SRob Herring nvidia,emem-configuration = < 2556*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_CFG */ 2557*724ba675SRob Herring 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2558*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2559*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2560*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ 2561*724ba675SRob Herring 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 2562*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 2563*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2564*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2565*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2566*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2567*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2568*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2569*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2570*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2571*724ba675SRob Herring 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ 2572*724ba675SRob Herring 0x74430504 /* MC_EMEM_ARB_MISC0 */ 2573*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2574*724ba675SRob Herring >; 2575*724ba675SRob Herring }; 2576*724ba675SRob Herring 2577*724ba675SRob Herring timing-204000000 { 2578*724ba675SRob Herring clock-frequency = <204000000>; 2579*724ba675SRob Herring nvidia,emem-configuration = < 2580*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_CFG */ 2581*724ba675SRob Herring 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2582*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2583*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 2584*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ 2585*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ 2586*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ 2587*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2588*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2589*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2590*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2591*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ 2592*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ 2593*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2594*724ba675SRob Herring 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ 2595*724ba675SRob Herring 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ 2596*724ba675SRob Herring 0x74040a06 /* MC_EMEM_ARB_MISC0 */ 2597*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2598*724ba675SRob Herring >; 2599*724ba675SRob Herring }; 2600*724ba675SRob Herring 2601*724ba675SRob Herring timing-400000000 { 2602*724ba675SRob Herring clock-frequency = <400000000>; 2603*724ba675SRob Herring nvidia,emem-configuration = < 2604*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_CFG */ 2605*724ba675SRob Herring 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2606*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 2607*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ 2608*724ba675SRob Herring 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ 2609*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ 2610*724ba675SRob Herring 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ 2611*724ba675SRob Herring 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 2612*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2613*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2614*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2615*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2616*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ 2617*724ba675SRob Herring 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 2618*724ba675SRob Herring 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ 2619*724ba675SRob Herring 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ 2620*724ba675SRob Herring 0x7086120a /* MC_EMEM_ARB_MISC0 */ 2621*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2622*724ba675SRob Herring >; 2623*724ba675SRob Herring }; 2624*724ba675SRob Herring 2625*724ba675SRob Herring timing-800000000 { 2626*724ba675SRob Herring clock-frequency = <800000000>; 2627*724ba675SRob Herring nvidia,emem-configuration = < 2628*724ba675SRob Herring 0x00000018 /* MC_EMEM_ARB_CFG */ 2629*724ba675SRob Herring 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 2630*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ 2631*724ba675SRob Herring 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ 2632*724ba675SRob Herring 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ 2633*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ 2634*724ba675SRob Herring 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ 2635*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ 2636*724ba675SRob Herring 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 2637*724ba675SRob Herring 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ 2638*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ 2639*724ba675SRob Herring 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 2640*724ba675SRob Herring 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ 2641*724ba675SRob Herring 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ 2642*724ba675SRob Herring 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ 2643*724ba675SRob Herring 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ 2644*724ba675SRob Herring 0x712c2414 /* MC_EMEM_ARB_MISC0 */ 2645*724ba675SRob Herring 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 2646*724ba675SRob Herring >; 2647*724ba675SRob Herring }; 2648*724ba675SRob Herring }; 2649*724ba675SRob Herring }; 2650*724ba675SRob Herring 2651*724ba675SRob Herring memory-controller@7000f400 { 2652*724ba675SRob Herring emc-timings-0 { 2653*724ba675SRob Herring nvidia,ram-code = <0>; /* Samsung RAM */ 2654*724ba675SRob Herring 2655*724ba675SRob Herring timing-25500000 { 2656*724ba675SRob Herring clock-frequency = <25500000>; 2657*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2658*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 2659*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 2660*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 2661*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 2662*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2663*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2664*724ba675SRob Herring nvidia,emc-configuration = < 2665*724ba675SRob Herring 0x00000001 /* EMC_RC */ 2666*724ba675SRob Herring 0x00000006 /* EMC_RFC */ 2667*724ba675SRob Herring 0x00000000 /* EMC_RAS */ 2668*724ba675SRob Herring 0x00000000 /* EMC_RP */ 2669*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 2670*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 2671*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 2672*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 2673*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 2674*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 2675*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 2676*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 2677*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 2678*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 2679*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 2680*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 2681*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 2682*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 2683*724ba675SRob Herring 0x000000c0 /* EMC_REFRESH */ 2684*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 2685*724ba675SRob Herring 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ 2686*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 2687*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 2688*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 2689*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 2690*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 2691*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 2692*724ba675SRob Herring 0x00000007 /* EMC_TXSR */ 2693*724ba675SRob Herring 0x00000007 /* EMC_TXSRDLL */ 2694*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 2695*724ba675SRob Herring 0x00000002 /* EMC_TFAW */ 2696*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 2697*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 2698*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 2699*724ba675SRob Herring 0x000000c7 /* EMC_TREFBW */ 2700*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 2701*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 2702*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 2703*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 2704*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 2705*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 2706*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 2707*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 2708*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 2709*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 2710*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 2711*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 2712*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 2713*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 2714*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 2715*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 2716*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 2717*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 2718*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 2719*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 2720*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 2721*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 2722*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 2723*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 2724*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 2725*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 2726*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 2727*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 2728*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 2729*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 2730*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 2731*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 2732*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 2733*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 2734*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 2735*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 2736*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 2737*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 2738*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 2739*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 2740*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 2741*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 2742*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 2743*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 2744*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 2745*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 2746*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 2747*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 2748*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 2749*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 2750*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 2751*724ba675SRob Herring 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ 2752*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 2753*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 2754*724ba675SRob Herring >; 2755*724ba675SRob Herring }; 2756*724ba675SRob Herring 2757*724ba675SRob Herring timing-51000000 { 2758*724ba675SRob Herring clock-frequency = <51000000>; 2759*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2760*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 2761*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 2762*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 2763*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 2764*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2765*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2766*724ba675SRob Herring nvidia,emc-configuration = < 2767*724ba675SRob Herring 0x00000002 /* EMC_RC */ 2768*724ba675SRob Herring 0x0000000d /* EMC_RFC */ 2769*724ba675SRob Herring 0x00000001 /* EMC_RAS */ 2770*724ba675SRob Herring 0x00000000 /* EMC_RP */ 2771*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 2772*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 2773*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 2774*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 2775*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 2776*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 2777*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 2778*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 2779*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 2780*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 2781*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 2782*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 2783*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 2784*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 2785*724ba675SRob Herring 0x00000181 /* EMC_REFRESH */ 2786*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 2787*724ba675SRob Herring 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ 2788*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 2789*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 2790*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 2791*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 2792*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 2793*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 2794*724ba675SRob Herring 0x0000000e /* EMC_TXSR */ 2795*724ba675SRob Herring 0x0000000e /* EMC_TXSRDLL */ 2796*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 2797*724ba675SRob Herring 0x00000003 /* EMC_TFAW */ 2798*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 2799*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 2800*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 2801*724ba675SRob Herring 0x0000018e /* EMC_TREFBW */ 2802*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 2803*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 2804*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 2805*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 2806*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 2807*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 2808*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 2809*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 2810*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 2811*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 2812*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 2813*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 2814*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 2815*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 2816*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 2817*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 2818*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 2819*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 2820*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 2821*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 2822*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 2823*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 2824*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 2825*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 2826*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 2827*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 2828*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 2829*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 2830*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 2831*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 2832*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 2833*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 2834*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 2835*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 2836*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 2837*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 2838*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 2839*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 2840*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 2841*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 2842*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 2843*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 2844*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 2845*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 2846*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 2847*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 2848*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 2849*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 2850*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 2851*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 2852*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 2853*724ba675SRob Herring 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ 2854*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 2855*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 2856*724ba675SRob Herring >; 2857*724ba675SRob Herring }; 2858*724ba675SRob Herring 2859*724ba675SRob Herring timing-102000000 { 2860*724ba675SRob Herring clock-frequency = <102000000>; 2861*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2862*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 2863*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 2864*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 2865*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 2866*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2867*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2868*724ba675SRob Herring nvidia,emc-configuration = < 2869*724ba675SRob Herring 0x00000004 /* EMC_RC */ 2870*724ba675SRob Herring 0x0000001a /* EMC_RFC */ 2871*724ba675SRob Herring 0x00000003 /* EMC_RAS */ 2872*724ba675SRob Herring 0x00000001 /* EMC_RP */ 2873*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 2874*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 2875*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 2876*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 2877*724ba675SRob Herring 0x00000001 /* EMC_RD_RCD */ 2878*724ba675SRob Herring 0x00000001 /* EMC_WR_RCD */ 2879*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 2880*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 2881*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 2882*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 2883*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 2884*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 2885*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 2886*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 2887*724ba675SRob Herring 0x00000303 /* EMC_REFRESH */ 2888*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 2889*724ba675SRob Herring 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ 2890*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 2891*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 2892*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 2893*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 2894*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 2895*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 2896*724ba675SRob Herring 0x0000001c /* EMC_TXSR */ 2897*724ba675SRob Herring 0x0000001c /* EMC_TXSRDLL */ 2898*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 2899*724ba675SRob Herring 0x00000005 /* EMC_TFAW */ 2900*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 2901*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 2902*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 2903*724ba675SRob Herring 0x0000031c /* EMC_TREFBW */ 2904*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 2905*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 2906*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 2907*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 2908*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 2909*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 2910*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 2911*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 2912*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 2913*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 2914*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 2915*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 2916*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 2917*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 2918*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 2919*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 2920*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 2921*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 2922*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 2923*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 2924*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 2925*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 2926*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 2927*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 2928*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 2929*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 2930*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 2931*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 2932*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 2933*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 2934*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 2935*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 2936*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 2937*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 2938*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 2939*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 2940*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 2941*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 2942*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 2943*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 2944*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 2945*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 2946*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 2947*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 2948*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 2949*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 2950*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 2951*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 2952*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 2953*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 2954*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 2955*724ba675SRob Herring 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ 2956*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 2957*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 2958*724ba675SRob Herring >; 2959*724ba675SRob Herring }; 2960*724ba675SRob Herring 2961*724ba675SRob Herring timing-204000000 { 2962*724ba675SRob Herring clock-frequency = <204000000>; 2963*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2964*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 2965*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 2966*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 2967*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 2968*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2969*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2970*724ba675SRob Herring nvidia,emc-configuration = < 2971*724ba675SRob Herring 0x00000009 /* EMC_RC */ 2972*724ba675SRob Herring 0x00000035 /* EMC_RFC */ 2973*724ba675SRob Herring 0x00000007 /* EMC_RAS */ 2974*724ba675SRob Herring 0x00000002 /* EMC_RP */ 2975*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 2976*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 2977*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 2978*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 2979*724ba675SRob Herring 0x00000002 /* EMC_RD_RCD */ 2980*724ba675SRob Herring 0x00000002 /* EMC_WR_RCD */ 2981*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 2982*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 2983*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 2984*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 2985*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 2986*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 2987*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 2988*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 2989*724ba675SRob Herring 0x00000607 /* EMC_REFRESH */ 2990*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 2991*724ba675SRob Herring 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ 2992*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 2993*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 2994*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 2995*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 2996*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 2997*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 2998*724ba675SRob Herring 0x00000038 /* EMC_TXSR */ 2999*724ba675SRob Herring 0x00000038 /* EMC_TXSRDLL */ 3000*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3001*724ba675SRob Herring 0x00000009 /* EMC_TFAW */ 3002*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3003*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3004*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3005*724ba675SRob Herring 0x00000638 /* EMC_TREFBW */ 3006*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3007*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 3008*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3009*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3010*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3011*724ba675SRob Herring 0x004400a4 /* EMC_CFG_DIG_DLL */ 3012*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3013*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS0 */ 3014*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS1 */ 3015*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS2 */ 3016*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS3 */ 3017*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS4 */ 3018*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS5 */ 3019*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS6 */ 3020*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS7 */ 3021*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3022*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3023*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3024*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3025*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3026*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3027*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3028*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3029*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3030*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3031*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3032*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3033*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3034*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3035*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3036*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3037*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ0 */ 3038*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ1 */ 3039*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ2 */ 3040*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ3 */ 3041*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3042*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3043*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3044*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3045*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3046*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3047*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3048*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3049*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3050*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3051*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3052*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3053*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3054*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3055*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3056*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3057*724ba675SRob Herring 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ 3058*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3059*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3060*724ba675SRob Herring >; 3061*724ba675SRob Herring }; 3062*724ba675SRob Herring 3063*724ba675SRob Herring timing-400000000 { 3064*724ba675SRob Herring clock-frequency = <400000000>; 3065*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3066*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 3067*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200000>; 3068*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000521>; 3069*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3070*724ba675SRob Herring nvidia,emc-configuration = < 3071*724ba675SRob Herring 0x00000012 /* EMC_RC */ 3072*724ba675SRob Herring 0x00000066 /* EMC_RFC */ 3073*724ba675SRob Herring 0x0000000c /* EMC_RAS */ 3074*724ba675SRob Herring 0x00000004 /* EMC_RP */ 3075*724ba675SRob Herring 0x00000003 /* EMC_R2W */ 3076*724ba675SRob Herring 0x00000008 /* EMC_W2R */ 3077*724ba675SRob Herring 0x00000002 /* EMC_R2P */ 3078*724ba675SRob Herring 0x0000000a /* EMC_W2P */ 3079*724ba675SRob Herring 0x00000004 /* EMC_RD_RCD */ 3080*724ba675SRob Herring 0x00000004 /* EMC_WR_RCD */ 3081*724ba675SRob Herring 0x00000002 /* EMC_RRD */ 3082*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3083*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3084*724ba675SRob Herring 0x00000004 /* EMC_WDV */ 3085*724ba675SRob Herring 0x00000006 /* EMC_QUSE */ 3086*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3087*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3088*724ba675SRob Herring 0x0000000c /* EMC_RDV */ 3089*724ba675SRob Herring 0x00000bf0 /* EMC_REFRESH */ 3090*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3091*724ba675SRob Herring 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ 3092*724ba675SRob Herring 0x00000001 /* EMC_PDEX2WR */ 3093*724ba675SRob Herring 0x00000008 /* EMC_PDEX2RD */ 3094*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3095*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3096*724ba675SRob Herring 0x00000008 /* EMC_AR2PDEN */ 3097*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3098*724ba675SRob Herring 0x0000006c /* EMC_TXSR */ 3099*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 3100*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3101*724ba675SRob Herring 0x00000010 /* EMC_TFAW */ 3102*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3103*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3104*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3105*724ba675SRob Herring 0x00000c30 /* EMC_TREFBW */ 3106*724ba675SRob Herring 0x00000000 /* EMC_QUSE_EXTRA */ 3107*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3108*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3109*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3110*724ba675SRob Herring 0x00007088 /* EMC_FBIO_CFG5 */ 3111*724ba675SRob Herring 0x001d0084 /* EMC_CFG_DIG_DLL */ 3112*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3113*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ 3114*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ 3115*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ 3116*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ 3117*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ 3118*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ 3119*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ 3120*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ 3121*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3122*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3123*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3124*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3125*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3126*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3127*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3128*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3129*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3130*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3131*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3132*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3133*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3134*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3135*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3136*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3137*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ0 */ 3138*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ1 */ 3139*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ2 */ 3140*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ3 */ 3141*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3142*724ba675SRob Herring 0x0800013d /* EMC_XM2DQSPADCTRL2 */ 3143*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3144*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3145*724ba675SRob Herring 0x01f1f508 /* EMC_XM2COMPPADCTRL */ 3146*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3147*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3148*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 3149*724ba675SRob Herring 0x08000021 /* EMC_XM2DQSPADCTRL3 */ 3150*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3151*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3152*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3153*724ba675SRob Herring 0x0158000c /* EMC_MRS_WAIT_CNT */ 3154*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3155*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3156*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3157*724ba675SRob Herring 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ 3158*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3159*724ba675SRob Herring 0xff00ff89 /* EMC_CFG_RSV */ 3160*724ba675SRob Herring >; 3161*724ba675SRob Herring }; 3162*724ba675SRob Herring 3163*724ba675SRob Herring timing-800000000 { 3164*724ba675SRob Herring clock-frequency = <800000000>; 3165*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3166*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 3167*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200018>; 3168*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000d71>; 3169*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3170*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3171*724ba675SRob Herring nvidia,emc-configuration = < 3172*724ba675SRob Herring 0x00000025 /* EMC_RC */ 3173*724ba675SRob Herring 0x000000ce /* EMC_RFC */ 3174*724ba675SRob Herring 0x0000001a /* EMC_RAS */ 3175*724ba675SRob Herring 0x00000009 /* EMC_RP */ 3176*724ba675SRob Herring 0x00000005 /* EMC_R2W */ 3177*724ba675SRob Herring 0x0000000d /* EMC_W2R */ 3178*724ba675SRob Herring 0x00000004 /* EMC_R2P */ 3179*724ba675SRob Herring 0x00000013 /* EMC_W2P */ 3180*724ba675SRob Herring 0x00000009 /* EMC_RD_RCD */ 3181*724ba675SRob Herring 0x00000009 /* EMC_WR_RCD */ 3182*724ba675SRob Herring 0x00000004 /* EMC_RRD */ 3183*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3184*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3185*724ba675SRob Herring 0x00000007 /* EMC_WDV */ 3186*724ba675SRob Herring 0x0000000a /* EMC_QUSE */ 3187*724ba675SRob Herring 0x00000009 /* EMC_QRST */ 3188*724ba675SRob Herring 0x0000000b /* EMC_QSAFE */ 3189*724ba675SRob Herring 0x00000011 /* EMC_RDV */ 3190*724ba675SRob Herring 0x00001820 /* EMC_REFRESH */ 3191*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3192*724ba675SRob Herring 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ 3193*724ba675SRob Herring 0x00000003 /* EMC_PDEX2WR */ 3194*724ba675SRob Herring 0x00000012 /* EMC_PDEX2RD */ 3195*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3196*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3197*724ba675SRob Herring 0x0000000f /* EMC_AR2PDEN */ 3198*724ba675SRob Herring 0x00000018 /* EMC_RW2PDEN */ 3199*724ba675SRob Herring 0x000000d8 /* EMC_TXSR */ 3200*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 3201*724ba675SRob Herring 0x00000005 /* EMC_TCKE */ 3202*724ba675SRob Herring 0x00000020 /* EMC_TFAW */ 3203*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3204*724ba675SRob Herring 0x00000007 /* EMC_TCLKSTABLE */ 3205*724ba675SRob Herring 0x00000008 /* EMC_TCLKSTOP */ 3206*724ba675SRob Herring 0x00001860 /* EMC_TREFBW */ 3207*724ba675SRob Herring 0x0000000b /* EMC_QUSE_EXTRA */ 3208*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 3209*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3210*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3211*724ba675SRob Herring 0x00005088 /* EMC_FBIO_CFG5 */ 3212*724ba675SRob Herring 0xf0070191 /* EMC_CFG_DIG_DLL */ 3213*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3214*724ba675SRob Herring 0x0000800a /* EMC_DLL_XFORM_DQS0 */ 3215*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS1 */ 3216*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS2 */ 3217*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS3 */ 3218*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS4 */ 3219*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS5 */ 3220*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS6 */ 3221*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS7 */ 3222*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ 3223*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ 3224*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ 3225*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ 3226*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ 3227*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ 3228*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ 3229*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ 3230*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3231*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3232*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3233*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3234*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3235*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3236*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3237*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3238*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ0 */ 3239*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ1 */ 3240*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ2 */ 3241*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ3 */ 3242*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3243*724ba675SRob Herring 0x0600013d /* EMC_XM2DQSPADCTRL2 */ 3244*724ba675SRob Herring 0x22220000 /* EMC_XM2DQPADCTRL2 */ 3245*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3246*724ba675SRob Herring 0x01f1f501 /* EMC_XM2COMPPADCTRL */ 3247*724ba675SRob Herring 0x07077404 /* EMC_XM2VTTGENPADCTRL */ 3248*724ba675SRob Herring 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ 3249*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 3250*724ba675SRob Herring 0x08000021 /* EMC_XM2DQSPADCTRL3 */ 3251*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3252*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3253*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3254*724ba675SRob Herring 0x00f0000c /* EMC_MRS_WAIT_CNT */ 3255*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3256*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3257*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3258*724ba675SRob Herring 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ 3259*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3260*724ba675SRob Herring 0xff00ff49 /* EMC_CFG_RSV */ 3261*724ba675SRob Herring >; 3262*724ba675SRob Herring }; 3263*724ba675SRob Herring }; 3264*724ba675SRob Herring 3265*724ba675SRob Herring emc-timings-1 { 3266*724ba675SRob Herring nvidia,ram-code = <1>; /* Hynix M RAM */ 3267*724ba675SRob Herring 3268*724ba675SRob Herring timing-25500000 { 3269*724ba675SRob Herring clock-frequency = <25500000>; 3270*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3271*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3272*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3273*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3274*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3275*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3276*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3277*724ba675SRob Herring nvidia,emc-configuration = < 3278*724ba675SRob Herring 0x00000001 /* EMC_RC */ 3279*724ba675SRob Herring 0x00000006 /* EMC_RFC */ 3280*724ba675SRob Herring 0x00000000 /* EMC_RAS */ 3281*724ba675SRob Herring 0x00000000 /* EMC_RP */ 3282*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3283*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3284*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 3285*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 3286*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 3287*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 3288*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 3289*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3290*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3291*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 3292*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 3293*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3294*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3295*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 3296*724ba675SRob Herring 0x000000c0 /* EMC_REFRESH */ 3297*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3298*724ba675SRob Herring 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ 3299*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 3300*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 3301*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3302*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3303*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 3304*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3305*724ba675SRob Herring 0x00000007 /* EMC_TXSR */ 3306*724ba675SRob Herring 0x00000007 /* EMC_TXSRDLL */ 3307*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3308*724ba675SRob Herring 0x00000002 /* EMC_TFAW */ 3309*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3310*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3311*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3312*724ba675SRob Herring 0x000000c7 /* EMC_TREFBW */ 3313*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3314*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3315*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3316*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3317*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3318*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 3319*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3320*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 3321*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 3322*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 3323*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 3324*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 3325*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 3326*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 3327*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 3328*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3329*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3330*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3331*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3332*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3333*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3334*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3335*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3336*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3337*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3338*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3339*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3340*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3341*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3342*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3343*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3344*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 3345*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 3346*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 3347*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 3348*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3349*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3350*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3351*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3352*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3353*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3354*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3355*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3356*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3357*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3358*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 3359*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 3360*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3361*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3362*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3363*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3364*724ba675SRob Herring 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ 3365*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3366*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3367*724ba675SRob Herring >; 3368*724ba675SRob Herring }; 3369*724ba675SRob Herring 3370*724ba675SRob Herring timing-51000000 { 3371*724ba675SRob Herring clock-frequency = <51000000>; 3372*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3373*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3374*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3375*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3376*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3377*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3378*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3379*724ba675SRob Herring nvidia,emc-configuration = < 3380*724ba675SRob Herring 0x00000002 /* EMC_RC */ 3381*724ba675SRob Herring 0x0000000d /* EMC_RFC */ 3382*724ba675SRob Herring 0x00000001 /* EMC_RAS */ 3383*724ba675SRob Herring 0x00000000 /* EMC_RP */ 3384*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3385*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3386*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 3387*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 3388*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 3389*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 3390*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 3391*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3392*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3393*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 3394*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 3395*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3396*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3397*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 3398*724ba675SRob Herring 0x00000181 /* EMC_REFRESH */ 3399*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3400*724ba675SRob Herring 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ 3401*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 3402*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 3403*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3404*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3405*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 3406*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3407*724ba675SRob Herring 0x0000000e /* EMC_TXSR */ 3408*724ba675SRob Herring 0x0000000e /* EMC_TXSRDLL */ 3409*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3410*724ba675SRob Herring 0x00000003 /* EMC_TFAW */ 3411*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3412*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3413*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3414*724ba675SRob Herring 0x0000018e /* EMC_TREFBW */ 3415*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3416*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3417*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3418*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3419*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3420*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 3421*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3422*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 3423*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 3424*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 3425*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 3426*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 3427*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 3428*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 3429*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 3430*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3431*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3432*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3433*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3434*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3435*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3436*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3437*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3438*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3439*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3440*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3441*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3442*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3443*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3444*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3445*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3446*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 3447*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 3448*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 3449*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 3450*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3451*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3452*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3453*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3454*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3455*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3456*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3457*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3458*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3459*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3460*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 3461*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 3462*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3463*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3464*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3465*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3466*724ba675SRob Herring 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ 3467*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3468*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3469*724ba675SRob Herring >; 3470*724ba675SRob Herring }; 3471*724ba675SRob Herring 3472*724ba675SRob Herring timing-102000000 { 3473*724ba675SRob Herring clock-frequency = <102000000>; 3474*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3475*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3476*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3477*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3478*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3479*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3480*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3481*724ba675SRob Herring nvidia,emc-configuration = < 3482*724ba675SRob Herring 0x00000004 /* EMC_RC */ 3483*724ba675SRob Herring 0x0000001a /* EMC_RFC */ 3484*724ba675SRob Herring 0x00000003 /* EMC_RAS */ 3485*724ba675SRob Herring 0x00000001 /* EMC_RP */ 3486*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3487*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3488*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 3489*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 3490*724ba675SRob Herring 0x00000001 /* EMC_RD_RCD */ 3491*724ba675SRob Herring 0x00000001 /* EMC_WR_RCD */ 3492*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 3493*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3494*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3495*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 3496*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 3497*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3498*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3499*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 3500*724ba675SRob Herring 0x00000303 /* EMC_REFRESH */ 3501*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3502*724ba675SRob Herring 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ 3503*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 3504*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 3505*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3506*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3507*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 3508*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3509*724ba675SRob Herring 0x0000001c /* EMC_TXSR */ 3510*724ba675SRob Herring 0x0000001c /* EMC_TXSRDLL */ 3511*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3512*724ba675SRob Herring 0x00000005 /* EMC_TFAW */ 3513*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3514*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3515*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3516*724ba675SRob Herring 0x0000031c /* EMC_TREFBW */ 3517*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3518*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3519*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3520*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3521*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3522*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 3523*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3524*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 3525*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 3526*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 3527*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 3528*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 3529*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 3530*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 3531*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 3532*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3533*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3534*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3535*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3536*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3537*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3538*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3539*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3540*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3541*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3542*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3543*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3544*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3545*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3546*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3547*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3548*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 3549*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 3550*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 3551*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 3552*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3553*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3554*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3555*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3556*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3557*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3558*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3559*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3560*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3561*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3562*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 3563*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 3564*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3565*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3566*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3567*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3568*724ba675SRob Herring 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ 3569*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3570*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3571*724ba675SRob Herring >; 3572*724ba675SRob Herring }; 3573*724ba675SRob Herring 3574*724ba675SRob Herring timing-204000000 { 3575*724ba675SRob Herring clock-frequency = <204000000>; 3576*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3577*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3578*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3579*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3580*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3581*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3582*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3583*724ba675SRob Herring nvidia,emc-configuration = < 3584*724ba675SRob Herring 0x00000009 /* EMC_RC */ 3585*724ba675SRob Herring 0x00000035 /* EMC_RFC */ 3586*724ba675SRob Herring 0x00000007 /* EMC_RAS */ 3587*724ba675SRob Herring 0x00000002 /* EMC_RP */ 3588*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3589*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3590*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 3591*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 3592*724ba675SRob Herring 0x00000002 /* EMC_RD_RCD */ 3593*724ba675SRob Herring 0x00000002 /* EMC_WR_RCD */ 3594*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 3595*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3596*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3597*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 3598*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 3599*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3600*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3601*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 3602*724ba675SRob Herring 0x00000607 /* EMC_REFRESH */ 3603*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3604*724ba675SRob Herring 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ 3605*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 3606*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 3607*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3608*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3609*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 3610*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3611*724ba675SRob Herring 0x00000038 /* EMC_TXSR */ 3612*724ba675SRob Herring 0x00000038 /* EMC_TXSRDLL */ 3613*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3614*724ba675SRob Herring 0x00000009 /* EMC_TFAW */ 3615*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3616*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3617*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3618*724ba675SRob Herring 0x00000638 /* EMC_TREFBW */ 3619*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3620*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 3621*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3622*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3623*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3624*724ba675SRob Herring 0x004400a4 /* EMC_CFG_DIG_DLL */ 3625*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3626*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS0 */ 3627*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS1 */ 3628*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS2 */ 3629*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS3 */ 3630*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS4 */ 3631*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS5 */ 3632*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS6 */ 3633*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS7 */ 3634*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3635*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3636*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3637*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3638*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3639*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3640*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3641*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3642*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3643*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3644*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3645*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3646*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3647*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3648*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3649*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3650*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ0 */ 3651*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ1 */ 3652*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ2 */ 3653*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ3 */ 3654*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3655*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3656*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3657*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3658*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3659*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3660*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3661*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3662*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3663*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3664*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3665*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3666*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3667*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3668*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3669*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3670*724ba675SRob Herring 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ 3671*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3672*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3673*724ba675SRob Herring >; 3674*724ba675SRob Herring }; 3675*724ba675SRob Herring 3676*724ba675SRob Herring timing-400000000 { 3677*724ba675SRob Herring clock-frequency = <400000000>; 3678*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3679*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 3680*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200000>; 3681*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000521>; 3682*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3683*724ba675SRob Herring nvidia,emc-configuration = < 3684*724ba675SRob Herring 0x00000012 /* EMC_RC */ 3685*724ba675SRob Herring 0x00000066 /* EMC_RFC */ 3686*724ba675SRob Herring 0x0000000c /* EMC_RAS */ 3687*724ba675SRob Herring 0x00000004 /* EMC_RP */ 3688*724ba675SRob Herring 0x00000003 /* EMC_R2W */ 3689*724ba675SRob Herring 0x00000008 /* EMC_W2R */ 3690*724ba675SRob Herring 0x00000002 /* EMC_R2P */ 3691*724ba675SRob Herring 0x0000000a /* EMC_W2P */ 3692*724ba675SRob Herring 0x00000004 /* EMC_RD_RCD */ 3693*724ba675SRob Herring 0x00000004 /* EMC_WR_RCD */ 3694*724ba675SRob Herring 0x00000002 /* EMC_RRD */ 3695*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3696*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3697*724ba675SRob Herring 0x00000004 /* EMC_WDV */ 3698*724ba675SRob Herring 0x00000006 /* EMC_QUSE */ 3699*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3700*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3701*724ba675SRob Herring 0x0000000c /* EMC_RDV */ 3702*724ba675SRob Herring 0x00000bf0 /* EMC_REFRESH */ 3703*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3704*724ba675SRob Herring 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ 3705*724ba675SRob Herring 0x00000001 /* EMC_PDEX2WR */ 3706*724ba675SRob Herring 0x00000008 /* EMC_PDEX2RD */ 3707*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3708*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3709*724ba675SRob Herring 0x00000008 /* EMC_AR2PDEN */ 3710*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3711*724ba675SRob Herring 0x0000006c /* EMC_TXSR */ 3712*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 3713*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3714*724ba675SRob Herring 0x00000010 /* EMC_TFAW */ 3715*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3716*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3717*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3718*724ba675SRob Herring 0x00000c30 /* EMC_TREFBW */ 3719*724ba675SRob Herring 0x00000000 /* EMC_QUSE_EXTRA */ 3720*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3721*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3722*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3723*724ba675SRob Herring 0x00007088 /* EMC_FBIO_CFG5 */ 3724*724ba675SRob Herring 0x001d0084 /* EMC_CFG_DIG_DLL */ 3725*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3726*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ 3727*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ 3728*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ 3729*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ 3730*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ 3731*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ 3732*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ 3733*724ba675SRob Herring 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ 3734*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3735*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3736*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3737*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3738*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3739*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3740*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3741*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3742*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3743*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3744*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3745*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3746*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3747*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3748*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3749*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3750*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ0 */ 3751*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ1 */ 3752*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ2 */ 3753*724ba675SRob Herring 0x00048000 /* EMC_DLL_XFORM_DQ3 */ 3754*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3755*724ba675SRob Herring 0x0800013d /* EMC_XM2DQSPADCTRL2 */ 3756*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3757*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3758*724ba675SRob Herring 0x01f1f508 /* EMC_XM2COMPPADCTRL */ 3759*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3760*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3761*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 3762*724ba675SRob Herring 0x08000021 /* EMC_XM2DQSPADCTRL3 */ 3763*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3764*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3765*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3766*724ba675SRob Herring 0x0158000c /* EMC_MRS_WAIT_CNT */ 3767*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3768*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3769*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3770*724ba675SRob Herring 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ 3771*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3772*724ba675SRob Herring 0xff00ff89 /* EMC_CFG_RSV */ 3773*724ba675SRob Herring >; 3774*724ba675SRob Herring }; 3775*724ba675SRob Herring 3776*724ba675SRob Herring timing-800000000 { 3777*724ba675SRob Herring clock-frequency = <800000000>; 3778*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3779*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 3780*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200018>; 3781*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000d71>; 3782*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3783*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3784*724ba675SRob Herring nvidia,emc-configuration = < 3785*724ba675SRob Herring 0x00000025 /* EMC_RC */ 3786*724ba675SRob Herring 0x000000ce /* EMC_RFC */ 3787*724ba675SRob Herring 0x0000001a /* EMC_RAS */ 3788*724ba675SRob Herring 0x00000009 /* EMC_RP */ 3789*724ba675SRob Herring 0x00000005 /* EMC_R2W */ 3790*724ba675SRob Herring 0x0000000d /* EMC_W2R */ 3791*724ba675SRob Herring 0x00000004 /* EMC_R2P */ 3792*724ba675SRob Herring 0x00000013 /* EMC_W2P */ 3793*724ba675SRob Herring 0x00000009 /* EMC_RD_RCD */ 3794*724ba675SRob Herring 0x00000009 /* EMC_WR_RCD */ 3795*724ba675SRob Herring 0x00000004 /* EMC_RRD */ 3796*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3797*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3798*724ba675SRob Herring 0x00000007 /* EMC_WDV */ 3799*724ba675SRob Herring 0x0000000a /* EMC_QUSE */ 3800*724ba675SRob Herring 0x00000009 /* EMC_QRST */ 3801*724ba675SRob Herring 0x0000000b /* EMC_QSAFE */ 3802*724ba675SRob Herring 0x00000011 /* EMC_RDV */ 3803*724ba675SRob Herring 0x00001820 /* EMC_REFRESH */ 3804*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3805*724ba675SRob Herring 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ 3806*724ba675SRob Herring 0x00000003 /* EMC_PDEX2WR */ 3807*724ba675SRob Herring 0x00000012 /* EMC_PDEX2RD */ 3808*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3809*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3810*724ba675SRob Herring 0x0000000f /* EMC_AR2PDEN */ 3811*724ba675SRob Herring 0x00000018 /* EMC_RW2PDEN */ 3812*724ba675SRob Herring 0x000000d8 /* EMC_TXSR */ 3813*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 3814*724ba675SRob Herring 0x00000005 /* EMC_TCKE */ 3815*724ba675SRob Herring 0x00000020 /* EMC_TFAW */ 3816*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3817*724ba675SRob Herring 0x00000007 /* EMC_TCLKSTABLE */ 3818*724ba675SRob Herring 0x00000008 /* EMC_TCLKSTOP */ 3819*724ba675SRob Herring 0x00001860 /* EMC_TREFBW */ 3820*724ba675SRob Herring 0x0000000b /* EMC_QUSE_EXTRA */ 3821*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 3822*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3823*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3824*724ba675SRob Herring 0x00005088 /* EMC_FBIO_CFG5 */ 3825*724ba675SRob Herring 0xf0070191 /* EMC_CFG_DIG_DLL */ 3826*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3827*724ba675SRob Herring 0x0000800a /* EMC_DLL_XFORM_DQS0 */ 3828*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS1 */ 3829*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS2 */ 3830*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS3 */ 3831*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS4 */ 3832*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS5 */ 3833*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS6 */ 3834*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS7 */ 3835*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ 3836*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ 3837*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ 3838*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ 3839*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ 3840*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ 3841*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ 3842*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ 3843*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3844*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3845*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3846*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3847*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3848*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3849*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3850*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3851*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ0 */ 3852*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ1 */ 3853*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ2 */ 3854*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ3 */ 3855*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3856*724ba675SRob Herring 0x0600013d /* EMC_XM2DQSPADCTRL2 */ 3857*724ba675SRob Herring 0x22220000 /* EMC_XM2DQPADCTRL2 */ 3858*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3859*724ba675SRob Herring 0x01f1f501 /* EMC_XM2COMPPADCTRL */ 3860*724ba675SRob Herring 0x07077404 /* EMC_XM2VTTGENPADCTRL */ 3861*724ba675SRob Herring 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ 3862*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 3863*724ba675SRob Herring 0x08000021 /* EMC_XM2DQSPADCTRL3 */ 3864*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3865*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 3866*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 3867*724ba675SRob Herring 0x00f0000c /* EMC_MRS_WAIT_CNT */ 3868*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3869*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3870*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3871*724ba675SRob Herring 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ 3872*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3873*724ba675SRob Herring 0xff00ff49 /* EMC_CFG_RSV */ 3874*724ba675SRob Herring >; 3875*724ba675SRob Herring }; 3876*724ba675SRob Herring }; 3877*724ba675SRob Herring 3878*724ba675SRob Herring emc-timings-2 { 3879*724ba675SRob Herring nvidia,ram-code = <2>; /* Hynix A RAM */ 3880*724ba675SRob Herring 3881*724ba675SRob Herring timing-25500000 { 3882*724ba675SRob Herring clock-frequency = <25500000>; 3883*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3884*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3885*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3886*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3887*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3888*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3889*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3890*724ba675SRob Herring nvidia,emc-configuration = < 3891*724ba675SRob Herring 0x00000001 /* EMC_RC */ 3892*724ba675SRob Herring 0x00000007 /* EMC_RFC */ 3893*724ba675SRob Herring 0x00000000 /* EMC_RAS */ 3894*724ba675SRob Herring 0x00000000 /* EMC_RP */ 3895*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3896*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3897*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 3898*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 3899*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 3900*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 3901*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 3902*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 3903*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 3904*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 3905*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 3906*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 3907*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 3908*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 3909*724ba675SRob Herring 0x000000c0 /* EMC_REFRESH */ 3910*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 3911*724ba675SRob Herring 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ 3912*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 3913*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 3914*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 3915*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 3916*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 3917*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 3918*724ba675SRob Herring 0x00000008 /* EMC_TXSR */ 3919*724ba675SRob Herring 0x00000008 /* EMC_TXSRDLL */ 3920*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 3921*724ba675SRob Herring 0x00000002 /* EMC_TFAW */ 3922*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 3923*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 3924*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 3925*724ba675SRob Herring 0x000000c7 /* EMC_TREFBW */ 3926*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 3927*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 3928*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 3929*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 3930*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 3931*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 3932*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 3933*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 3934*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 3935*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 3936*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 3937*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 3938*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 3939*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 3940*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 3941*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 3942*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 3943*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 3944*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 3945*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 3946*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 3947*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 3948*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 3949*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 3950*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 3951*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 3952*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 3953*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 3954*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 3955*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 3956*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 3957*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 3958*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 3959*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 3960*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 3961*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 3962*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 3963*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 3964*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 3965*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 3966*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 3967*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 3968*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 3969*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 3970*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 3971*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 3972*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 3973*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 3974*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 3975*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 3976*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 3977*724ba675SRob Herring 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ 3978*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 3979*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 3980*724ba675SRob Herring >; 3981*724ba675SRob Herring }; 3982*724ba675SRob Herring 3983*724ba675SRob Herring timing-51000000 { 3984*724ba675SRob Herring clock-frequency = <51000000>; 3985*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 3986*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 3987*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 3988*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 3989*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 3990*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 3991*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 3992*724ba675SRob Herring nvidia,emc-configuration = < 3993*724ba675SRob Herring 0x00000002 /* EMC_RC */ 3994*724ba675SRob Herring 0x0000000f /* EMC_RFC */ 3995*724ba675SRob Herring 0x00000001 /* EMC_RAS */ 3996*724ba675SRob Herring 0x00000000 /* EMC_RP */ 3997*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 3998*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 3999*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 4000*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 4001*724ba675SRob Herring 0x00000000 /* EMC_RD_RCD */ 4002*724ba675SRob Herring 0x00000000 /* EMC_WR_RCD */ 4003*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 4004*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 4005*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 4006*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 4007*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 4008*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 4009*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 4010*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 4011*724ba675SRob Herring 0x00000181 /* EMC_REFRESH */ 4012*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 4013*724ba675SRob Herring 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ 4014*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 4015*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 4016*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 4017*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 4018*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 4019*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 4020*724ba675SRob Herring 0x00000010 /* EMC_TXSR */ 4021*724ba675SRob Herring 0x00000010 /* EMC_TXSRDLL */ 4022*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 4023*724ba675SRob Herring 0x00000003 /* EMC_TFAW */ 4024*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 4025*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 4026*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 4027*724ba675SRob Herring 0x0000018e /* EMC_TREFBW */ 4028*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 4029*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 4030*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 4031*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 4032*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 4033*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 4034*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 4035*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 4036*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 4037*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 4038*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 4039*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 4040*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 4041*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 4042*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 4043*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 4044*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 4045*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 4046*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 4047*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 4048*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 4049*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 4050*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 4051*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 4052*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 4053*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 4054*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 4055*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 4056*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 4057*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 4058*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 4059*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 4060*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 4061*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 4062*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 4063*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 4064*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 4065*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 4066*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 4067*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 4068*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 4069*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 4070*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 4071*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 4072*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 4073*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 4074*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 4075*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 4076*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 4077*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 4078*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 4079*724ba675SRob Herring 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ 4080*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 4081*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 4082*724ba675SRob Herring >; 4083*724ba675SRob Herring }; 4084*724ba675SRob Herring 4085*724ba675SRob Herring timing-102000000 { 4086*724ba675SRob Herring clock-frequency = <102000000>; 4087*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 4088*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 4089*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 4090*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 4091*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 4092*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 4093*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 4094*724ba675SRob Herring nvidia,emc-configuration = < 4095*724ba675SRob Herring 0x00000004 /* EMC_RC */ 4096*724ba675SRob Herring 0x0000001e /* EMC_RFC */ 4097*724ba675SRob Herring 0x00000003 /* EMC_RAS */ 4098*724ba675SRob Herring 0x00000001 /* EMC_RP */ 4099*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 4100*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 4101*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 4102*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 4103*724ba675SRob Herring 0x00000001 /* EMC_RD_RCD */ 4104*724ba675SRob Herring 0x00000001 /* EMC_WR_RCD */ 4105*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 4106*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 4107*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 4108*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 4109*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 4110*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 4111*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 4112*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 4113*724ba675SRob Herring 0x00000303 /* EMC_REFRESH */ 4114*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 4115*724ba675SRob Herring 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ 4116*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 4117*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 4118*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 4119*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 4120*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 4121*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 4122*724ba675SRob Herring 0x00000020 /* EMC_TXSR */ 4123*724ba675SRob Herring 0x00000020 /* EMC_TXSRDLL */ 4124*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 4125*724ba675SRob Herring 0x00000005 /* EMC_TFAW */ 4126*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 4127*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 4128*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 4129*724ba675SRob Herring 0x0000031c /* EMC_TREFBW */ 4130*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 4131*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 4132*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 4133*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 4134*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 4135*724ba675SRob Herring 0x007800a4 /* EMC_CFG_DIG_DLL */ 4136*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 4137*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ 4138*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ 4139*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ 4140*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ 4141*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ 4142*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ 4143*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ 4144*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ 4145*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 4146*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 4147*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 4148*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 4149*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 4150*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 4151*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 4152*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 4153*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 4154*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 4155*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 4156*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 4157*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 4158*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 4159*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 4160*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 4161*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 4162*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 4163*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 4164*724ba675SRob Herring 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 4165*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 4166*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 4167*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 4168*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 4169*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 4170*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 4171*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 4172*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 4173*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 4174*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 4175*724ba675SRob Herring 0x00000000 /* EMC_ZCAL_INTERVAL */ 4176*724ba675SRob Herring 0x00000040 /* EMC_ZCAL_WAIT_CNT */ 4177*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 4178*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 4179*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 4180*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 4181*724ba675SRob Herring 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ 4182*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 4183*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 4184*724ba675SRob Herring >; 4185*724ba675SRob Herring }; 4186*724ba675SRob Herring 4187*724ba675SRob Herring timing-204000000 { 4188*724ba675SRob Herring clock-frequency = <204000000>; 4189*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 4190*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100003>; 4191*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200008>; 4192*724ba675SRob Herring nvidia,emc-mode-reset = <0x80001221>; 4193*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 4194*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 4195*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 4196*724ba675SRob Herring nvidia,emc-configuration = < 4197*724ba675SRob Herring 0x00000009 /* EMC_RC */ 4198*724ba675SRob Herring 0x0000003d /* EMC_RFC */ 4199*724ba675SRob Herring 0x00000007 /* EMC_RAS */ 4200*724ba675SRob Herring 0x00000002 /* EMC_RP */ 4201*724ba675SRob Herring 0x00000002 /* EMC_R2W */ 4202*724ba675SRob Herring 0x0000000a /* EMC_W2R */ 4203*724ba675SRob Herring 0x00000005 /* EMC_R2P */ 4204*724ba675SRob Herring 0x0000000b /* EMC_W2P */ 4205*724ba675SRob Herring 0x00000002 /* EMC_RD_RCD */ 4206*724ba675SRob Herring 0x00000002 /* EMC_WR_RCD */ 4207*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 4208*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 4209*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 4210*724ba675SRob Herring 0x00000005 /* EMC_WDV */ 4211*724ba675SRob Herring 0x00000005 /* EMC_QUSE */ 4212*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 4213*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 4214*724ba675SRob Herring 0x0000000b /* EMC_RDV */ 4215*724ba675SRob Herring 0x00000607 /* EMC_REFRESH */ 4216*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 4217*724ba675SRob Herring 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ 4218*724ba675SRob Herring 0x00000002 /* EMC_PDEX2WR */ 4219*724ba675SRob Herring 0x00000002 /* EMC_PDEX2RD */ 4220*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 4221*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 4222*724ba675SRob Herring 0x00000007 /* EMC_AR2PDEN */ 4223*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 4224*724ba675SRob Herring 0x00000040 /* EMC_TXSR */ 4225*724ba675SRob Herring 0x00000040 /* EMC_TXSRDLL */ 4226*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 4227*724ba675SRob Herring 0x00000009 /* EMC_TFAW */ 4228*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 4229*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 4230*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 4231*724ba675SRob Herring 0x00000638 /* EMC_TREFBW */ 4232*724ba675SRob Herring 0x00000006 /* EMC_QUSE_EXTRA */ 4233*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 4234*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 4235*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 4236*724ba675SRob Herring 0x00004288 /* EMC_FBIO_CFG5 */ 4237*724ba675SRob Herring 0x004400a4 /* EMC_CFG_DIG_DLL */ 4238*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 4239*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS0 */ 4240*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS1 */ 4241*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS2 */ 4242*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS3 */ 4243*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS4 */ 4244*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS5 */ 4245*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS6 */ 4246*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQS7 */ 4247*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 4248*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 4249*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 4250*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 4251*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 4252*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 4253*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 4254*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 4255*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 4256*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 4257*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 4258*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 4259*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 4260*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 4261*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 4262*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 4263*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ0 */ 4264*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ1 */ 4265*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ2 */ 4266*724ba675SRob Herring 0x00080000 /* EMC_DLL_XFORM_DQ3 */ 4267*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 4268*724ba675SRob Herring 0x0800211c /* EMC_XM2DQSPADCTRL2 */ 4269*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 4270*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 4271*724ba675SRob Herring 0x01f1f108 /* EMC_XM2COMPPADCTRL */ 4272*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 4273*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 4274*724ba675SRob Herring 0x08000168 /* EMC_XM2QUSEPADCTRL */ 4275*724ba675SRob Herring 0x08000000 /* EMC_XM2DQSPADCTRL3 */ 4276*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 4277*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 4278*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 4279*724ba675SRob Herring 0x000c000c /* EMC_MRS_WAIT_CNT */ 4280*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 4281*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 4282*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 4283*724ba675SRob Herring 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ 4284*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 4285*724ba675SRob Herring 0xff00ff00 /* EMC_CFG_RSV */ 4286*724ba675SRob Herring >; 4287*724ba675SRob Herring }; 4288*724ba675SRob Herring 4289*724ba675SRob Herring timing-400000000 { 4290*724ba675SRob Herring clock-frequency = <400000000>; 4291*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 4292*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 4293*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200000>; 4294*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000521>; 4295*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 4296*724ba675SRob Herring nvidia,emc-configuration = < 4297*724ba675SRob Herring 0x00000012 /* EMC_RC */ 4298*724ba675SRob Herring 0x00000076 /* EMC_RFC */ 4299*724ba675SRob Herring 0x0000000c /* EMC_RAS */ 4300*724ba675SRob Herring 0x00000004 /* EMC_RP */ 4301*724ba675SRob Herring 0x00000003 /* EMC_R2W */ 4302*724ba675SRob Herring 0x00000008 /* EMC_W2R */ 4303*724ba675SRob Herring 0x00000002 /* EMC_R2P */ 4304*724ba675SRob Herring 0x0000000a /* EMC_W2P */ 4305*724ba675SRob Herring 0x00000004 /* EMC_RD_RCD */ 4306*724ba675SRob Herring 0x00000004 /* EMC_WR_RCD */ 4307*724ba675SRob Herring 0x00000002 /* EMC_RRD */ 4308*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 4309*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 4310*724ba675SRob Herring 0x00000004 /* EMC_WDV */ 4311*724ba675SRob Herring 0x00000006 /* EMC_QUSE */ 4312*724ba675SRob Herring 0x00000004 /* EMC_QRST */ 4313*724ba675SRob Herring 0x0000000a /* EMC_QSAFE */ 4314*724ba675SRob Herring 0x0000000c /* EMC_RDV */ 4315*724ba675SRob Herring 0x00000bf0 /* EMC_REFRESH */ 4316*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 4317*724ba675SRob Herring 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ 4318*724ba675SRob Herring 0x00000001 /* EMC_PDEX2WR */ 4319*724ba675SRob Herring 0x00000008 /* EMC_PDEX2RD */ 4320*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 4321*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 4322*724ba675SRob Herring 0x00000008 /* EMC_AR2PDEN */ 4323*724ba675SRob Herring 0x0000000f /* EMC_RW2PDEN */ 4324*724ba675SRob Herring 0x0000007c /* EMC_TXSR */ 4325*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 4326*724ba675SRob Herring 0x00000004 /* EMC_TCKE */ 4327*724ba675SRob Herring 0x00000010 /* EMC_TFAW */ 4328*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 4329*724ba675SRob Herring 0x00000004 /* EMC_TCLKSTABLE */ 4330*724ba675SRob Herring 0x00000005 /* EMC_TCLKSTOP */ 4331*724ba675SRob Herring 0x00000c30 /* EMC_TREFBW */ 4332*724ba675SRob Herring 0x00000000 /* EMC_QUSE_EXTRA */ 4333*724ba675SRob Herring 0x00000004 /* EMC_FBIO_CFG6 */ 4334*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 4335*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 4336*724ba675SRob Herring 0x00007088 /* EMC_FBIO_CFG5 */ 4337*724ba675SRob Herring 0x001d0084 /* EMC_CFG_DIG_DLL */ 4338*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 4339*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS0 */ 4340*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS1 */ 4341*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS2 */ 4342*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS3 */ 4343*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS4 */ 4344*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS5 */ 4345*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS6 */ 4346*724ba675SRob Herring 0x00044000 /* EMC_DLL_XFORM_DQS7 */ 4347*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 4348*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 4349*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 4350*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 4351*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 4352*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 4353*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 4354*724ba675SRob Herring 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 4355*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 4356*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 4357*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 4358*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 4359*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 4360*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 4361*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 4362*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 4363*724ba675SRob Herring 0x00058000 /* EMC_DLL_XFORM_DQ0 */ 4364*724ba675SRob Herring 0x00058000 /* EMC_DLL_XFORM_DQ1 */ 4365*724ba675SRob Herring 0x00058000 /* EMC_DLL_XFORM_DQ2 */ 4366*724ba675SRob Herring 0x00058000 /* EMC_DLL_XFORM_DQ3 */ 4367*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 4368*724ba675SRob Herring 0x0800013d /* EMC_XM2DQSPADCTRL2 */ 4369*724ba675SRob Herring 0x00000000 /* EMC_XM2DQPADCTRL2 */ 4370*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 4371*724ba675SRob Herring 0x01f1f508 /* EMC_XM2COMPPADCTRL */ 4372*724ba675SRob Herring 0x05057404 /* EMC_XM2VTTGENPADCTRL */ 4373*724ba675SRob Herring 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ 4374*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 4375*724ba675SRob Herring 0x08000021 /* EMC_XM2DQSPADCTRL3 */ 4376*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 4377*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 4378*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 4379*724ba675SRob Herring 0x0148000c /* EMC_MRS_WAIT_CNT */ 4380*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 4381*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 4382*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 4383*724ba675SRob Herring 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ 4384*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 4385*724ba675SRob Herring 0xff00ff89 /* EMC_CFG_RSV */ 4386*724ba675SRob Herring >; 4387*724ba675SRob Herring }; 4388*724ba675SRob Herring 4389*724ba675SRob Herring timing-800000000 { 4390*724ba675SRob Herring clock-frequency = <800000000>; 4391*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 4392*724ba675SRob Herring nvidia,emc-mode-1 = <0x80100002>; 4393*724ba675SRob Herring nvidia,emc-mode-2 = <0x80200018>; 4394*724ba675SRob Herring nvidia,emc-mode-reset = <0x80000d71>; 4395*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000040>; 4396*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 4397*724ba675SRob Herring nvidia,emc-configuration = < 4398*724ba675SRob Herring 0x00000025 /* EMC_RC */ 4399*724ba675SRob Herring 0x000000ee /* EMC_RFC */ 4400*724ba675SRob Herring 0x0000001a /* EMC_RAS */ 4401*724ba675SRob Herring 0x00000009 /* EMC_RP */ 4402*724ba675SRob Herring 0x00000005 /* EMC_R2W */ 4403*724ba675SRob Herring 0x0000000d /* EMC_W2R */ 4404*724ba675SRob Herring 0x00000004 /* EMC_R2P */ 4405*724ba675SRob Herring 0x00000013 /* EMC_W2P */ 4406*724ba675SRob Herring 0x00000009 /* EMC_RD_RCD */ 4407*724ba675SRob Herring 0x00000009 /* EMC_WR_RCD */ 4408*724ba675SRob Herring 0x00000003 /* EMC_RRD */ 4409*724ba675SRob Herring 0x00000001 /* EMC_REXT */ 4410*724ba675SRob Herring 0x00000000 /* EMC_WEXT */ 4411*724ba675SRob Herring 0x00000007 /* EMC_WDV */ 4412*724ba675SRob Herring 0x0000000a /* EMC_QUSE */ 4413*724ba675SRob Herring 0x00000009 /* EMC_QRST */ 4414*724ba675SRob Herring 0x0000000b /* EMC_QSAFE */ 4415*724ba675SRob Herring 0x00000011 /* EMC_RDV */ 4416*724ba675SRob Herring 0x00001820 /* EMC_REFRESH */ 4417*724ba675SRob Herring 0x00000000 /* EMC_BURST_REFRESH_NUM */ 4418*724ba675SRob Herring 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ 4419*724ba675SRob Herring 0x00000003 /* EMC_PDEX2WR */ 4420*724ba675SRob Herring 0x00000012 /* EMC_PDEX2RD */ 4421*724ba675SRob Herring 0x00000001 /* EMC_PCHG2PDEN */ 4422*724ba675SRob Herring 0x00000000 /* EMC_ACT2PDEN */ 4423*724ba675SRob Herring 0x0000000f /* EMC_AR2PDEN */ 4424*724ba675SRob Herring 0x00000018 /* EMC_RW2PDEN */ 4425*724ba675SRob Herring 0x000000f8 /* EMC_TXSR */ 4426*724ba675SRob Herring 0x00000200 /* EMC_TXSRDLL */ 4427*724ba675SRob Herring 0x00000005 /* EMC_TCKE */ 4428*724ba675SRob Herring 0x00000020 /* EMC_TFAW */ 4429*724ba675SRob Herring 0x00000000 /* EMC_TRPAB */ 4430*724ba675SRob Herring 0x00000007 /* EMC_TCLKSTABLE */ 4431*724ba675SRob Herring 0x00000008 /* EMC_TCLKSTOP */ 4432*724ba675SRob Herring 0x00001860 /* EMC_TREFBW */ 4433*724ba675SRob Herring 0x0000000b /* EMC_QUSE_EXTRA */ 4434*724ba675SRob Herring 0x00000006 /* EMC_FBIO_CFG6 */ 4435*724ba675SRob Herring 0x00000000 /* EMC_ODT_WRITE */ 4436*724ba675SRob Herring 0x00000000 /* EMC_ODT_READ */ 4437*724ba675SRob Herring 0x00005088 /* EMC_FBIO_CFG5 */ 4438*724ba675SRob Herring 0xf0070191 /* EMC_CFG_DIG_DLL */ 4439*724ba675SRob Herring 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 4440*724ba675SRob Herring 0x0000000c /* EMC_DLL_XFORM_DQS0 */ 4441*724ba675SRob Herring 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ 4442*724ba675SRob Herring 0x00000008 /* EMC_DLL_XFORM_DQS2 */ 4443*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS3 */ 4444*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS4 */ 4445*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS5 */ 4446*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS6 */ 4447*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQS7 */ 4448*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ 4449*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ 4450*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ 4451*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ 4452*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ 4453*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ 4454*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ 4455*724ba675SRob Herring 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ 4456*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 4457*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 4458*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 4459*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 4460*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 4461*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 4462*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 4463*724ba675SRob Herring 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 4464*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ0 */ 4465*724ba675SRob Herring 0x0000000c /* EMC_DLL_XFORM_DQ1 */ 4466*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ2 */ 4467*724ba675SRob Herring 0x0000000a /* EMC_DLL_XFORM_DQ3 */ 4468*724ba675SRob Herring 0x000002a0 /* EMC_XM2CMDPADCTRL */ 4469*724ba675SRob Herring 0x0600013d /* EMC_XM2DQSPADCTRL2 */ 4470*724ba675SRob Herring 0x22220000 /* EMC_XM2DQPADCTRL2 */ 4471*724ba675SRob Herring 0x77fff884 /* EMC_XM2CLKPADCTRL */ 4472*724ba675SRob Herring 0x01f1f501 /* EMC_XM2COMPPADCTRL */ 4473*724ba675SRob Herring 0x07077404 /* EMC_XM2VTTGENPADCTRL */ 4474*724ba675SRob Herring 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ 4475*724ba675SRob Herring 0x080001e8 /* EMC_XM2QUSEPADCTRL */ 4476*724ba675SRob Herring 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ 4477*724ba675SRob Herring 0x00000802 /* EMC_CTT_TERM_CTRL */ 4478*724ba675SRob Herring 0x00020000 /* EMC_ZCAL_INTERVAL */ 4479*724ba675SRob Herring 0x00000100 /* EMC_ZCAL_WAIT_CNT */ 4480*724ba675SRob Herring 0x00d0000c /* EMC_MRS_WAIT_CNT */ 4481*724ba675SRob Herring 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ 4482*724ba675SRob Herring 0x00000000 /* EMC_CTT */ 4483*724ba675SRob Herring 0x00000000 /* EMC_CTT_DURATION */ 4484*724ba675SRob Herring 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ 4485*724ba675SRob Herring 0xe8000000 /* EMC_FBIO_SPARE */ 4486*724ba675SRob Herring 0xff00ff49 /* EMC_CFG_RSV */ 4487*724ba675SRob Herring >; 4488*724ba675SRob Herring }; 4489*724ba675SRob Herring }; 4490*724ba675SRob Herring }; 4491*724ba675SRob Herring 4492*724ba675SRob Herring hda@70030000 { 4493*724ba675SRob Herring status = "okay"; 4494*724ba675SRob Herring }; 4495*724ba675SRob Herring 4496*724ba675SRob Herring sdmmc3: mmc@78000400 { 4497*724ba675SRob Herring status = "okay"; 4498*724ba675SRob Herring 4499*724ba675SRob Herring #address-cells = <1>; 4500*724ba675SRob Herring #size-cells = <0>; 4501*724ba675SRob Herring 4502*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 4503*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 4504*724ba675SRob Herring assigned-clock-rates = <50000000>; 4505*724ba675SRob Herring 4506*724ba675SRob Herring max-frequency = <50000000>; 4507*724ba675SRob Herring keep-power-in-suspend; 4508*724ba675SRob Herring 4509*724ba675SRob Herring bus-width = <4>; 4510*724ba675SRob Herring non-removable; 4511*724ba675SRob Herring 4512*724ba675SRob Herring mmc-pwrseq = <&wifi_pwrseq>; 4513*724ba675SRob Herring vmmc-supply = <&sdmmc_3v3_reg>; 4514*724ba675SRob Herring vqmmc-supply = <&vdd_1v8>; 4515*724ba675SRob Herring 4516*724ba675SRob Herring /* Azurewave AW-NH660 BCM4330 */ 4517*724ba675SRob Herring brcmf: wifi@1 { 4518*724ba675SRob Herring reg = <1>; 4519*724ba675SRob Herring compatible = "brcm,bcm4329-fmac"; 4520*724ba675SRob Herring interrupt-parent = <&gpio>; 4521*724ba675SRob Herring interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 4522*724ba675SRob Herring interrupt-names = "host-wake"; 4523*724ba675SRob Herring }; 4524*724ba675SRob Herring }; 4525*724ba675SRob Herring 4526*724ba675SRob Herring sdmmc4: mmc@78000600 { 4527*724ba675SRob Herring status = "okay"; 4528*724ba675SRob Herring 4529*724ba675SRob Herring keep-power-in-suspend; 4530*724ba675SRob Herring bus-width = <8>; 4531*724ba675SRob Herring non-removable; 4532*724ba675SRob Herring vmmc-supply = <&sys_3v3_reg>; 4533*724ba675SRob Herring vqmmc-supply = <&vdd_1v8>; 4534*724ba675SRob Herring nvidia,default-tap = <0x0F>; 4535*724ba675SRob Herring max-frequency = <25500000>; 4536*724ba675SRob Herring }; 4537*724ba675SRob Herring 4538*724ba675SRob Herring usb@7d000000 { 4539*724ba675SRob Herring compatible = "nvidia,tegra30-udc"; 4540*724ba675SRob Herring status = "okay"; 4541*724ba675SRob Herring }; 4542*724ba675SRob Herring 4543*724ba675SRob Herring usb-phy@7d000000 { 4544*724ba675SRob Herring status = "okay"; 4545*724ba675SRob Herring dr_mode = "peripheral"; 4546*724ba675SRob Herring }; 4547*724ba675SRob Herring 4548*724ba675SRob Herring usb@7d004000 { 4549*724ba675SRob Herring status = "okay"; 4550*724ba675SRob Herring #address-cells = <1>; 4551*724ba675SRob Herring #size-cells = <0>; 4552*724ba675SRob Herring 4553*724ba675SRob Herring ethernet@2 { /* SMSC 10/100T Ethernet Controller */ 4554*724ba675SRob Herring compatible = "usb424,9e00"; 4555*724ba675SRob Herring reg = <2>; 4556*724ba675SRob Herring local-mac-address = [00 11 22 33 44 55]; 4557*724ba675SRob Herring }; 4558*724ba675SRob Herring }; 4559*724ba675SRob Herring 4560*724ba675SRob Herring usb-phy@7d004000 { 4561*724ba675SRob Herring vbus-supply = <&vdd_smsc>; 4562*724ba675SRob Herring status = "okay"; 4563*724ba675SRob Herring }; 4564*724ba675SRob Herring 4565*724ba675SRob Herring usb@7d008000 { 4566*724ba675SRob Herring status = "okay"; 4567*724ba675SRob Herring }; 4568*724ba675SRob Herring 4569*724ba675SRob Herring usb-phy@7d008000 { 4570*724ba675SRob Herring vbus-supply = <&usb3_vbus_reg>; 4571*724ba675SRob Herring status = "okay"; 4572*724ba675SRob Herring }; 4573*724ba675SRob Herring 4574*724ba675SRob Herring /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 4575*724ba675SRob Herring clk32k_in: clock { 4576*724ba675SRob Herring compatible = "fixed-clock"; 4577*724ba675SRob Herring #clock-cells = <0>; 4578*724ba675SRob Herring clock-frequency = <32768>; 4579*724ba675SRob Herring clock-output-names = "pmic-oscillator"; 4580*724ba675SRob Herring }; 4581*724ba675SRob Herring 4582*724ba675SRob Herring cpus { 4583*724ba675SRob Herring cpu0: cpu@0 { 4584*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 4585*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 4586*724ba675SRob Herring #cooling-cells = <2>; 4587*724ba675SRob Herring }; 4588*724ba675SRob Herring 4589*724ba675SRob Herring cpu1: cpu@1 { 4590*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 4591*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 4592*724ba675SRob Herring #cooling-cells = <2>; 4593*724ba675SRob Herring }; 4594*724ba675SRob Herring 4595*724ba675SRob Herring cpu2: cpu@2 { 4596*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 4597*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 4598*724ba675SRob Herring #cooling-cells = <2>; 4599*724ba675SRob Herring }; 4600*724ba675SRob Herring 4601*724ba675SRob Herring cpu3: cpu@3 { 4602*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 4603*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 4604*724ba675SRob Herring #cooling-cells = <2>; 4605*724ba675SRob Herring }; 4606*724ba675SRob Herring }; 4607*724ba675SRob Herring 4608*724ba675SRob Herring fan: fan { 4609*724ba675SRob Herring compatible = "gpio-fan"; 4610*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; 4611*724ba675SRob Herring gpio-fan,speed-map = <0 0 4612*724ba675SRob Herring 4500 1>; 4613*724ba675SRob Herring #cooling-cells = <2>; 4614*724ba675SRob Herring }; 4615*724ba675SRob Herring 4616*724ba675SRob Herring gpio-keys { 4617*724ba675SRob Herring compatible = "gpio-keys"; 4618*724ba675SRob Herring 4619*724ba675SRob Herring key-power { 4620*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 4621*724ba675SRob Herring debounce-interval = <10>; 4622*724ba675SRob Herring linux,code = <KEY_POWER>; 4623*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 4624*724ba675SRob Herring wakeup-source; 4625*724ba675SRob Herring }; 4626*724ba675SRob Herring }; 4627*724ba675SRob Herring 4628*724ba675SRob Herring leds { 4629*724ba675SRob Herring compatible = "gpio-leds"; 4630*724ba675SRob Herring 4631*724ba675SRob Herring led-power { 4632*724ba675SRob Herring label = "power-led"; 4633*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 4634*724ba675SRob Herring default-state = "on"; 4635*724ba675SRob Herring linux,default-trigger = "heartbeat"; 4636*724ba675SRob Herring retain-state-suspended; 4637*724ba675SRob Herring }; 4638*724ba675SRob Herring }; 4639*724ba675SRob Herring 4640*724ba675SRob Herring opp-table-actmon { 4641*724ba675SRob Herring /delete-node/ opp-900000000; 4642*724ba675SRob Herring }; 4643*724ba675SRob Herring 4644*724ba675SRob Herring opp-table-emc { 4645*724ba675SRob Herring /delete-node/ opp-900000000-1350; 4646*724ba675SRob Herring }; 4647*724ba675SRob Herring 4648*724ba675SRob Herring wifi_pwrseq: pwrseq-wifi { 4649*724ba675SRob Herring compatible = "mmc-pwrseq-simple"; 4650*724ba675SRob Herring 4651*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 4652*724ba675SRob Herring clock-names = "ext_clock"; 4653*724ba675SRob Herring 4654*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; 4655*724ba675SRob Herring post-power-on-delay-ms = <300>; 4656*724ba675SRob Herring power-off-delay-us = <300>; 4657*724ba675SRob Herring }; 4658*724ba675SRob Herring 4659*724ba675SRob Herring vdd_12v_in: regulator-vdd-12v-in { 4660*724ba675SRob Herring compatible = "regulator-fixed"; 4661*724ba675SRob Herring regulator-name = "vdd_12v_in"; 4662*724ba675SRob Herring regulator-min-microvolt = <12000000>; 4663*724ba675SRob Herring regulator-max-microvolt = <12000000>; 4664*724ba675SRob Herring regulator-always-on; 4665*724ba675SRob Herring }; 4666*724ba675SRob Herring 4667*724ba675SRob Herring sdmmc_3v3_reg: regulator-sdmmc-3v3 { 4668*724ba675SRob Herring compatible = "regulator-fixed"; 4669*724ba675SRob Herring regulator-name = "sdmmc_3v3"; 4670*724ba675SRob Herring regulator-min-microvolt = <3300000>; 4671*724ba675SRob Herring regulator-max-microvolt = <3300000>; 4672*724ba675SRob Herring enable-active-high; 4673*724ba675SRob Herring regulator-always-on; 4674*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 4675*724ba675SRob Herring vin-supply = <&sys_3v3_reg>; 4676*724ba675SRob Herring }; 4677*724ba675SRob Herring 4678*724ba675SRob Herring vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { 4679*724ba675SRob Herring compatible = "regulator-fixed"; 4680*724ba675SRob Herring regulator-name = "vdd_fuse_3v3"; 4681*724ba675SRob Herring regulator-min-microvolt = <3300000>; 4682*724ba675SRob Herring regulator-max-microvolt = <3300000>; 4683*724ba675SRob Herring enable-active-high; 4684*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; 4685*724ba675SRob Herring vin-supply = <&sys_3v3_reg>; 4686*724ba675SRob Herring regulator-always-on; 4687*724ba675SRob Herring }; 4688*724ba675SRob Herring 4689*724ba675SRob Herring vdd_vid_reg: regulator-vdd-vid { 4690*724ba675SRob Herring compatible = "regulator-fixed"; 4691*724ba675SRob Herring regulator-name = "vddio_vid"; 4692*724ba675SRob Herring regulator-min-microvolt = <5000000>; 4693*724ba675SRob Herring regulator-max-microvolt = <5000000>; 4694*724ba675SRob Herring enable-active-high; 4695*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; 4696*724ba675SRob Herring vin-supply = <&vdd_5v0_reg>; 4697*724ba675SRob Herring regulator-boot-on; 4698*724ba675SRob Herring }; 4699*724ba675SRob Herring 4700*724ba675SRob Herring ddr_reg: regulator-ddr { 4701*724ba675SRob Herring compatible = "regulator-fixed"; 4702*724ba675SRob Herring regulator-name = "vdd_ddr"; 4703*724ba675SRob Herring regulator-min-microvolt = <1500000>; 4704*724ba675SRob Herring regulator-max-microvolt = <1500000>; 4705*724ba675SRob Herring regulator-always-on; 4706*724ba675SRob Herring enable-active-high; 4707*724ba675SRob Herring gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 4708*724ba675SRob Herring regulator-boot-on; 4709*724ba675SRob Herring vin-supply = <&vdd_12v_in>; 4710*724ba675SRob Herring }; 4711*724ba675SRob Herring 4712*724ba675SRob Herring sys_3v3_reg: regulator-sys-3v3 { 4713*724ba675SRob Herring compatible = "regulator-fixed"; 4714*724ba675SRob Herring regulator-name = "sys_3v3"; 4715*724ba675SRob Herring regulator-min-microvolt = <3300000>; 4716*724ba675SRob Herring regulator-max-microvolt = <3300000>; 4717*724ba675SRob Herring enable-active-high; 4718*724ba675SRob Herring gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 4719*724ba675SRob Herring regulator-always-on; 4720*724ba675SRob Herring regulator-boot-on; 4721*724ba675SRob Herring vin-supply = <&vdd_12v_in>; 4722*724ba675SRob Herring }; 4723*724ba675SRob Herring 4724*724ba675SRob Herring vdd_5v0_reg: regulator-vdd-5v0 { 4725*724ba675SRob Herring compatible = "regulator-fixed"; 4726*724ba675SRob Herring regulator-name = "vdd_5v0"; 4727*724ba675SRob Herring regulator-min-microvolt = <5000000>; 4728*724ba675SRob Herring regulator-max-microvolt = <5000000>; 4729*724ba675SRob Herring enable-active-high; 4730*724ba675SRob Herring gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 4731*724ba675SRob Herring regulator-always-on; 4732*724ba675SRob Herring regulator-boot-on; 4733*724ba675SRob Herring vin-supply = <&vdd_12v_in>; 4734*724ba675SRob Herring }; 4735*724ba675SRob Herring 4736*724ba675SRob Herring vdd_smsc: regulator-vdd-smsc { 4737*724ba675SRob Herring compatible = "regulator-fixed"; 4738*724ba675SRob Herring regulator-name = "vdd_smsc"; 4739*724ba675SRob Herring enable-active-high; 4740*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; 4741*724ba675SRob Herring }; 4742*724ba675SRob Herring 4743*724ba675SRob Herring usb3_vbus_reg: regulator-usb3-vbus { 4744*724ba675SRob Herring compatible = "regulator-fixed"; 4745*724ba675SRob Herring regulator-name = "usb3_vbus"; 4746*724ba675SRob Herring regulator-min-microvolt = <5000000>; 4747*724ba675SRob Herring regulator-max-microvolt = <5000000>; 4748*724ba675SRob Herring enable-active-high; 4749*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; 4750*724ba675SRob Herring vin-supply = <&vdd_5v0_reg>; 4751*724ba675SRob Herring }; 4752*724ba675SRob Herring 4753*724ba675SRob Herring thermal-zones { 4754*724ba675SRob Herring cpu_thermal: cpu-thermal { 4755*724ba675SRob Herring polling-delay = <5000>; 4756*724ba675SRob Herring polling-delay-passive = <5000>; 4757*724ba675SRob Herring 4758*724ba675SRob Herring thermal-sensors = <&cpu_temp 1>; 4759*724ba675SRob Herring 4760*724ba675SRob Herring trips { 4761*724ba675SRob Herring cpu_alert0: cpu-alert0 { 4762*724ba675SRob Herring temperature = <50000>; 4763*724ba675SRob Herring hysteresis = <10000>; 4764*724ba675SRob Herring type = "active"; 4765*724ba675SRob Herring }; 4766*724ba675SRob Herring cpu_alert1: cpu-alert1 { 4767*724ba675SRob Herring temperature = <70000>; 4768*724ba675SRob Herring hysteresis = <5000>; 4769*724ba675SRob Herring type = "passive"; 4770*724ba675SRob Herring }; 4771*724ba675SRob Herring cpu_crit: cpu-crit { 4772*724ba675SRob Herring temperature = <90000>; 4773*724ba675SRob Herring hysteresis = <2000>; 4774*724ba675SRob Herring type = "critical"; 4775*724ba675SRob Herring }; 4776*724ba675SRob Herring }; 4777*724ba675SRob Herring 4778*724ba675SRob Herring cooling-maps { 4779*724ba675SRob Herring map0 { 4780*724ba675SRob Herring trip = <&cpu_alert0>; 4781*724ba675SRob Herring cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4782*724ba675SRob Herring }; 4783*724ba675SRob Herring map1 { 4784*724ba675SRob Herring trip = <&cpu_alert1>; 4785*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4786*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4787*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4788*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4789*724ba675SRob Herring <&actmon THERMAL_NO_LIMIT 4790*724ba675SRob Herring THERMAL_NO_LIMIT>; 4791*724ba675SRob Herring }; 4792*724ba675SRob Herring }; 4793*724ba675SRob Herring }; 4794*724ba675SRob Herring }; 4795*724ba675SRob Herring}; 4796