xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra30-lg-x3.dtsi (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1*b68e6e0dSSvyatoslav Ryhel// SPDX-License-Identifier: GPL-2.0
2*b68e6e0dSSvyatoslav Ryhel
3*b68e6e0dSSvyatoslav Ryhel#include <dt-bindings/input/gpio-keys.h>
4*b68e6e0dSSvyatoslav Ryhel#include <dt-bindings/input/input.h>
5*b68e6e0dSSvyatoslav Ryhel#include <dt-bindings/leds/common.h>
6*b68e6e0dSSvyatoslav Ryhel#include <dt-bindings/mfd/max77620.h>
7*b68e6e0dSSvyatoslav Ryhel#include <dt-bindings/thermal/thermal.h>
8*b68e6e0dSSvyatoslav Ryhel
9*b68e6e0dSSvyatoslav Ryhel#include "tegra30.dtsi"
10*b68e6e0dSSvyatoslav Ryhel#include "tegra30-cpu-opp.dtsi"
11*b68e6e0dSSvyatoslav Ryhel#include "tegra30-cpu-opp-microvolt.dtsi"
12*b68e6e0dSSvyatoslav Ryhel
13*b68e6e0dSSvyatoslav Ryhel/ {
14*b68e6e0dSSvyatoslav Ryhel	chassis-type = "handset";
15*b68e6e0dSSvyatoslav Ryhel
16*b68e6e0dSSvyatoslav Ryhel	aliases {
17*b68e6e0dSSvyatoslav Ryhel		mmc0 = &sdmmc4; /* eMMC */
18*b68e6e0dSSvyatoslav Ryhel		mmc1 = &sdmmc1; /* WiFi */
19*b68e6e0dSSvyatoslav Ryhel
20*b68e6e0dSSvyatoslav Ryhel		rtc0 = &pmic;
21*b68e6e0dSSvyatoslav Ryhel		rtc1 = "/rtc@7000e000";
22*b68e6e0dSSvyatoslav Ryhel
23*b68e6e0dSSvyatoslav Ryhel		serial0 = &uartd; /* Console */
24*b68e6e0dSSvyatoslav Ryhel		serial1 = &uartc; /* Bluetooth */
25*b68e6e0dSSvyatoslav Ryhel		serial2 = &uartb; /* GPS */
26*b68e6e0dSSvyatoslav Ryhel	};
27*b68e6e0dSSvyatoslav Ryhel
28*b68e6e0dSSvyatoslav Ryhel	/*
29*b68e6e0dSSvyatoslav Ryhel	 * The decompressor and also some bootloaders rely on a
30*b68e6e0dSSvyatoslav Ryhel	 * pre-existing /chosen node to be available to insert the
31*b68e6e0dSSvyatoslav Ryhel	 * command line and merge other ATAGS info.
32*b68e6e0dSSvyatoslav Ryhel	 */
33*b68e6e0dSSvyatoslav Ryhel	chosen { };
34*b68e6e0dSSvyatoslav Ryhel
35*b68e6e0dSSvyatoslav Ryhel	firmware {
36*b68e6e0dSSvyatoslav Ryhel		trusted-foundations {
37*b68e6e0dSSvyatoslav Ryhel			compatible = "tlm,trusted-foundations";
38*b68e6e0dSSvyatoslav Ryhel			tlm,version-major = <2>;
39*b68e6e0dSSvyatoslav Ryhel			tlm,version-minor = <8>;
40*b68e6e0dSSvyatoslav Ryhel		};
41*b68e6e0dSSvyatoslav Ryhel	};
42*b68e6e0dSSvyatoslav Ryhel
43*b68e6e0dSSvyatoslav Ryhel	memory@80000000 {
44*b68e6e0dSSvyatoslav Ryhel		reg = <0x80000000 0x40000000>;
45*b68e6e0dSSvyatoslav Ryhel	};
46*b68e6e0dSSvyatoslav Ryhel
47*b68e6e0dSSvyatoslav Ryhel	reserved-memory {
48*b68e6e0dSSvyatoslav Ryhel		#address-cells = <1>;
49*b68e6e0dSSvyatoslav Ryhel		#size-cells = <1>;
50*b68e6e0dSSvyatoslav Ryhel		ranges;
51*b68e6e0dSSvyatoslav Ryhel
52*b68e6e0dSSvyatoslav Ryhel		linux,cma@80000000 {
53*b68e6e0dSSvyatoslav Ryhel			compatible = "shared-dma-pool";
54*b68e6e0dSSvyatoslav Ryhel			alloc-ranges = <0x80000000 0x30000000>;
55*b68e6e0dSSvyatoslav Ryhel			size = <0x10000000>;		/* 256MiB */
56*b68e6e0dSSvyatoslav Ryhel			linux,cma-default;
57*b68e6e0dSSvyatoslav Ryhel			reusable;
58*b68e6e0dSSvyatoslav Ryhel		};
59*b68e6e0dSSvyatoslav Ryhel
60*b68e6e0dSSvyatoslav Ryhel		ramoops@bed00000 {
61*b68e6e0dSSvyatoslav Ryhel			compatible = "ramoops";
62*b68e6e0dSSvyatoslav Ryhel			reg = <0xbed00000 0x10000>;	/* 64kB */
63*b68e6e0dSSvyatoslav Ryhel			console-size = <0x8000>;	/* 32kB */
64*b68e6e0dSSvyatoslav Ryhel			record-size = <0x400>;		/* 1kB */
65*b68e6e0dSSvyatoslav Ryhel			ecc-size = <16>;
66*b68e6e0dSSvyatoslav Ryhel		};
67*b68e6e0dSSvyatoslav Ryhel
68*b68e6e0dSSvyatoslav Ryhel		trustzone@bfe00000 {
69*b68e6e0dSSvyatoslav Ryhel			reg = <0xbfe00000 0x200000>;	/* 2MB */
70*b68e6e0dSSvyatoslav Ryhel			no-map;
71*b68e6e0dSSvyatoslav Ryhel		};
72*b68e6e0dSSvyatoslav Ryhel	};
73*b68e6e0dSSvyatoslav Ryhel
74*b68e6e0dSSvyatoslav Ryhel	vde@6001a000 {
75*b68e6e0dSSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
76*b68e6e0dSSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
77*b68e6e0dSSvyatoslav Ryhel		assigned-clock-rates = <408000000>;
78*b68e6e0dSSvyatoslav Ryhel	};
79*b68e6e0dSSvyatoslav Ryhel
80*b68e6e0dSSvyatoslav Ryhel	pinmux@70000868 {
81*b68e6e0dSSvyatoslav Ryhel		pinctrl-names = "default";
82*b68e6e0dSSvyatoslav Ryhel		pinctrl-0 = <&state_default>;
83*b68e6e0dSSvyatoslav Ryhel
84*b68e6e0dSSvyatoslav Ryhel		state_default: pinmux {
85*b68e6e0dSSvyatoslav Ryhel			/* WLAN SDIO pinmux */
86*b68e6e0dSSvyatoslav Ryhel			sdmmc1-clk {
87*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "sdmmc1_clk_pz0";
88*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "sdmmc1";
89*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
91*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92*b68e6e0dSSvyatoslav Ryhel			};
93*b68e6e0dSSvyatoslav Ryhel			sdmmc1-cmd {
94*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "sdmmc1_cmd_pz1",
95*b68e6e0dSSvyatoslav Ryhel						"sdmmc1_dat3_py4",
96*b68e6e0dSSvyatoslav Ryhel						"sdmmc1_dat2_py5",
97*b68e6e0dSSvyatoslav Ryhel						"sdmmc1_dat1_py6",
98*b68e6e0dSSvyatoslav Ryhel						"sdmmc1_dat0_py7";
99*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "sdmmc1";
100*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
101*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
102*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
103*b68e6e0dSSvyatoslav Ryhel			};
104*b68e6e0dSSvyatoslav Ryhel			wlan-reset {
105*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pv3";
106*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
107*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
109*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
110*b68e6e0dSSvyatoslav Ryhel			};
111*b68e6e0dSSvyatoslav Ryhel			wlan-host-wake {
112*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu6";
113*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "pwm3";
114*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
115*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
116*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
117*b68e6e0dSSvyatoslav Ryhel			};
118*b68e6e0dSSvyatoslav Ryhel
119*b68e6e0dSSvyatoslav Ryhel			/* GNSS UART-B pinmux */
120*b68e6e0dSSvyatoslav Ryhel			gps-pwr-en {
121*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row6_pr6";
122*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
123*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
124*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
125*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
126*b68e6e0dSSvyatoslav Ryhel			};
127*b68e6e0dSSvyatoslav Ryhel			gps-ldo-en {
128*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_dir_py1";
129*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
130*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
131*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
132*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
133*b68e6e0dSSvyatoslav Ryhel			};
134*b68e6e0dSSvyatoslav Ryhel			gps-clk-ref {
135*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_ad8_ph0";
136*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
137*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
139*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
140*b68e6e0dSSvyatoslav Ryhel			};
141*b68e6e0dSSvyatoslav Ryhel
142*b68e6e0dSSvyatoslav Ryhel			/* Bluetooth UART-C pinmux */
143*b68e6e0dSSvyatoslav Ryhel			uartc-cts-rxd {
144*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "uart3_cts_n_pa1",
145*b68e6e0dSSvyatoslav Ryhel						"uart3_rxd_pw7";
146*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uartc";
147*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
149*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150*b68e6e0dSSvyatoslav Ryhel			};
151*b68e6e0dSSvyatoslav Ryhel			uartc-rts-txd {
152*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "uart3_rts_n_pc0",
153*b68e6e0dSSvyatoslav Ryhel						"uart3_txd_pw6";
154*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uartc";
155*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
157*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
158*b68e6e0dSSvyatoslav Ryhel			};
159*b68e6e0dSSvyatoslav Ryhel			bt-reset {
160*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "clk2_req_pcc5";
161*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "dap";
162*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
164*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
165*b68e6e0dSSvyatoslav Ryhel			};
166*b68e6e0dSSvyatoslav Ryhel			bt-dev-wake {
167*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row11_ps3";
168*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
169*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
170*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
171*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
172*b68e6e0dSSvyatoslav Ryhel			};
173*b68e6e0dSSvyatoslav Ryhel			bt-host-wake {
174*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row12_ps4";
175*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
176*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
177*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
178*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
179*b68e6e0dSSvyatoslav Ryhel			};
180*b68e6e0dSSvyatoslav Ryhel			bt-pcm-dap4 {
181*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "dap4_fs_pp4",
182*b68e6e0dSSvyatoslav Ryhel						"dap4_din_pp5",
183*b68e6e0dSSvyatoslav Ryhel						"dap4_dout_pp6",
184*b68e6e0dSSvyatoslav Ryhel						"dap4_sclk_pp7";
185*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2s3";
186*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
188*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189*b68e6e0dSSvyatoslav Ryhel			};
190*b68e6e0dSSvyatoslav Ryhel
191*b68e6e0dSSvyatoslav Ryhel			/* EMMC pinmux */
192*b68e6e0dSSvyatoslav Ryhel			sdmmc4-clk {
193*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_clk_pcc4";
194*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "sdmmc4";
195*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
197*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
198*b68e6e0dSSvyatoslav Ryhel			};
199*b68e6e0dSSvyatoslav Ryhel			sdmmc4-data {
200*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_cmd_pt7",
201*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat0_paa0",
202*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat1_paa1",
203*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat2_paa2",
204*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat3_paa3",
205*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat4_paa4",
206*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat5_paa5",
207*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat6_paa6",
208*b68e6e0dSSvyatoslav Ryhel						"sdmmc4_dat7_paa7";
209*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "sdmmc4";
210*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
211*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
212*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
213*b68e6e0dSSvyatoslav Ryhel			};
214*b68e6e0dSSvyatoslav Ryhel			sdmmc4-reset {
215*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_rst_n_pcc3";
216*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
217*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
218*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
219*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220*b68e6e0dSSvyatoslav Ryhel			};
221*b68e6e0dSSvyatoslav Ryhel
222*b68e6e0dSSvyatoslav Ryhel			/* I2C pinmux */
223*b68e6e0dSSvyatoslav Ryhel			gen1-i2c {
224*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gen1_i2c_scl_pc4",
225*b68e6e0dSSvyatoslav Ryhel						"gen1_i2c_sda_pc5";
226*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2c1";
227*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
228*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
229*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230*b68e6e0dSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
231*b68e6e0dSSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
232*b68e6e0dSSvyatoslav Ryhel			};
233*b68e6e0dSSvyatoslav Ryhel			gen2-i2c {
234*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gen2_i2c_scl_pt5",
235*b68e6e0dSSvyatoslav Ryhel						"gen2_i2c_sda_pt6";
236*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2c2";
237*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
239*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240*b68e6e0dSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
241*b68e6e0dSSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
242*b68e6e0dSSvyatoslav Ryhel			};
243*b68e6e0dSSvyatoslav Ryhel			cam-i2c {
244*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "cam_i2c_scl_pbb1",
245*b68e6e0dSSvyatoslav Ryhel						"cam_i2c_sda_pbb2";
246*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2c3";
247*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
249*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
250*b68e6e0dSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
251*b68e6e0dSSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
252*b68e6e0dSSvyatoslav Ryhel			};
253*b68e6e0dSSvyatoslav Ryhel			ddc-i2c {
254*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ddc_scl_pv4",
255*b68e6e0dSSvyatoslav Ryhel						"ddc_sda_pv5";
256*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2c4";
257*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
258*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
259*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
260*b68e6e0dSSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
261*b68e6e0dSSvyatoslav Ryhel			};
262*b68e6e0dSSvyatoslav Ryhel			pwr-i2c {
263*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pwr_i2c_scl_pz6",
264*b68e6e0dSSvyatoslav Ryhel						"pwr_i2c_sda_pz7";
265*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2cpwr";
266*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
268*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269*b68e6e0dSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
270*b68e6e0dSSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
271*b68e6e0dSSvyatoslav Ryhel			};
272*b68e6e0dSSvyatoslav Ryhel			mhl-i2c {
273*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_col6_pq6",
274*b68e6e0dSSvyatoslav Ryhel						"kb_col7_pq7";
275*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
276*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
278*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
279*b68e6e0dSSvyatoslav Ryhel			};
280*b68e6e0dSSvyatoslav Ryhel
281*b68e6e0dSSvyatoslav Ryhel			/* GPIO keys pinmux */
282*b68e6e0dSSvyatoslav Ryhel			power-key {
283*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_wp_n_pc7";
284*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
285*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
286*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
287*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
288*b68e6e0dSSvyatoslav Ryhel			};
289*b68e6e0dSSvyatoslav Ryhel			volume-down {
290*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_data3_po4";
291*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi3";
292*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
293*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
294*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
295*b68e6e0dSSvyatoslav Ryhel			};
296*b68e6e0dSSvyatoslav Ryhel
297*b68e6e0dSSvyatoslav Ryhel			/* Sensors pinmux */
298*b68e6e0dSSvyatoslav Ryhel			sen-vdd {
299*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi1_miso_px7";
300*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
301*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
302*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
303*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
304*b68e6e0dSSvyatoslav Ryhel			};
305*b68e6e0dSSvyatoslav Ryhel			proxi-vdd {
306*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi2_miso_px1";
307*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
308*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
310*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
311*b68e6e0dSSvyatoslav Ryhel			};
312*b68e6e0dSSvyatoslav Ryhel			sen-vio {
313*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_dc1_pd2";
314*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
315*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
317*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
318*b68e6e0dSSvyatoslav Ryhel			};
319*b68e6e0dSSvyatoslav Ryhel			nct-irq {
320*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_iordy_pi5";
321*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
322*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
324*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
325*b68e6e0dSSvyatoslav Ryhel			};
326*b68e6e0dSSvyatoslav Ryhel			bat-irq {
327*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row8_ps0";
328*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
329*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
330*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
331*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
332*b68e6e0dSSvyatoslav Ryhel			};
333*b68e6e0dSSvyatoslav Ryhel			charger-irq {
334*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_cs1_n_pj2";
335*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
336*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
337*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
338*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
339*b68e6e0dSSvyatoslav Ryhel			};
340*b68e6e0dSSvyatoslav Ryhel			mpu-irq {
341*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_ad12_ph4";
342*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
343*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
344*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
345*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
346*b68e6e0dSSvyatoslav Ryhel			};
347*b68e6e0dSSvyatoslav Ryhel			compass-irq {
348*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_ad13_ph5";
349*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
350*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
351*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
352*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
353*b68e6e0dSSvyatoslav Ryhel			};
354*b68e6e0dSSvyatoslav Ryhel			light-irq {
355*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_cs4_n_pk2";
356*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
357*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
358*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
359*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
360*b68e6e0dSSvyatoslav Ryhel			};
361*b68e6e0dSSvyatoslav Ryhel
362*b68e6e0dSSvyatoslav Ryhel			/* LED pinmux */
363*b68e6e0dSSvyatoslav Ryhel			backlight-en {
364*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_dc0_pn6";
365*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd3";
366*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
367*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
368*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
369*b68e6e0dSSvyatoslav Ryhel			};
370*b68e6e0dSSvyatoslav Ryhel			flash-led-en {
371*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pbb3";
372*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "vgp3";
373*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
375*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
376*b68e6e0dSSvyatoslav Ryhel			};
377*b68e6e0dSSvyatoslav Ryhel			keypad-led {
378*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row2_pr2",
379*b68e6e0dSSvyatoslav Ryhel						"kb_row3_pr3";
380*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd3";
381*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
382*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
383*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
384*b68e6e0dSSvyatoslav Ryhel			};
385*b68e6e0dSSvyatoslav Ryhel
386*b68e6e0dSSvyatoslav Ryhel			/* NFC pinmux */
387*b68e6e0dSSvyatoslav Ryhel			nfc-irq {
388*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi2_cs1_n_pw2";
389*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi2";
390*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
392*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393*b68e6e0dSSvyatoslav Ryhel			};
394*b68e6e0dSSvyatoslav Ryhel			nfc-ven {
395*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi1_sck_px5";
396*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi1";
397*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
398*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
399*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400*b68e6e0dSSvyatoslav Ryhel			};
401*b68e6e0dSSvyatoslav Ryhel			nfc-firm {
402*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row0_pr0";
403*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
404*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
406*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
407*b68e6e0dSSvyatoslav Ryhel			};
408*b68e6e0dSSvyatoslav Ryhel
409*b68e6e0dSSvyatoslav Ryhel			/* DC pinmux */
410*b68e6e0dSSvyatoslav Ryhel			lcd-pwr {
411*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_pwr0_pb2",
412*b68e6e0dSSvyatoslav Ryhel						"lcd_pwr1_pc1";
413*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
414*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
416*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
417*b68e6e0dSSvyatoslav Ryhel			};
418*b68e6e0dSSvyatoslav Ryhel			lcd-wr-n {
419*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_wr_n_pz3";
420*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
421*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
422*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
423*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
424*b68e6e0dSSvyatoslav Ryhel			};
425*b68e6e0dSSvyatoslav Ryhel			lcd-id {
426*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_m1_pw1";
427*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
428*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
430*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431*b68e6e0dSSvyatoslav Ryhel			};
432*b68e6e0dSSvyatoslav Ryhel			lcd-pclk {
433*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_pclk_pb3",
434*b68e6e0dSSvyatoslav Ryhel						"lcd_de_pj1",
435*b68e6e0dSSvyatoslav Ryhel						"lcd_hsync_pj3",
436*b68e6e0dSSvyatoslav Ryhel						"lcd_vsync_pj4";
437*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
438*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
439*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
440*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
441*b68e6e0dSSvyatoslav Ryhel			};
442*b68e6e0dSSvyatoslav Ryhel			lcd-rgb-blue {
443*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_d0_pe0",
444*b68e6e0dSSvyatoslav Ryhel						"lcd_d1_pe1",
445*b68e6e0dSSvyatoslav Ryhel						"lcd_d2_pe2",
446*b68e6e0dSSvyatoslav Ryhel						"lcd_d3_pe3",
447*b68e6e0dSSvyatoslav Ryhel						"lcd_d4_pe4",
448*b68e6e0dSSvyatoslav Ryhel						"lcd_d5_pe5",
449*b68e6e0dSSvyatoslav Ryhel						"lcd_d18_pm2",
450*b68e6e0dSSvyatoslav Ryhel						"lcd_d19_pm3";
451*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
452*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
454*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
455*b68e6e0dSSvyatoslav Ryhel			};
456*b68e6e0dSSvyatoslav Ryhel			lcd-rgb-green {
457*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_d6_pe6",
458*b68e6e0dSSvyatoslav Ryhel						"lcd_d7_pe7",
459*b68e6e0dSSvyatoslav Ryhel						"lcd_d8_pf0",
460*b68e6e0dSSvyatoslav Ryhel						"lcd_d9_pf1",
461*b68e6e0dSSvyatoslav Ryhel						"lcd_d10_pf2",
462*b68e6e0dSSvyatoslav Ryhel						"lcd_d11_pf3",
463*b68e6e0dSSvyatoslav Ryhel						"lcd_d20_pm4",
464*b68e6e0dSSvyatoslav Ryhel						"lcd_d21_pm5";
465*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
466*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
468*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469*b68e6e0dSSvyatoslav Ryhel			};
470*b68e6e0dSSvyatoslav Ryhel			lcd-rgb-red {
471*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_d12_pf4",
472*b68e6e0dSSvyatoslav Ryhel						"lcd_d13_pf5",
473*b68e6e0dSSvyatoslav Ryhel						"lcd_d14_pf6",
474*b68e6e0dSSvyatoslav Ryhel						"lcd_d15_pf7",
475*b68e6e0dSSvyatoslav Ryhel						"lcd_d16_pm0",
476*b68e6e0dSSvyatoslav Ryhel						"lcd_d17_pm1",
477*b68e6e0dSSvyatoslav Ryhel						"lcd_d22_pm6",
478*b68e6e0dSSvyatoslav Ryhel						"lcd_d23_pm7";
479*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "displaya";
480*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
481*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
482*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
483*b68e6e0dSSvyatoslav Ryhel			};
484*b68e6e0dSSvyatoslav Ryhel
485*b68e6e0dSSvyatoslav Ryhel			/* Bridge pinmux */
486*b68e6e0dSSvyatoslav Ryhel			bridge-reset {
487*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_data1_po2";
488*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi3";
489*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
490*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
491*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
492*b68e6e0dSSvyatoslav Ryhel			};
493*b68e6e0dSSvyatoslav Ryhel			rgb-ic-en {
494*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_a18_pb1";
495*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uartd";
496*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
497*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
498*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
499*b68e6e0dSSvyatoslav Ryhel			};
500*b68e6e0dSSvyatoslav Ryhel			bridge-clk {
501*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "clk3_out_pee0";
502*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "extperiph3";
503*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
505*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506*b68e6e0dSSvyatoslav Ryhel			};
507*b68e6e0dSSvyatoslav Ryhel			rgb-bridge {
508*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_sdin_pz2",
509*b68e6e0dSSvyatoslav Ryhel						"lcd_sdout_pn5",
510*b68e6e0dSSvyatoslav Ryhel						"lcd_cs0_n_pn4",
511*b68e6e0dSSvyatoslav Ryhel						"lcd_sck_pz4";
512*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi5";
513*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
514*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
515*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
516*b68e6e0dSSvyatoslav Ryhel			};
517*b68e6e0dSSvyatoslav Ryhel
518*b68e6e0dSSvyatoslav Ryhel			/* Panel pinmux */
519*b68e6e0dSSvyatoslav Ryhel			panel-reset {
520*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "lcd_cs1_n_pw0";
521*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
522*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
523*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
524*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
525*b68e6e0dSSvyatoslav Ryhel			};
526*b68e6e0dSSvyatoslav Ryhel			panel-vio {
527*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_clk_py0";
528*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
529*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
530*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
531*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
532*b68e6e0dSSvyatoslav Ryhel			};
533*b68e6e0dSSvyatoslav Ryhel
534*b68e6e0dSSvyatoslav Ryhel			/* Touchscreen pinmux */
535*b68e6e0dSSvyatoslav Ryhel			touch-vdd {
536*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_col1_pq1";
537*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
538*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
539*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
540*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
541*b68e6e0dSSvyatoslav Ryhel			};
542*b68e6e0dSSvyatoslav Ryhel			touch-vio {
543*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi1_mosi_px4";
544*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi2";
545*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
547*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
548*b68e6e0dSSvyatoslav Ryhel			};
549*b68e6e0dSSvyatoslav Ryhel			touch-irq-n {
550*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_col3_pq3";
551*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
552*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
553*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
554*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555*b68e6e0dSSvyatoslav Ryhel			};
556*b68e6e0dSSvyatoslav Ryhel			touch-rst-n {
557*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_data0_po1";
558*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi3";
559*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
560*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
561*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
562*b68e6e0dSSvyatoslav Ryhel			};
563*b68e6e0dSSvyatoslav Ryhel			touch-maker-id {
564*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_col2_pq2";
565*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
566*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
567*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
568*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
569*b68e6e0dSSvyatoslav Ryhel			};
570*b68e6e0dSSvyatoslav Ryhel
571*b68e6e0dSSvyatoslav Ryhel			/* MHL pinmux */
572*b68e6e0dSSvyatoslav Ryhel			mhl-vio {
573*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pv2";
574*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "owr";
575*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
577*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
578*b68e6e0dSSvyatoslav Ryhel			};
579*b68e6e0dSSvyatoslav Ryhel			mhl-rst-n {
580*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "clk3_req_pee1";
581*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "dev3";
582*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
583*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
584*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
585*b68e6e0dSSvyatoslav Ryhel			};
586*b68e6e0dSSvyatoslav Ryhel			mhl-irq {
587*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "crt_vsync_pv7";
588*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
589*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
590*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
591*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592*b68e6e0dSSvyatoslav Ryhel			};
593*b68e6e0dSSvyatoslav Ryhel			mhl-sel {
594*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row10_ps2";
595*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
596*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
597*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
598*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
599*b68e6e0dSSvyatoslav Ryhel			};
600*b68e6e0dSSvyatoslav Ryhel			hdmi-hpd {
601*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "hdmi_int_pn7";
602*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "hdmi";
603*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
605*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606*b68e6e0dSSvyatoslav Ryhel			};
607*b68e6e0dSSvyatoslav Ryhel
608*b68e6e0dSSvyatoslav Ryhel			/* AUDIO pinmux */
609*b68e6e0dSSvyatoslav Ryhel			hp-detect {
610*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pbb6";
611*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "vgp6";
612*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
614*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615*b68e6e0dSSvyatoslav Ryhel			};
616*b68e6e0dSSvyatoslav Ryhel			hp-hook {
617*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_data4_po5";
618*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "ulpi";
619*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
620*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
621*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
622*b68e6e0dSSvyatoslav Ryhel			};
623*b68e6e0dSSvyatoslav Ryhel			ear-mic-en {
624*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi2_mosi_px0";
625*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi2";
626*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
627*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
628*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
629*b68e6e0dSSvyatoslav Ryhel			};
630*b68e6e0dSSvyatoslav Ryhel			audio-irq {
631*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "spi2_cs2_n_pw3";
632*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi3";
633*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
634*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
635*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
636*b68e6e0dSSvyatoslav Ryhel			};
637*b68e6e0dSSvyatoslav Ryhel			audio-mclk {
638*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "clk1_out_pw4";
639*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "extperiph1";
640*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
641*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
642*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
643*b68e6e0dSSvyatoslav Ryhel			};
644*b68e6e0dSSvyatoslav Ryhel			dap-i2s0 {
645*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "dap1_fs_pn0",
646*b68e6e0dSSvyatoslav Ryhel						"dap1_din_pn1",
647*b68e6e0dSSvyatoslav Ryhel						"dap1_dout_pn2",
648*b68e6e0dSSvyatoslav Ryhel						"dap1_sclk_pn3";
649*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2s0";
650*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
651*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
652*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
653*b68e6e0dSSvyatoslav Ryhel			};
654*b68e6e0dSSvyatoslav Ryhel			dap-i2s1 {
655*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "dap2_fs_pa2",
656*b68e6e0dSSvyatoslav Ryhel						"dap2_sclk_pa3",
657*b68e6e0dSSvyatoslav Ryhel						"dap2_din_pa4",
658*b68e6e0dSSvyatoslav Ryhel						"dap2_dout_pa5";
659*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2s1";
660*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
661*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
662*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
663*b68e6e0dSSvyatoslav Ryhel			};
664*b68e6e0dSSvyatoslav Ryhel
665*b68e6e0dSSvyatoslav Ryhel			/* MUIC pinmux */
666*b68e6e0dSSvyatoslav Ryhel			muic-irq {
667*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_cs0_n_pj0";
668*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
669*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
670*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
671*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
672*b68e6e0dSSvyatoslav Ryhel			};
673*b68e6e0dSSvyatoslav Ryhel			muic-dp2t {
674*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pcc2";
675*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
676*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
678*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679*b68e6e0dSSvyatoslav Ryhel			};
680*b68e6e0dSSvyatoslav Ryhel			muic-usif {
681*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_stp_py3";
682*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "spi1";
683*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
684*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
685*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
686*b68e6e0dSSvyatoslav Ryhel			};
687*b68e6e0dSSvyatoslav Ryhel			ifx-usb-vbus-en {
688*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row4_pr4";
689*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
690*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
691*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
692*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
693*b68e6e0dSSvyatoslav Ryhel			};
694*b68e6e0dSSvyatoslav Ryhel			pcb-rev {
695*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_wait_pi7",
696*b68e6e0dSSvyatoslav Ryhel						"gmi_rst_n_pi4";
697*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
698*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
699*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
700*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
701*b68e6e0dSSvyatoslav Ryhel			};
702*b68e6e0dSSvyatoslav Ryhel			jtag-rtck {
703*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "jtag_rtck_pu7";
704*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rtck";
705*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
706*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
707*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
708*b68e6e0dSSvyatoslav Ryhel			};
709*b68e6e0dSSvyatoslav Ryhel
710*b68e6e0dSSvyatoslav Ryhel			/* Camera pinmux */
711*b68e6e0dSSvyatoslav Ryhel			cam-mclk {
712*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "cam_mclk_pcc0";
713*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "vi_alt3";
714*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
715*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
716*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
717*b68e6e0dSSvyatoslav Ryhel			};
718*b68e6e0dSSvyatoslav Ryhel			cam-pmic-en {
719*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pbb4";
720*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "vgp4";
721*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
722*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
723*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
724*b68e6e0dSSvyatoslav Ryhel			};
725*b68e6e0dSSvyatoslav Ryhel			front-cam-rst {
726*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pbb5";
727*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "vgp5";
728*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
729*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
730*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
731*b68e6e0dSSvyatoslav Ryhel			};
732*b68e6e0dSSvyatoslav Ryhel			front-cam-vio {
733*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_nxt_py2";
734*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd2";
735*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
736*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
737*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
738*b68e6e0dSSvyatoslav Ryhel			};
739*b68e6e0dSSvyatoslav Ryhel			rear-cam-rst {
740*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_cs3_n_pk4";
741*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
742*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
743*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
744*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
745*b68e6e0dSSvyatoslav Ryhel			};
746*b68e6e0dSSvyatoslav Ryhel			rear-cam-eprom-pr {
747*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_cs2_n_pk3";
748*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
749*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
750*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
751*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
752*b68e6e0dSSvyatoslav Ryhel			};
753*b68e6e0dSSvyatoslav Ryhel			rear-cam-vcm-pwdn {
754*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row1_pr1";
755*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
756*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
757*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
758*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
759*b68e6e0dSSvyatoslav Ryhel			};
760*b68e6e0dSSvyatoslav Ryhel
761*b68e6e0dSSvyatoslav Ryhel			/* Haptic pinmux */
762*b68e6e0dSSvyatoslav Ryhel			haptic-en {
763*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_ad9_ph1";
764*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "gmi";
765*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
766*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
767*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
768*b68e6e0dSSvyatoslav Ryhel			};
769*b68e6e0dSSvyatoslav Ryhel			haptic-osc {
770*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "gmi_ad11_ph3";
771*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "pwm3";
772*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
773*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
774*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
775*b68e6e0dSSvyatoslav Ryhel			};
776*b68e6e0dSSvyatoslav Ryhel
777*b68e6e0dSSvyatoslav Ryhel			/* Modem pinmux */
778*b68e6e0dSSvyatoslav Ryhel			cp2ap-ack1-host-active {
779*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu5";
780*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
781*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
782*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
783*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
784*b68e6e0dSSvyatoslav Ryhel			};
785*b68e6e0dSSvyatoslav Ryhel			cp2ap-ack2-host-wakeup {
786*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pv0";
787*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd4";
788*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
789*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
790*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
791*b68e6e0dSSvyatoslav Ryhel			};
792*b68e6e0dSSvyatoslav Ryhel			ap2cp-ack2-suspend-req {
793*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row14_ps6";
794*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
795*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
797*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
798*b68e6e0dSSvyatoslav Ryhel			};
799*b68e6e0dSSvyatoslav Ryhel			ap2cp-ack1-slave-wakeup {
800*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row15_ps7";
801*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
802*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
803*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
804*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
805*b68e6e0dSSvyatoslav Ryhel			};
806*b68e6e0dSSvyatoslav Ryhel			cp-kkp {
807*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_col0_pq0";
808*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
809*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
810*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
811*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
812*b68e6e0dSSvyatoslav Ryhel			};
813*b68e6e0dSSvyatoslav Ryhel			cp-crash-irq {
814*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "kb_row13_ps5";
815*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "kbc";
816*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
817*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
818*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
819*b68e6e0dSSvyatoslav Ryhel			};
820*b68e6e0dSSvyatoslav Ryhel			ap2cp-uarta-tx-ipc {
821*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu0";
822*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uarta";
823*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
825*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
826*b68e6e0dSSvyatoslav Ryhel			};
827*b68e6e0dSSvyatoslav Ryhel			ap2cp-uarta-rx-ipc {
828*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu1";
829*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uarta";
830*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
831*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
832*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
833*b68e6e0dSSvyatoslav Ryhel			};
834*b68e6e0dSSvyatoslav Ryhel			fota-ap-cts-cp-rts {
835*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu2";
836*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uarta";
837*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
838*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
839*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
840*b68e6e0dSSvyatoslav Ryhel			};
841*b68e6e0dSSvyatoslav Ryhel			fota-ap-rts-cp-cts {
842*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pu3";
843*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "uarta";
844*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
845*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
846*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
847*b68e6e0dSSvyatoslav Ryhel			};
848*b68e6e0dSSvyatoslav Ryhel			modem-enable {
849*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "ulpi_data7_po0";
850*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "hsi";
851*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
852*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
853*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
854*b68e6e0dSSvyatoslav Ryhel			};
855*b68e6e0dSSvyatoslav Ryhel			modem-reset {
856*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "pv1";
857*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "rsvd1";
858*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
859*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
860*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
861*b68e6e0dSSvyatoslav Ryhel			};
862*b68e6e0dSSvyatoslav Ryhel			dap-i2s2 {
863*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "dap3_fs_pp0",
864*b68e6e0dSSvyatoslav Ryhel						"dap3_din_pp1",
865*b68e6e0dSSvyatoslav Ryhel						"dap3_dout_pp2",
866*b68e6e0dSSvyatoslav Ryhel						"dap3_sclk_pp3";
867*b68e6e0dSSvyatoslav Ryhel				nvidia,function = "i2s2";
868*b68e6e0dSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
869*b68e6e0dSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
870*b68e6e0dSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
871*b68e6e0dSSvyatoslav Ryhel			};
872*b68e6e0dSSvyatoslav Ryhel
873*b68e6e0dSSvyatoslav Ryhel			/* GPIO power/drive control */
874*b68e6e0dSSvyatoslav Ryhel			drive-i2c {
875*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "drive_dbg",
876*b68e6e0dSSvyatoslav Ryhel						"drive_at5",
877*b68e6e0dSSvyatoslav Ryhel						"drive_gme",
878*b68e6e0dSSvyatoslav Ryhel						"drive_ddc",
879*b68e6e0dSSvyatoslav Ryhel						"drive_ao1";
880*b68e6e0dSSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
881*b68e6e0dSSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
882*b68e6e0dSSvyatoslav Ryhel				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
883*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-down-strength = <31>;
884*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-up-strength = <31>;
885*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
886*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
887*b68e6e0dSSvyatoslav Ryhel			};
888*b68e6e0dSSvyatoslav Ryhel
889*b68e6e0dSSvyatoslav Ryhel			drive-uart3 {
890*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "drive_uart3";
891*b68e6e0dSSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
892*b68e6e0dSSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
893*b68e6e0dSSvyatoslav Ryhel				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
894*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-down-strength = <31>;
895*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-up-strength = <31>;
896*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
897*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
898*b68e6e0dSSvyatoslav Ryhel			};
899*b68e6e0dSSvyatoslav Ryhel
900*b68e6e0dSSvyatoslav Ryhel			drive-gmi {
901*b68e6e0dSSvyatoslav Ryhel				nvidia,pins = "drive_at3";
902*b68e6e0dSSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
903*b68e6e0dSSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
904*b68e6e0dSSvyatoslav Ryhel				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
905*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-down-strength = <31>;
906*b68e6e0dSSvyatoslav Ryhel				nvidia,pull-up-strength = <31>;
907*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
908*b68e6e0dSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
909*b68e6e0dSSvyatoslav Ryhel			};
910*b68e6e0dSSvyatoslav Ryhel		};
911*b68e6e0dSSvyatoslav Ryhel	};
912*b68e6e0dSSvyatoslav Ryhel
913*b68e6e0dSSvyatoslav Ryhel	uartb: serial@70006040 {
914*b68e6e0dSSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
915*b68e6e0dSSvyatoslav Ryhel		reset-names = "serial";
916*b68e6e0dSSvyatoslav Ryhel		/delete-property/ reg-shift;
917*b68e6e0dSSvyatoslav Ryhel		status = "okay";
918*b68e6e0dSSvyatoslav Ryhel
919*b68e6e0dSSvyatoslav Ryhel		/* GNSS GSD5T */
920*b68e6e0dSSvyatoslav Ryhel	};
921*b68e6e0dSSvyatoslav Ryhel
922*b68e6e0dSSvyatoslav Ryhel	uartc: serial@70006200 {
923*b68e6e0dSSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
924*b68e6e0dSSvyatoslav Ryhel		reset-names = "serial";
925*b68e6e0dSSvyatoslav Ryhel		/delete-property/ reg-shift;
926*b68e6e0dSSvyatoslav Ryhel		status = "okay";
927*b68e6e0dSSvyatoslav Ryhel
928*b68e6e0dSSvyatoslav Ryhel		nvidia,adjust-baud-rates = <0 9600 100>,
929*b68e6e0dSSvyatoslav Ryhel					   <9600 115200 200>,
930*b68e6e0dSSvyatoslav Ryhel					   <1000000 4000000 136>;
931*b68e6e0dSSvyatoslav Ryhel
932*b68e6e0dSSvyatoslav Ryhel		/* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */
933*b68e6e0dSSvyatoslav Ryhel		bluetooth {
934*b68e6e0dSSvyatoslav Ryhel			compatible = "brcm,bcm4330-bt";
935*b68e6e0dSSvyatoslav Ryhel			max-speed = <4000000>;
936*b68e6e0dSSvyatoslav Ryhel
937*b68e6e0dSSvyatoslav Ryhel			clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
938*b68e6e0dSSvyatoslav Ryhel			clock-names = "txco";
939*b68e6e0dSSvyatoslav Ryhel
940*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
941*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(S, 4) IRQ_TYPE_EDGE_RISING>;
942*b68e6e0dSSvyatoslav Ryhel			interrupt-names = "host-wakeup";
943*b68e6e0dSSvyatoslav Ryhel
944*b68e6e0dSSvyatoslav Ryhel			device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
945*b68e6e0dSSvyatoslav Ryhel			shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
946*b68e6e0dSSvyatoslav Ryhel
947*b68e6e0dSSvyatoslav Ryhel			vbat-supply = <&vdd_3v3_vbat>;
948*b68e6e0dSSvyatoslav Ryhel			vddio-supply = <&vdd_1v8_vio>;
949*b68e6e0dSSvyatoslav Ryhel		};
950*b68e6e0dSSvyatoslav Ryhel	};
951*b68e6e0dSSvyatoslav Ryhel
952*b68e6e0dSSvyatoslav Ryhel	uartd: serial@70006300 {
953*b68e6e0dSSvyatoslav Ryhel		/delete-property/ dmas;
954*b68e6e0dSSvyatoslav Ryhel		/delete-property/ dma-names;
955*b68e6e0dSSvyatoslav Ryhel		status = "okay";
956*b68e6e0dSSvyatoslav Ryhel
957*b68e6e0dSSvyatoslav Ryhel		/* Console */
958*b68e6e0dSSvyatoslav Ryhel	};
959*b68e6e0dSSvyatoslav Ryhel
960*b68e6e0dSSvyatoslav Ryhel	pwm@7000a000 {
961*b68e6e0dSSvyatoslav Ryhel		status = "okay";
962*b68e6e0dSSvyatoslav Ryhel	};
963*b68e6e0dSSvyatoslav Ryhel
964*b68e6e0dSSvyatoslav Ryhel	gen1_i2c: i2c@7000c000 {
965*b68e6e0dSSvyatoslav Ryhel		status = "okay";
966*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <400000>;
967*b68e6e0dSSvyatoslav Ryhel
968*b68e6e0dSSvyatoslav Ryhel		/* Aichi AMI306 digital compass */
969*b68e6e0dSSvyatoslav Ryhel		magnetometer@e {
970*b68e6e0dSSvyatoslav Ryhel			compatible = "asahi-kasei,ak8974";
971*b68e6e0dSSvyatoslav Ryhel			reg = <0x0e>;
972*b68e6e0dSSvyatoslav Ryhel
973*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
974*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_EDGE_RISING>;
975*b68e6e0dSSvyatoslav Ryhel
976*b68e6e0dSSvyatoslav Ryhel			avdd-supply = <&vdd_3v0_sen>;
977*b68e6e0dSSvyatoslav Ryhel			dvdd-supply = <&vdd_1v8_vio>;
978*b68e6e0dSSvyatoslav Ryhel
979*b68e6e0dSSvyatoslav Ryhel			mount-matrix = "-1",  "0",  "0",
980*b68e6e0dSSvyatoslav Ryhel					"0",  "1",  "0",
981*b68e6e0dSSvyatoslav Ryhel					"0",  "0", "-1";
982*b68e6e0dSSvyatoslav Ryhel		};
983*b68e6e0dSSvyatoslav Ryhel
984*b68e6e0dSSvyatoslav Ryhel		max98089: audio-codec@10 {
985*b68e6e0dSSvyatoslav Ryhel			compatible = "maxim,max98089";
986*b68e6e0dSSvyatoslav Ryhel			reg = <0x10>;
987*b68e6e0dSSvyatoslav Ryhel
988*b68e6e0dSSvyatoslav Ryhel			clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
989*b68e6e0dSSvyatoslav Ryhel			clock-names = "mclk";
990*b68e6e0dSSvyatoslav Ryhel
991*b68e6e0dSSvyatoslav Ryhel			assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
992*b68e6e0dSSvyatoslav Ryhel			assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>;
993*b68e6e0dSSvyatoslav Ryhel		};
994*b68e6e0dSSvyatoslav Ryhel
995*b68e6e0dSSvyatoslav Ryhel		nfc@28 {
996*b68e6e0dSSvyatoslav Ryhel			compatible = "nxp,pn544-i2c";
997*b68e6e0dSSvyatoslav Ryhel			reg = <0x28>;
998*b68e6e0dSSvyatoslav Ryhel
999*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1000*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
1001*b68e6e0dSSvyatoslav Ryhel
1002*b68e6e0dSSvyatoslav Ryhel			enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
1003*b68e6e0dSSvyatoslav Ryhel			firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
1004*b68e6e0dSSvyatoslav Ryhel		};
1005*b68e6e0dSSvyatoslav Ryhel
1006*b68e6e0dSSvyatoslav Ryhel		imu@68 {
1007*b68e6e0dSSvyatoslav Ryhel			compatible = "invensense,mpu6050";
1008*b68e6e0dSSvyatoslav Ryhel			reg = <0x68>;
1009*b68e6e0dSSvyatoslav Ryhel
1010*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1011*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_RISING>;
1012*b68e6e0dSSvyatoslav Ryhel
1013*b68e6e0dSSvyatoslav Ryhel			vdd-supply = <&vdd_3v0_sen>;
1014*b68e6e0dSSvyatoslav Ryhel			vddio-supply = <&vdd_1v8_sen>;
1015*b68e6e0dSSvyatoslav Ryhel
1016*b68e6e0dSSvyatoslav Ryhel			mount-matrix =  "1",  "0",  "0",
1017*b68e6e0dSSvyatoslav Ryhel					"0",  "1",  "0",
1018*b68e6e0dSSvyatoslav Ryhel					"0",  "0", "-1";
1019*b68e6e0dSSvyatoslav Ryhel		};
1020*b68e6e0dSSvyatoslav Ryhel	};
1021*b68e6e0dSSvyatoslav Ryhel
1022*b68e6e0dSSvyatoslav Ryhel	gen2_i2c: i2c@7000c400 {
1023*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1024*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <400000>;
1025*b68e6e0dSSvyatoslav Ryhel
1026*b68e6e0dSSvyatoslav Ryhel		/* Synaptics RMI4 S3203B touchcreen */
1027*b68e6e0dSSvyatoslav Ryhel		touchscreen@20 {
1028*b68e6e0dSSvyatoslav Ryhel			compatible = "syna,rmi4-i2c";
1029*b68e6e0dSSvyatoslav Ryhel			reg = <0x20>;
1030*b68e6e0dSSvyatoslav Ryhel
1031*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1032*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_EDGE_FALLING>;
1033*b68e6e0dSSvyatoslav Ryhel
1034*b68e6e0dSSvyatoslav Ryhel			vdd-supply = <&vdd_3v0_touch>;
1035*b68e6e0dSSvyatoslav Ryhel			vio-supply = <&vdd_1v8_touch>;
1036*b68e6e0dSSvyatoslav Ryhel
1037*b68e6e0dSSvyatoslav Ryhel			syna,reset-delay-ms = <20>;
1038*b68e6e0dSSvyatoslav Ryhel			syna,startup-delay-ms = <200>;
1039*b68e6e0dSSvyatoslav Ryhel
1040*b68e6e0dSSvyatoslav Ryhel			#address-cells = <1>;
1041*b68e6e0dSSvyatoslav Ryhel			#size-cells = <0>;
1042*b68e6e0dSSvyatoslav Ryhel
1043*b68e6e0dSSvyatoslav Ryhel			rmi4-f01@1 {
1044*b68e6e0dSSvyatoslav Ryhel				reg = <0x1>;
1045*b68e6e0dSSvyatoslav Ryhel				syna,nosleep-mode = <1>;
1046*b68e6e0dSSvyatoslav Ryhel			};
1047*b68e6e0dSSvyatoslav Ryhel
1048*b68e6e0dSSvyatoslav Ryhel			rmi4-f11@11 {
1049*b68e6e0dSSvyatoslav Ryhel				reg = <0x11>;
1050*b68e6e0dSSvyatoslav Ryhel				syna,sensor-type = <1>;
1051*b68e6e0dSSvyatoslav Ryhel
1052*b68e6e0dSSvyatoslav Ryhel				syna,clip-x-low = <0>;
1053*b68e6e0dSSvyatoslav Ryhel				syna,clip-y-low = <0>;
1054*b68e6e0dSSvyatoslav Ryhel			};
1055*b68e6e0dSSvyatoslav Ryhel		};
1056*b68e6e0dSSvyatoslav Ryhel	};
1057*b68e6e0dSSvyatoslav Ryhel
1058*b68e6e0dSSvyatoslav Ryhel	cam_i2c: i2c@7000c500 {
1059*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1060*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <400000>;
1061*b68e6e0dSSvyatoslav Ryhel
1062*b68e6e0dSSvyatoslav Ryhel		dw9714: coil@c {
1063*b68e6e0dSSvyatoslav Ryhel			compatible = "dongwoon,dw9714";
1064*b68e6e0dSSvyatoslav Ryhel			reg = <0x0c>;
1065*b68e6e0dSSvyatoslav Ryhel
1066*b68e6e0dSSvyatoslav Ryhel			enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>;
1067*b68e6e0dSSvyatoslav Ryhel
1068*b68e6e0dSSvyatoslav Ryhel			vcc-supply = <&vcc_focuser>;
1069*b68e6e0dSSvyatoslav Ryhel		};
1070*b68e6e0dSSvyatoslav Ryhel
1071*b68e6e0dSSvyatoslav Ryhel		camera-pmic@7d {
1072*b68e6e0dSSvyatoslav Ryhel			compatible = "ti,lp8720";
1073*b68e6e0dSSvyatoslav Ryhel			reg = <0x7d>;
1074*b68e6e0dSSvyatoslav Ryhel
1075*b68e6e0dSSvyatoslav Ryhel			enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
1076*b68e6e0dSSvyatoslav Ryhel
1077*b68e6e0dSSvyatoslav Ryhel			vt_1v2_front: ldo1 {
1078*b68e6e0dSSvyatoslav Ryhel				regulator-name = "vt_1v2_dig";
1079*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <1200000>;
1080*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <1200000>;
1081*b68e6e0dSSvyatoslav Ryhel			};
1082*b68e6e0dSSvyatoslav Ryhel
1083*b68e6e0dSSvyatoslav Ryhel			vt_2v7_front: ldo2 {
1084*b68e6e0dSSvyatoslav Ryhel				regulator-name = "vt_2v7_vana";
1085*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <2700000>;
1086*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <2700000>;
1087*b68e6e0dSSvyatoslav Ryhel			};
1088*b68e6e0dSSvyatoslav Ryhel
1089*b68e6e0dSSvyatoslav Ryhel			vdd_2v7_rear: ldo3 {
1090*b68e6e0dSSvyatoslav Ryhel				regulator-name = "8m_2v7_vana";
1091*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <2700000>;
1092*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <2800000>;
1093*b68e6e0dSSvyatoslav Ryhel			};
1094*b68e6e0dSSvyatoslav Ryhel
1095*b68e6e0dSSvyatoslav Ryhel			vio_1v8_rear: ldo4 {
1096*b68e6e0dSSvyatoslav Ryhel				regulator-name = "vio_1v8_cam";
1097*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <1800000>;
1098*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <1800000>;
1099*b68e6e0dSSvyatoslav Ryhel			};
1100*b68e6e0dSSvyatoslav Ryhel
1101*b68e6e0dSSvyatoslav Ryhel			vcc_focuser: ldo5 {
1102*b68e6e0dSSvyatoslav Ryhel				regulator-name = "8m_2v8_vcm";
1103*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <2800000>;
1104*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <2800000>;
1105*b68e6e0dSSvyatoslav Ryhel			};
1106*b68e6e0dSSvyatoslav Ryhel
1107*b68e6e0dSSvyatoslav Ryhel			vdd_1v2_rear: buck {
1108*b68e6e0dSSvyatoslav Ryhel				regulator-name = "8m_1v2_cam";
1109*b68e6e0dSSvyatoslav Ryhel				regulator-min-microvolt = <1200000>;
1110*b68e6e0dSSvyatoslav Ryhel				regulator-max-microvolt = <1200000>;
1111*b68e6e0dSSvyatoslav Ryhel			};
1112*b68e6e0dSSvyatoslav Ryhel		};
1113*b68e6e0dSSvyatoslav Ryhel	};
1114*b68e6e0dSSvyatoslav Ryhel
1115*b68e6e0dSSvyatoslav Ryhel	hdmi_ddc: i2c@7000c700 {
1116*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1117*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <100000>;
1118*b68e6e0dSSvyatoslav Ryhel	};
1119*b68e6e0dSSvyatoslav Ryhel
1120*b68e6e0dSSvyatoslav Ryhel	pwr_i2c: i2c@7000d000 {
1121*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1122*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <400000>;
1123*b68e6e0dSSvyatoslav Ryhel
1124*b68e6e0dSSvyatoslav Ryhel		pmic: max77663@1c {
1125*b68e6e0dSSvyatoslav Ryhel			compatible = "maxim,max77663";
1126*b68e6e0dSSvyatoslav Ryhel			reg = <0x1c>;
1127*b68e6e0dSSvyatoslav Ryhel
1128*b68e6e0dSSvyatoslav Ryhel			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1129*b68e6e0dSSvyatoslav Ryhel			#interrupt-cells = <2>;
1130*b68e6e0dSSvyatoslav Ryhel			interrupt-controller;
1131*b68e6e0dSSvyatoslav Ryhel
1132*b68e6e0dSSvyatoslav Ryhel			#gpio-cells = <2>;
1133*b68e6e0dSSvyatoslav Ryhel			gpio-controller;
1134*b68e6e0dSSvyatoslav Ryhel
1135*b68e6e0dSSvyatoslav Ryhel			system-power-controller;
1136*b68e6e0dSSvyatoslav Ryhel
1137*b68e6e0dSSvyatoslav Ryhel			pinctrl-names = "default";
1138*b68e6e0dSSvyatoslav Ryhel			pinctrl-0 = <&max77663_default>;
1139*b68e6e0dSSvyatoslav Ryhel
1140*b68e6e0dSSvyatoslav Ryhel			max77663_default: pinmux {
1141*b68e6e0dSSvyatoslav Ryhel				gpio1 {
1142*b68e6e0dSSvyatoslav Ryhel					pins = "gpio1";
1143*b68e6e0dSSvyatoslav Ryhel					function = "gpio";
1144*b68e6e0dSSvyatoslav Ryhel					drive-open-drain = <1>;
1145*b68e6e0dSSvyatoslav Ryhel				};
1146*b68e6e0dSSvyatoslav Ryhel
1147*b68e6e0dSSvyatoslav Ryhel				gpio4 {
1148*b68e6e0dSSvyatoslav Ryhel					pins = "gpio4";
1149*b68e6e0dSSvyatoslav Ryhel					function = "32k-out1";
1150*b68e6e0dSSvyatoslav Ryhel				};
1151*b68e6e0dSSvyatoslav Ryhel			};
1152*b68e6e0dSSvyatoslav Ryhel
1153*b68e6e0dSSvyatoslav Ryhel			fps {
1154*b68e6e0dSSvyatoslav Ryhel				fps0 {
1155*b68e6e0dSSvyatoslav Ryhel					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1156*b68e6e0dSSvyatoslav Ryhel				};
1157*b68e6e0dSSvyatoslav Ryhel
1158*b68e6e0dSSvyatoslav Ryhel				fps1 {
1159*b68e6e0dSSvyatoslav Ryhel					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
1160*b68e6e0dSSvyatoslav Ryhel				};
1161*b68e6e0dSSvyatoslav Ryhel
1162*b68e6e0dSSvyatoslav Ryhel				fps2 {
1163*b68e6e0dSSvyatoslav Ryhel					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1164*b68e6e0dSSvyatoslav Ryhel				};
1165*b68e6e0dSSvyatoslav Ryhel			};
1166*b68e6e0dSSvyatoslav Ryhel
1167*b68e6e0dSSvyatoslav Ryhel			regulators {
1168*b68e6e0dSSvyatoslav Ryhel				in-sd0-supply = <&vdd_5v0_vbus>;
1169*b68e6e0dSSvyatoslav Ryhel				in-sd1-supply = <&vdd_5v0_vbus>;
1170*b68e6e0dSSvyatoslav Ryhel				in-sd2-supply = <&vdd_5v0_vbus>;
1171*b68e6e0dSSvyatoslav Ryhel				in-sd3-supply = <&vdd_5v0_vbus>;
1172*b68e6e0dSSvyatoslav Ryhel
1173*b68e6e0dSSvyatoslav Ryhel				in-ldo0-1-supply = <&vdd_1v8_vio>;
1174*b68e6e0dSSvyatoslav Ryhel				in-ldo2-supply   = <&vdd_3v3_vbat>;
1175*b68e6e0dSSvyatoslav Ryhel				in-ldo3-5-supply = <&vdd_3v3_vbat>;
1176*b68e6e0dSSvyatoslav Ryhel				in-ldo4-6-supply = <&vdd_3v3_vbat>;
1177*b68e6e0dSSvyatoslav Ryhel				in-ldo7-8-supply = <&vdd_1v8_vio>;
1178*b68e6e0dSSvyatoslav Ryhel
1179*b68e6e0dSSvyatoslav Ryhel				vdd_cpu: sd0 {
1180*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_cpu";
1181*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <800000>;
1182*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1250000>;
1183*b68e6e0dSSvyatoslav Ryhel					regulator-coupled-with = <&vdd_core>;
1184*b68e6e0dSSvyatoslav Ryhel					regulator-coupled-max-spread = <300000>;
1185*b68e6e0dSSvyatoslav Ryhel					regulator-max-step-microvolt = <100000>;
1186*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1187*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1188*b68e6e0dSSvyatoslav Ryhel
1189*b68e6e0dSSvyatoslav Ryhel					nvidia,tegra-cpu-regulator;
1190*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1191*b68e6e0dSSvyatoslav Ryhel				};
1192*b68e6e0dSSvyatoslav Ryhel
1193*b68e6e0dSSvyatoslav Ryhel				vdd_core: sd1 {
1194*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_core";
1195*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <950000>;
1196*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1350000>;
1197*b68e6e0dSSvyatoslav Ryhel					regulator-coupled-with = <&vdd_cpu>;
1198*b68e6e0dSSvyatoslav Ryhel					regulator-coupled-max-spread = <300000>;
1199*b68e6e0dSSvyatoslav Ryhel					regulator-max-step-microvolt = <100000>;
1200*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1201*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1202*b68e6e0dSSvyatoslav Ryhel
1203*b68e6e0dSSvyatoslav Ryhel					nvidia,tegra-core-regulator;
1204*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1205*b68e6e0dSSvyatoslav Ryhel				};
1206*b68e6e0dSSvyatoslav Ryhel
1207*b68e6e0dSSvyatoslav Ryhel				vdd_1v8_vio: sd2 {
1208*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_1v8_gen";
1209*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1800000>;
1210*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1800000>;
1211*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1212*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1213*b68e6e0dSSvyatoslav Ryhel
1214*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1215*b68e6e0dSSvyatoslav Ryhel				};
1216*b68e6e0dSSvyatoslav Ryhel
1217*b68e6e0dSSvyatoslav Ryhel				sd3 {
1218*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vddio_ddr";
1219*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1220*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1221*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1222*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1223*b68e6e0dSSvyatoslav Ryhel
1224*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1225*b68e6e0dSSvyatoslav Ryhel				};
1226*b68e6e0dSSvyatoslav Ryhel
1227*b68e6e0dSSvyatoslav Ryhel				ldo0 {
1228*b68e6e0dSSvyatoslav Ryhel					regulator-name = "avdd_pll";
1229*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1230*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1231*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1232*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1233*b68e6e0dSSvyatoslav Ryhel
1234*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1235*b68e6e0dSSvyatoslav Ryhel				};
1236*b68e6e0dSSvyatoslav Ryhel
1237*b68e6e0dSSvyatoslav Ryhel				ldo1 {
1238*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_ddr_hs";
1239*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1000000>;
1240*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1000000>;
1241*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1242*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1243*b68e6e0dSSvyatoslav Ryhel
1244*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1245*b68e6e0dSSvyatoslav Ryhel				};
1246*b68e6e0dSSvyatoslav Ryhel
1247*b68e6e0dSSvyatoslav Ryhel				avdd_3v3_periph: ldo2 {
1248*b68e6e0dSSvyatoslav Ryhel					regulator-name = "avdd_usb";
1249*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <3300000>;
1250*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <3300000>;
1251*b68e6e0dSSvyatoslav Ryhel
1252*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1253*b68e6e0dSSvyatoslav Ryhel				};
1254*b68e6e0dSSvyatoslav Ryhel
1255*b68e6e0dSSvyatoslav Ryhel				vdd_usd: ldo3 {
1256*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_sdmmc3";
1257*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <3000000>;
1258*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <3000000>;
1259*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1260*b68e6e0dSSvyatoslav Ryhel
1261*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1262*b68e6e0dSSvyatoslav Ryhel				};
1263*b68e6e0dSSvyatoslav Ryhel
1264*b68e6e0dSSvyatoslav Ryhel				ldo4 {
1265*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_rtc";
1266*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1267*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1268*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1269*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1270*b68e6e0dSSvyatoslav Ryhel
1271*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1272*b68e6e0dSSvyatoslav Ryhel				};
1273*b68e6e0dSSvyatoslav Ryhel
1274*b68e6e0dSSvyatoslav Ryhel				vcore_emmc: ldo5 {
1275*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_ddr_rx";
1276*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <2850000>;
1277*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <2850000>;
1278*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1279*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1280*b68e6e0dSSvyatoslav Ryhel
1281*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1282*b68e6e0dSSvyatoslav Ryhel				};
1283*b68e6e0dSSvyatoslav Ryhel
1284*b68e6e0dSSvyatoslav Ryhel				avdd_1v8_hdmi_pll: ldo6 {
1285*b68e6e0dSSvyatoslav Ryhel					regulator-name = "avdd_osc";
1286*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1800000>;
1287*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1800000>;
1288*b68e6e0dSSvyatoslav Ryhel					regulator-always-on;
1289*b68e6e0dSSvyatoslav Ryhel					regulator-boot-on;
1290*b68e6e0dSSvyatoslav Ryhel
1291*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1292*b68e6e0dSSvyatoslav Ryhel				};
1293*b68e6e0dSSvyatoslav Ryhel
1294*b68e6e0dSSvyatoslav Ryhel				vdd_1v2_mhl: ldo7 {
1295*b68e6e0dSSvyatoslav Ryhel					regulator-name = "vdd_1v2_mhl";
1296*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1050000>;
1297*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1250000>;
1298*b68e6e0dSSvyatoslav Ryhel
1299*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1300*b68e6e0dSSvyatoslav Ryhel				};
1301*b68e6e0dSSvyatoslav Ryhel
1302*b68e6e0dSSvyatoslav Ryhel				ldo8 {
1303*b68e6e0dSSvyatoslav Ryhel					regulator-name = "avdd_dsi_csi";
1304*b68e6e0dSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1305*b68e6e0dSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1306*b68e6e0dSSvyatoslav Ryhel
1307*b68e6e0dSSvyatoslav Ryhel					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1308*b68e6e0dSSvyatoslav Ryhel				};
1309*b68e6e0dSSvyatoslav Ryhel			};
1310*b68e6e0dSSvyatoslav Ryhel		};
1311*b68e6e0dSSvyatoslav Ryhel
1312*b68e6e0dSSvyatoslav Ryhel		fuel-gauge@36 {
1313*b68e6e0dSSvyatoslav Ryhel			compatible = "maxim,max17043";
1314*b68e6e0dSSvyatoslav Ryhel			reg = <0x36>;
1315*b68e6e0dSSvyatoslav Ryhel
1316*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1317*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;
1318*b68e6e0dSSvyatoslav Ryhel
1319*b68e6e0dSSvyatoslav Ryhel			monitored-battery = <&battery>;
1320*b68e6e0dSSvyatoslav Ryhel
1321*b68e6e0dSSvyatoslav Ryhel			maxim,alert-low-soc-level = <10>;
1322*b68e6e0dSSvyatoslav Ryhel			wakeup-source;
1323*b68e6e0dSSvyatoslav Ryhel		};
1324*b68e6e0dSSvyatoslav Ryhel
1325*b68e6e0dSSvyatoslav Ryhel		power-sensor@40 {
1326*b68e6e0dSSvyatoslav Ryhel			compatible = "ti,ina230";
1327*b68e6e0dSSvyatoslav Ryhel			reg = <0x40>;
1328*b68e6e0dSSvyatoslav Ryhel
1329*b68e6e0dSSvyatoslav Ryhel			vs-supply = <&vdd_3v0_sen>;
1330*b68e6e0dSSvyatoslav Ryhel		};
1331*b68e6e0dSSvyatoslav Ryhel
1332*b68e6e0dSSvyatoslav Ryhel		nct72: temperature-sensor@4c {
1333*b68e6e0dSSvyatoslav Ryhel			compatible = "onnn,nct1008";
1334*b68e6e0dSSvyatoslav Ryhel			reg = <0x4c>;
1335*b68e6e0dSSvyatoslav Ryhel
1336*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1337*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(I, 5) IRQ_TYPE_EDGE_FALLING>;
1338*b68e6e0dSSvyatoslav Ryhel
1339*b68e6e0dSSvyatoslav Ryhel			vcc-supply = <&vdd_3v0_sen>;
1340*b68e6e0dSSvyatoslav Ryhel			#thermal-sensor-cells = <1>;
1341*b68e6e0dSSvyatoslav Ryhel		};
1342*b68e6e0dSSvyatoslav Ryhel	};
1343*b68e6e0dSSvyatoslav Ryhel
1344*b68e6e0dSSvyatoslav Ryhel	i2c-mhl {
1345*b68e6e0dSSvyatoslav Ryhel		compatible = "i2c-gpio";
1346*b68e6e0dSSvyatoslav Ryhel
1347*b68e6e0dSSvyatoslav Ryhel		sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
1348*b68e6e0dSSvyatoslav Ryhel		scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
1349*b68e6e0dSSvyatoslav Ryhel
1350*b68e6e0dSSvyatoslav Ryhel		i2c-gpio,delay-us = <5>;
1351*b68e6e0dSSvyatoslav Ryhel
1352*b68e6e0dSSvyatoslav Ryhel		#address-cells = <1>;
1353*b68e6e0dSSvyatoslav Ryhel		#size-cells = <0>;
1354*b68e6e0dSSvyatoslav Ryhel	};
1355*b68e6e0dSSvyatoslav Ryhel
1356*b68e6e0dSSvyatoslav Ryhel	spi@7000dc00 {
1357*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1358*b68e6e0dSSvyatoslav Ryhel		spi-max-frequency = <25000000>;
1359*b68e6e0dSSvyatoslav Ryhel
1360*b68e6e0dSSvyatoslav Ryhel		/* DSI bridge */
1361*b68e6e0dSSvyatoslav Ryhel	};
1362*b68e6e0dSSvyatoslav Ryhel
1363*b68e6e0dSSvyatoslav Ryhel	pmc@7000e400 {
1364*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1365*b68e6e0dSSvyatoslav Ryhel		nvidia,invert-interrupt;
1366*b68e6e0dSSvyatoslav Ryhel		nvidia,suspend-mode = <2>;
1367*b68e6e0dSSvyatoslav Ryhel		nvidia,cpu-pwr-good-time = <2000>;
1368*b68e6e0dSSvyatoslav Ryhel		nvidia,cpu-pwr-off-time = <200>;
1369*b68e6e0dSSvyatoslav Ryhel		nvidia,core-pwr-good-time = <3845 3845>;
1370*b68e6e0dSSvyatoslav Ryhel		nvidia,core-pwr-off-time = <0>;
1371*b68e6e0dSSvyatoslav Ryhel		nvidia,core-power-req-active-high;
1372*b68e6e0dSSvyatoslav Ryhel		nvidia,sys-clock-req-active-high;
1373*b68e6e0dSSvyatoslav Ryhel		core-supply = <&vdd_core>;
1374*b68e6e0dSSvyatoslav Ryhel
1375*b68e6e0dSSvyatoslav Ryhel		i2c-thermtrip {
1376*b68e6e0dSSvyatoslav Ryhel			nvidia,i2c-controller-id = <4>;
1377*b68e6e0dSSvyatoslav Ryhel			nvidia,bus-addr = <0x1c>;
1378*b68e6e0dSSvyatoslav Ryhel			nvidia,reg-addr = <0x41>;
1379*b68e6e0dSSvyatoslav Ryhel			nvidia,reg-data = <0x02>;
1380*b68e6e0dSSvyatoslav Ryhel		};
1381*b68e6e0dSSvyatoslav Ryhel	};
1382*b68e6e0dSSvyatoslav Ryhel
1383*b68e6e0dSSvyatoslav Ryhel	hda@70030000 {
1384*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1385*b68e6e0dSSvyatoslav Ryhel	};
1386*b68e6e0dSSvyatoslav Ryhel
1387*b68e6e0dSSvyatoslav Ryhel	ahub@70080000 {
1388*b68e6e0dSSvyatoslav Ryhel		/* HIFI CODEC */
1389*b68e6e0dSSvyatoslav Ryhel		i2s@70080300 {		/* i2s0 */
1390*b68e6e0dSSvyatoslav Ryhel			status = "okay";
1391*b68e6e0dSSvyatoslav Ryhel		};
1392*b68e6e0dSSvyatoslav Ryhel
1393*b68e6e0dSSvyatoslav Ryhel		/* BASEBAND */
1394*b68e6e0dSSvyatoslav Ryhel		i2s@70080500 {		/* i2s2 */
1395*b68e6e0dSSvyatoslav Ryhel			status = "okay";
1396*b68e6e0dSSvyatoslav Ryhel		};
1397*b68e6e0dSSvyatoslav Ryhel
1398*b68e6e0dSSvyatoslav Ryhel		/* BT SCO */
1399*b68e6e0dSSvyatoslav Ryhel		i2s@70080600 {		/* i2s3 */
1400*b68e6e0dSSvyatoslav Ryhel			status = "okay";
1401*b68e6e0dSSvyatoslav Ryhel		};
1402*b68e6e0dSSvyatoslav Ryhel	};
1403*b68e6e0dSSvyatoslav Ryhel
1404*b68e6e0dSSvyatoslav Ryhel	sdmmc1: mmc@78000000 {
1405*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1406*b68e6e0dSSvyatoslav Ryhel
1407*b68e6e0dSSvyatoslav Ryhel		#address-cells = <1>;
1408*b68e6e0dSSvyatoslav Ryhel		#size-cells = <0>;
1409*b68e6e0dSSvyatoslav Ryhel
1410*b68e6e0dSSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
1411*b68e6e0dSSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1412*b68e6e0dSSvyatoslav Ryhel		assigned-clock-rates = <50000000>;
1413*b68e6e0dSSvyatoslav Ryhel
1414*b68e6e0dSSvyatoslav Ryhel		max-frequency = <50000000>;
1415*b68e6e0dSSvyatoslav Ryhel		keep-power-in-suspend;
1416*b68e6e0dSSvyatoslav Ryhel		bus-width = <4>;
1417*b68e6e0dSSvyatoslav Ryhel		non-removable;
1418*b68e6e0dSSvyatoslav Ryhel
1419*b68e6e0dSSvyatoslav Ryhel		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1420*b68e6e0dSSvyatoslav Ryhel		vmmc-supply = <&vdd_3v3_vbat>;
1421*b68e6e0dSSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
1422*b68e6e0dSSvyatoslav Ryhel
1423*b68e6e0dSSvyatoslav Ryhel		/* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */
1424*b68e6e0dSSvyatoslav Ryhel		wifi@1 {
1425*b68e6e0dSSvyatoslav Ryhel			compatible = "brcm,bcm4329-fmac";
1426*b68e6e0dSSvyatoslav Ryhel			reg = <1>;
1427*b68e6e0dSSvyatoslav Ryhel
1428*b68e6e0dSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1429*b68e6e0dSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
1430*b68e6e0dSSvyatoslav Ryhel			interrupt-names = "host-wake";
1431*b68e6e0dSSvyatoslav Ryhel		};
1432*b68e6e0dSSvyatoslav Ryhel	};
1433*b68e6e0dSSvyatoslav Ryhel
1434*b68e6e0dSSvyatoslav Ryhel	sdmmc4: mmc@78000600 {
1435*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1436*b68e6e0dSSvyatoslav Ryhel		bus-width = <8>;
1437*b68e6e0dSSvyatoslav Ryhel
1438*b68e6e0dSSvyatoslav Ryhel		non-removable;
1439*b68e6e0dSSvyatoslav Ryhel		mmc-ddr-1_8v;
1440*b68e6e0dSSvyatoslav Ryhel
1441*b68e6e0dSSvyatoslav Ryhel		vmmc-supply = <&vcore_emmc>;
1442*b68e6e0dSSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
1443*b68e6e0dSSvyatoslav Ryhel	};
1444*b68e6e0dSSvyatoslav Ryhel
1445*b68e6e0dSSvyatoslav Ryhel	/* Micro USB */
1446*b68e6e0dSSvyatoslav Ryhel	usb@7d000000 {
1447*b68e6e0dSSvyatoslav Ryhel		compatible = "nvidia,tegra30-udc";
1448*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1449*b68e6e0dSSvyatoslav Ryhel		dr_mode = "peripheral";
1450*b68e6e0dSSvyatoslav Ryhel	};
1451*b68e6e0dSSvyatoslav Ryhel
1452*b68e6e0dSSvyatoslav Ryhel	usb-phy@7d000000 {
1453*b68e6e0dSSvyatoslav Ryhel		status = "okay";
1454*b68e6e0dSSvyatoslav Ryhel		dr_mode = "peripheral";
1455*b68e6e0dSSvyatoslav Ryhel		nvidia,hssync-start-delay = <0>;
1456*b68e6e0dSSvyatoslav Ryhel		nvidia,xcvr-lsfslew = <2>;
1457*b68e6e0dSSvyatoslav Ryhel		nvidia,xcvr-lsrslew = <2>;
1458*b68e6e0dSSvyatoslav Ryhel		vbus-supply = <&avdd_3v3_periph>;
1459*b68e6e0dSSvyatoslav Ryhel	};
1460*b68e6e0dSSvyatoslav Ryhel
1461*b68e6e0dSSvyatoslav Ryhel	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1462*b68e6e0dSSvyatoslav Ryhel	clk32k_in: clock-32k {
1463*b68e6e0dSSvyatoslav Ryhel		compatible = "fixed-clock";
1464*b68e6e0dSSvyatoslav Ryhel		#clock-cells = <0>;
1465*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <32768>;
1466*b68e6e0dSSvyatoslav Ryhel		clock-output-names = "pmic-oscillator";
1467*b68e6e0dSSvyatoslav Ryhel	};
1468*b68e6e0dSSvyatoslav Ryhel
1469*b68e6e0dSSvyatoslav Ryhel	gps_refclk: clock-gps {
1470*b68e6e0dSSvyatoslav Ryhel		compatible = "fixed-clock";
1471*b68e6e0dSSvyatoslav Ryhel		clock-frequency = <26000000>;
1472*b68e6e0dSSvyatoslav Ryhel		clock-accuracy = <100>;
1473*b68e6e0dSSvyatoslav Ryhel		#clock-cells = <0>;
1474*b68e6e0dSSvyatoslav Ryhel	};
1475*b68e6e0dSSvyatoslav Ryhel
1476*b68e6e0dSSvyatoslav Ryhel	gps_osc: clock-gps-osc-gate {
1477*b68e6e0dSSvyatoslav Ryhel		compatible = "gpio-gate-clock";
1478*b68e6e0dSSvyatoslav Ryhel		enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
1479*b68e6e0dSSvyatoslav Ryhel		clocks = <&gps_refclk>;
1480*b68e6e0dSSvyatoslav Ryhel		#clock-cells = <0>;
1481*b68e6e0dSSvyatoslav Ryhel	};
1482*b68e6e0dSSvyatoslav Ryhel
1483*b68e6e0dSSvyatoslav Ryhel	cpus {
1484*b68e6e0dSSvyatoslav Ryhel		cpu0: cpu@0 {
1485*b68e6e0dSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1486*b68e6e0dSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1487*b68e6e0dSSvyatoslav Ryhel			#cooling-cells = <2>;
1488*b68e6e0dSSvyatoslav Ryhel		};
1489*b68e6e0dSSvyatoslav Ryhel		cpu1: cpu@1 {
1490*b68e6e0dSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1491*b68e6e0dSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1492*b68e6e0dSSvyatoslav Ryhel			#cooling-cells = <2>;
1493*b68e6e0dSSvyatoslav Ryhel		};
1494*b68e6e0dSSvyatoslav Ryhel		cpu2: cpu@2 {
1495*b68e6e0dSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1496*b68e6e0dSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1497*b68e6e0dSSvyatoslav Ryhel			#cooling-cells = <2>;
1498*b68e6e0dSSvyatoslav Ryhel		};
1499*b68e6e0dSSvyatoslav Ryhel		cpu3: cpu@3 {
1500*b68e6e0dSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1501*b68e6e0dSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1502*b68e6e0dSSvyatoslav Ryhel			#cooling-cells = <2>;
1503*b68e6e0dSSvyatoslav Ryhel		};
1504*b68e6e0dSSvyatoslav Ryhel	};
1505*b68e6e0dSSvyatoslav Ryhel
1506*b68e6e0dSSvyatoslav Ryhel	gpio-keys {
1507*b68e6e0dSSvyatoslav Ryhel		compatible = "gpio-keys";
1508*b68e6e0dSSvyatoslav Ryhel
1509*b68e6e0dSSvyatoslav Ryhel		key-power {
1510*b68e6e0dSSvyatoslav Ryhel			label = "Power";
1511*b68e6e0dSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
1512*b68e6e0dSSvyatoslav Ryhel			linux,code = <KEY_POWER>;
1513*b68e6e0dSSvyatoslav Ryhel			debounce-interval = <10>;
1514*b68e6e0dSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1515*b68e6e0dSSvyatoslav Ryhel			wakeup-source;
1516*b68e6e0dSSvyatoslav Ryhel		};
1517*b68e6e0dSSvyatoslav Ryhel
1518*b68e6e0dSSvyatoslav Ryhel		key-volume-down {
1519*b68e6e0dSSvyatoslav Ryhel			label = "Volume Down";
1520*b68e6e0dSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>;
1521*b68e6e0dSSvyatoslav Ryhel			linux,code = <KEY_VOLUMEDOWN>;
1522*b68e6e0dSSvyatoslav Ryhel			debounce-interval = <10>;
1523*b68e6e0dSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1524*b68e6e0dSSvyatoslav Ryhel			wakeup-source;
1525*b68e6e0dSSvyatoslav Ryhel		};
1526*b68e6e0dSSvyatoslav Ryhel	};
1527*b68e6e0dSSvyatoslav Ryhel
1528*b68e6e0dSSvyatoslav Ryhel	gpio-leds {
1529*b68e6e0dSSvyatoslav Ryhel		compatible = "gpio-leds";
1530*b68e6e0dSSvyatoslav Ryhel
1531*b68e6e0dSSvyatoslav Ryhel		led-keypad {
1532*b68e6e0dSSvyatoslav Ryhel			label = "keypad::white";
1533*b68e6e0dSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
1534*b68e6e0dSSvyatoslav Ryhel
1535*b68e6e0dSSvyatoslav Ryhel			color = <LED_COLOR_ID_WHITE>;
1536*b68e6e0dSSvyatoslav Ryhel			function = LED_FUNCTION_KBD_BACKLIGHT;
1537*b68e6e0dSSvyatoslav Ryhel		};
1538*b68e6e0dSSvyatoslav Ryhel	};
1539*b68e6e0dSSvyatoslav Ryhel
1540*b68e6e0dSSvyatoslav Ryhel	opp-table-actmon {
1541*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-625000000;
1542*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-667000000;
1543*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-750000000;
1544*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-800000000;
1545*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-900000000;
1546*b68e6e0dSSvyatoslav Ryhel	};
1547*b68e6e0dSSvyatoslav Ryhel
1548*b68e6e0dSSvyatoslav Ryhel	opp-table-emc {
1549*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-625000000-1200;
1550*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-625000000-1250;
1551*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-667000000-1200;
1552*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-750000000-1300;
1553*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-800000000-1300;
1554*b68e6e0dSSvyatoslav Ryhel		/delete-node/ opp-900000000-1350;
1555*b68e6e0dSSvyatoslav Ryhel	};
1556*b68e6e0dSSvyatoslav Ryhel
1557*b68e6e0dSSvyatoslav Ryhel	brcm_wifi_pwrseq: pwrseq-wifi {
1558*b68e6e0dSSvyatoslav Ryhel		compatible = "mmc-pwrseq-simple";
1559*b68e6e0dSSvyatoslav Ryhel
1560*b68e6e0dSSvyatoslav Ryhel		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1561*b68e6e0dSSvyatoslav Ryhel		clock-names = "ext_clock";
1562*b68e6e0dSSvyatoslav Ryhel
1563*b68e6e0dSSvyatoslav Ryhel		reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
1564*b68e6e0dSSvyatoslav Ryhel		post-power-on-delay-ms = <300>;
1565*b68e6e0dSSvyatoslav Ryhel		power-off-delay-us = <300>;
1566*b68e6e0dSSvyatoslav Ryhel	};
1567*b68e6e0dSSvyatoslav Ryhel
1568*b68e6e0dSSvyatoslav Ryhel	vdd_5v0_vbus: regulator-vbus {
1569*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1570*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_vbus";
1571*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1572*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1573*b68e6e0dSSvyatoslav Ryhel		regulator-always-on;
1574*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1575*b68e6e0dSSvyatoslav Ryhel	};
1576*b68e6e0dSSvyatoslav Ryhel
1577*b68e6e0dSSvyatoslav Ryhel	vdd_3v3_vbat: regulator-vbat {
1578*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1579*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_vbat";
1580*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
1581*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
1582*b68e6e0dSSvyatoslav Ryhel		regulator-always-on;
1583*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1584*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_vbus>;
1585*b68e6e0dSSvyatoslav Ryhel	};
1586*b68e6e0dSSvyatoslav Ryhel
1587*b68e6e0dSSvyatoslav Ryhel	vdd_3v0_sen: regulator-sen3v {
1588*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1589*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_3v0_sensor";
1590*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <3000000>;
1591*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <3000000>;
1592*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1593*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1594*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1595*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1596*b68e6e0dSSvyatoslav Ryhel	};
1597*b68e6e0dSSvyatoslav Ryhel
1598*b68e6e0dSSvyatoslav Ryhel	vdd_3v0_proxi: regulator-proxi {
1599*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1600*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_3v0_proxi";
1601*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <3000000>;
1602*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <3000000>;
1603*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1604*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
1605*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1606*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1607*b68e6e0dSSvyatoslav Ryhel	};
1608*b68e6e0dSSvyatoslav Ryhel
1609*b68e6e0dSSvyatoslav Ryhel	vdd_1v8_sen: regulator-sen1v8 {
1610*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1611*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_1v8_sensor";
1612*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1613*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1614*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1615*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
1616*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1617*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1618*b68e6e0dSSvyatoslav Ryhel	};
1619*b68e6e0dSSvyatoslav Ryhel
1620*b68e6e0dSSvyatoslav Ryhel	vcc_3v0_lcd: regulator-lcd3v {
1621*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1622*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vcc_3v0_lcd";
1623*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <3000000>;
1624*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <3000000>;
1625*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1626*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1627*b68e6e0dSSvyatoslav Ryhel	};
1628*b68e6e0dSSvyatoslav Ryhel
1629*b68e6e0dSSvyatoslav Ryhel	iovcc_1v8_lcd: regulator-lcd1v8 {
1630*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1631*b68e6e0dSSvyatoslav Ryhel		regulator-name = "iovcc_1v8_lcd";
1632*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1633*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1634*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1635*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
1636*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1637*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1638*b68e6e0dSSvyatoslav Ryhel	};
1639*b68e6e0dSSvyatoslav Ryhel
1640*b68e6e0dSSvyatoslav Ryhel	vio_1v8_mhl: regulator-mhl1v8 {
1641*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1642*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vio_1v8_mhl";
1643*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1644*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1645*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1646*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
1647*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1648*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1649*b68e6e0dSSvyatoslav Ryhel	};
1650*b68e6e0dSSvyatoslav Ryhel
1651*b68e6e0dSSvyatoslav Ryhel	vdd_3v0_touch: regulator-touchpwr {
1652*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1653*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_3v0_touch";
1654*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <3000000>;
1655*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <3000000>;
1656*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1657*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
1658*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1659*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1660*b68e6e0dSSvyatoslav Ryhel	};
1661*b68e6e0dSSvyatoslav Ryhel
1662*b68e6e0dSSvyatoslav Ryhel	vdd_1v8_touch: regulator-touchvio {
1663*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1664*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vdd_1v8_touch";
1665*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1666*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1667*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1668*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
1669*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1670*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1671*b68e6e0dSSvyatoslav Ryhel	};
1672*b68e6e0dSSvyatoslav Ryhel
1673*b68e6e0dSSvyatoslav Ryhel	vcc_1v8_gps: regulator-gps {
1674*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1675*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vcc_1v8_gps";
1676*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1677*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1678*b68e6e0dSSvyatoslav Ryhel		regulator-boot-on;
1679*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
1680*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1681*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1682*b68e6e0dSSvyatoslav Ryhel	};
1683*b68e6e0dSSvyatoslav Ryhel
1684*b68e6e0dSSvyatoslav Ryhel	vio_1v8_front: regulator-frontvio {
1685*b68e6e0dSSvyatoslav Ryhel		compatible = "regulator-fixed";
1686*b68e6e0dSSvyatoslav Ryhel		regulator-name = "vt_1v8_cam_vio";
1687*b68e6e0dSSvyatoslav Ryhel		regulator-min-microvolt = <1800000>;
1688*b68e6e0dSSvyatoslav Ryhel		regulator-max-microvolt = <1800000>;
1689*b68e6e0dSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
1690*b68e6e0dSSvyatoslav Ryhel		enable-active-high;
1691*b68e6e0dSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_vbat>;
1692*b68e6e0dSSvyatoslav Ryhel	};
1693*b68e6e0dSSvyatoslav Ryhel
1694*b68e6e0dSSvyatoslav Ryhel	sound {
1695*b68e6e0dSSvyatoslav Ryhel		nvidia,audio-routing =
1696*b68e6e0dSSvyatoslav Ryhel			"Headphone Jack", "HPL",
1697*b68e6e0dSSvyatoslav Ryhel			"Headphone Jack", "HPR",
1698*b68e6e0dSSvyatoslav Ryhel			"Int Spk", "SPKL",
1699*b68e6e0dSSvyatoslav Ryhel			"Int Spk", "SPKR",
1700*b68e6e0dSSvyatoslav Ryhel			"Earpiece", "RECL",
1701*b68e6e0dSSvyatoslav Ryhel			"Earpiece", "RECR",
1702*b68e6e0dSSvyatoslav Ryhel			"INA1", "Mic Jack",
1703*b68e6e0dSSvyatoslav Ryhel			"MIC1", "MICBIAS",
1704*b68e6e0dSSvyatoslav Ryhel			"MICBIAS", "Internal Mic 1",
1705*b68e6e0dSSvyatoslav Ryhel			"MIC2", "Internal Mic 2";
1706*b68e6e0dSSvyatoslav Ryhel
1707*b68e6e0dSSvyatoslav Ryhel		nvidia,i2s-controller = <&tegra_i2s0>;
1708*b68e6e0dSSvyatoslav Ryhel		nvidia,audio-codec = <&max98089>;
1709*b68e6e0dSSvyatoslav Ryhel
1710*b68e6e0dSSvyatoslav Ryhel		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>;
1711*b68e6e0dSSvyatoslav Ryhel		nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>;
1712*b68e6e0dSSvyatoslav Ryhel		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
1713*b68e6e0dSSvyatoslav Ryhel		nvidia,coupled-mic-hp-det;
1714*b68e6e0dSSvyatoslav Ryhel
1715*b68e6e0dSSvyatoslav Ryhel		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1716*b68e6e0dSSvyatoslav Ryhel			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1717*b68e6e0dSSvyatoslav Ryhel			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1718*b68e6e0dSSvyatoslav Ryhel		clock-names = "pll_a", "pll_a_out0", "mclk";
1719*b68e6e0dSSvyatoslav Ryhel
1720*b68e6e0dSSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1721*b68e6e0dSSvyatoslav Ryhel				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1722*b68e6e0dSSvyatoslav Ryhel
1723*b68e6e0dSSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1724*b68e6e0dSSvyatoslav Ryhel					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1725*b68e6e0dSSvyatoslav Ryhel	};
1726*b68e6e0dSSvyatoslav Ryhel
1727*b68e6e0dSSvyatoslav Ryhel	thermal-zones {
1728*b68e6e0dSSvyatoslav Ryhel		/*
1729*b68e6e0dSSvyatoslav Ryhel		 * NCT72 has two sensors:
1730*b68e6e0dSSvyatoslav Ryhel		 *
1731*b68e6e0dSSvyatoslav Ryhel		 *	0: internal that monitors ambient/skin temperature
1732*b68e6e0dSSvyatoslav Ryhel		 *	1: external that is connected to the CPU's diode
1733*b68e6e0dSSvyatoslav Ryhel		 *
1734*b68e6e0dSSvyatoslav Ryhel		 * Ideally we should use userspace thermal governor,
1735*b68e6e0dSSvyatoslav Ryhel		 * but it's a much more complex solution. The "skin"
1736*b68e6e0dSSvyatoslav Ryhel		 * zone exists as a simpler solution which prevents
1737*b68e6e0dSSvyatoslav Ryhel		 * this device from getting too hot from a user's
1738*b68e6e0dSSvyatoslav Ryhel		 * tactile perspective. The CPU zone is intended to
1739*b68e6e0dSSvyatoslav Ryhel		 * protect silicon from damage.
1740*b68e6e0dSSvyatoslav Ryhel		 */
1741*b68e6e0dSSvyatoslav Ryhel
1742*b68e6e0dSSvyatoslav Ryhel		skin-thermal {
1743*b68e6e0dSSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
1744*b68e6e0dSSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
1745*b68e6e0dSSvyatoslav Ryhel
1746*b68e6e0dSSvyatoslav Ryhel			thermal-sensors = <&nct72 0>;
1747*b68e6e0dSSvyatoslav Ryhel
1748*b68e6e0dSSvyatoslav Ryhel			trips {
1749*b68e6e0dSSvyatoslav Ryhel				trip0: skin-alert {
1750*b68e6e0dSSvyatoslav Ryhel					/* throttle at 50C until temperature drops to 49.8C */
1751*b68e6e0dSSvyatoslav Ryhel					temperature = <50000>;
1752*b68e6e0dSSvyatoslav Ryhel					hysteresis = <200>;
1753*b68e6e0dSSvyatoslav Ryhel					type = "passive";
1754*b68e6e0dSSvyatoslav Ryhel				};
1755*b68e6e0dSSvyatoslav Ryhel
1756*b68e6e0dSSvyatoslav Ryhel				trip1: skin-crit {
1757*b68e6e0dSSvyatoslav Ryhel					/* shut down at 60C */
1758*b68e6e0dSSvyatoslav Ryhel					temperature = <60000>;
1759*b68e6e0dSSvyatoslav Ryhel					hysteresis = <2000>;
1760*b68e6e0dSSvyatoslav Ryhel					type = "critical";
1761*b68e6e0dSSvyatoslav Ryhel				};
1762*b68e6e0dSSvyatoslav Ryhel			};
1763*b68e6e0dSSvyatoslav Ryhel
1764*b68e6e0dSSvyatoslav Ryhel			cooling-maps {
1765*b68e6e0dSSvyatoslav Ryhel				map0 {
1766*b68e6e0dSSvyatoslav Ryhel					trip = <&trip0>;
1767*b68e6e0dSSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1768*b68e6e0dSSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1769*b68e6e0dSSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770*b68e6e0dSSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771*b68e6e0dSSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
1772*b68e6e0dSSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
1773*b68e6e0dSSvyatoslav Ryhel				};
1774*b68e6e0dSSvyatoslav Ryhel			};
1775*b68e6e0dSSvyatoslav Ryhel		};
1776*b68e6e0dSSvyatoslav Ryhel
1777*b68e6e0dSSvyatoslav Ryhel		cpu-thermal {
1778*b68e6e0dSSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
1779*b68e6e0dSSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
1780*b68e6e0dSSvyatoslav Ryhel
1781*b68e6e0dSSvyatoslav Ryhel			thermal-sensors = <&nct72 1>;
1782*b68e6e0dSSvyatoslav Ryhel
1783*b68e6e0dSSvyatoslav Ryhel			trips {
1784*b68e6e0dSSvyatoslav Ryhel				trip2: cpu-alert {
1785*b68e6e0dSSvyatoslav Ryhel					/* throttle at 75C until temperature drops to 74.8C */
1786*b68e6e0dSSvyatoslav Ryhel					temperature = <75000>;
1787*b68e6e0dSSvyatoslav Ryhel					hysteresis = <200>;
1788*b68e6e0dSSvyatoslav Ryhel					type = "passive";
1789*b68e6e0dSSvyatoslav Ryhel				};
1790*b68e6e0dSSvyatoslav Ryhel
1791*b68e6e0dSSvyatoslav Ryhel				trip3: cpu-crit {
1792*b68e6e0dSSvyatoslav Ryhel					/* shut down at 90C */
1793*b68e6e0dSSvyatoslav Ryhel					temperature = <90000>;
1794*b68e6e0dSSvyatoslav Ryhel					hysteresis = <2000>;
1795*b68e6e0dSSvyatoslav Ryhel					type = "critical";
1796*b68e6e0dSSvyatoslav Ryhel				};
1797*b68e6e0dSSvyatoslav Ryhel			};
1798*b68e6e0dSSvyatoslav Ryhel
1799*b68e6e0dSSvyatoslav Ryhel			cooling-maps {
1800*b68e6e0dSSvyatoslav Ryhel				map1 {
1801*b68e6e0dSSvyatoslav Ryhel					trip = <&trip2>;
1802*b68e6e0dSSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1803*b68e6e0dSSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1804*b68e6e0dSSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1805*b68e6e0dSSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1806*b68e6e0dSSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
1807*b68e6e0dSSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
1808*b68e6e0dSSvyatoslav Ryhel				};
1809*b68e6e0dSSvyatoslav Ryhel			};
1810*b68e6e0dSSvyatoslav Ryhel		};
1811*b68e6e0dSSvyatoslav Ryhel	};
1812*b68e6e0dSSvyatoslav Ryhel};
1813