1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/input/input.h> 3#include <dt-bindings/thermal/thermal.h> 4#include "tegra30.dtsi" 5#include "tegra30-cpu-opp.dtsi" 6#include "tegra30-cpu-opp-microvolt.dtsi" 7 8/** 9 * This file contains common DT entry for all fab version of Cardhu. 10 * There is multiple fab version of Cardhu starting from A01 to A07. 11 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version 12 * A02 will have different sets of GPIOs for fixed regulator compare to 13 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are 14 * compatible with fab version A04. Based on Cardhu fab version, the 15 * related dts file need to be chosen like for Cardhu fab version A02, 16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use 17 * tegra30-cardhu-a04.dts. 18 * The identification of board is done in two ways, by looking the sticker 19 * on PCB and by reading board id eeprom. 20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th 21 * number is the fab version like here it is 002 and hence fab version A02. 22 * The (downstream internal) U-Boot of Cardhu display the board-id as 23 * follows: 24 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 25 * In this Fab version is 02 i.e. A02. 26 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). 27 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte 28 * wide. 29 */ 30 31/ { 32 model = "NVIDIA Tegra30 Cardhu evaluation board"; 33 compatible = "nvidia,cardhu", "nvidia,tegra30"; 34 35 aliases { 36 rtc0 = "/i2c@7000d000/tps65911@2d"; 37 rtc1 = "/rtc@7000e000"; 38 serial0 = &uarta; 39 serial1 = &uartc; 40 }; 41 42 chosen { 43 stdout-path = "serial0:115200n8"; 44 }; 45 46 memory@80000000 { 47 reg = <0x80000000 0x40000000>; 48 }; 49 50 pcie@3000 { 51 status = "okay"; 52 53 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ 54 avdd-pexb-supply = <&ldo1_reg>; 55 vdd-pexb-supply = <&ldo1_reg>; 56 avdd-pex-pll-supply = <&ldo1_reg>; 57 hvdd-pex-supply = <&pex_hvdd_3v3_reg>; 58 vddio-pex-ctl-supply = <&sys_3v3_reg>; 59 avdd-plle-supply = <&ldo2_reg>; 60 61 pci@1,0 { 62 nvidia,num-lanes = <4>; 63 }; 64 65 pci@2,0 { 66 nvidia,num-lanes = <1>; 67 }; 68 69 pci@3,0 { 70 status = "okay"; 71 nvidia,num-lanes = <1>; 72 }; 73 }; 74 75 host1x@50000000 { 76 dc@54200000 { 77 rgb { 78 status = "okay"; 79 80 nvidia,panel = <&panel>; 81 }; 82 }; 83 }; 84 85 pinmux@70000868 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&state_default>; 88 89 state_default: pinmux { 90 sdmmc1_clk_pz0 { 91 nvidia,pins = "sdmmc1_clk_pz0"; 92 nvidia,function = "sdmmc1"; 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 94 nvidia,tristate = <TEGRA_PIN_DISABLE>; 95 }; 96 sdmmc1_cmd_pz1 { 97 nvidia,pins = "sdmmc1_cmd_pz1", 98 "sdmmc1_dat0_py7", 99 "sdmmc1_dat1_py6", 100 "sdmmc1_dat2_py5", 101 "sdmmc1_dat3_py4"; 102 nvidia,function = "sdmmc1"; 103 nvidia,pull = <TEGRA_PIN_PULL_UP>; 104 nvidia,tristate = <TEGRA_PIN_DISABLE>; 105 }; 106 sdmmc3_clk_pa6 { 107 nvidia,pins = "sdmmc3_clk_pa6"; 108 nvidia,function = "sdmmc3"; 109 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 110 nvidia,tristate = <TEGRA_PIN_DISABLE>; 111 }; 112 sdmmc3_cmd_pa7 { 113 nvidia,pins = "sdmmc3_cmd_pa7", 114 "sdmmc3_dat0_pb7", 115 "sdmmc3_dat1_pb6", 116 "sdmmc3_dat2_pb5", 117 "sdmmc3_dat3_pb4"; 118 nvidia,function = "sdmmc3"; 119 nvidia,pull = <TEGRA_PIN_PULL_UP>; 120 nvidia,tristate = <TEGRA_PIN_DISABLE>; 121 }; 122 sdmmc4_clk_pcc4 { 123 nvidia,pins = "sdmmc4_clk_pcc4", 124 "sdmmc4_rst_n_pcc3"; 125 nvidia,function = "sdmmc4"; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 nvidia,tristate = <TEGRA_PIN_DISABLE>; 128 }; 129 sdmmc4_dat0_paa0 { 130 nvidia,pins = "sdmmc4_dat0_paa0", 131 "sdmmc4_dat1_paa1", 132 "sdmmc4_dat2_paa2", 133 "sdmmc4_dat3_paa3", 134 "sdmmc4_dat4_paa4", 135 "sdmmc4_dat5_paa5", 136 "sdmmc4_dat6_paa6", 137 "sdmmc4_dat7_paa7"; 138 nvidia,function = "sdmmc4"; 139 nvidia,pull = <TEGRA_PIN_PULL_UP>; 140 nvidia,tristate = <TEGRA_PIN_DISABLE>; 141 }; 142 dap2_fs_pa2 { 143 nvidia,pins = "dap2_fs_pa2", 144 "dap2_sclk_pa3", 145 "dap2_din_pa4", 146 "dap2_dout_pa5"; 147 nvidia,function = "i2s1"; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>; 150 }; 151 sdio3 { 152 nvidia,pins = "drive_sdio3"; 153 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 154 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 155 nvidia,pull-down-strength = <46>; 156 nvidia,pull-up-strength = <42>; 157 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 158 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 159 }; 160 uart3_txd_pw6 { 161 nvidia,pins = "uart3_txd_pw6", 162 "uart3_cts_n_pa1", 163 "uart3_rts_n_pc0", 164 "uart3_rxd_pw7"; 165 nvidia,function = "uartc"; 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167 nvidia,tristate = <TEGRA_PIN_DISABLE>; 168 }; 169 }; 170 }; 171 172 serial@70006000 { 173 /delete-property/ dmas; 174 /delete-property/ dma-names; 175 status = "okay"; 176 }; 177 178 serial@70006200 { 179 compatible = "nvidia,tegra30-hsuart"; 180 /delete-property/ reg-shift; 181 status = "okay"; 182 }; 183 184 pwm@7000a000 { 185 status = "okay"; 186 }; 187 188 panelddc: i2c@7000c000 { 189 status = "okay"; 190 clock-frequency = <100000>; 191 }; 192 193 i2c@7000c400 { 194 status = "okay"; 195 clock-frequency = <100000>; 196 }; 197 198 i2c@7000c500 { 199 status = "okay"; 200 clock-frequency = <100000>; 201 202 /* ALS and Proximity sensor */ 203 isl29028@44 { 204 compatible = "isil,isl29028"; 205 reg = <0x44>; 206 interrupt-parent = <&gpio>; 207 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 208 }; 209 210 i2cmux@70 { 211 compatible = "nxp,pca9546"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 reg = <0x70>; 215 reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; 216 }; 217 }; 218 219 i2c@7000c700 { 220 status = "okay"; 221 clock-frequency = <100000>; 222 }; 223 224 i2c@7000d000 { 225 status = "okay"; 226 clock-frequency = <100000>; 227 228 wm8903: wm8903@1a { 229 compatible = "wlf,wm8903"; 230 reg = <0x1a>; 231 interrupt-parent = <&gpio>; 232 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>; 233 234 gpio-controller; 235 #gpio-cells = <2>; 236 237 micdet-cfg = <0>; 238 micdet-delay = <100>; 239 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 240 }; 241 242 pmic: tps65911@2d { 243 compatible = "ti,tps65911"; 244 reg = <0x2d>; 245 246 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 247 #interrupt-cells = <2>; 248 interrupt-controller; 249 wakeup-source; 250 251 ti,system-power-controller; 252 253 #gpio-cells = <2>; 254 gpio-controller; 255 256 vcc1-supply = <&vdd_ac_bat_reg>; 257 vcc2-supply = <&vdd_ac_bat_reg>; 258 vcc3-supply = <&vio_reg>; 259 vcc4-supply = <&vdd_5v0_reg>; 260 vcc5-supply = <&vdd_ac_bat_reg>; 261 vcc6-supply = <&vdd2_reg>; 262 vcc7-supply = <&vdd_ac_bat_reg>; 263 vccio-supply = <&vdd_ac_bat_reg>; 264 265 regulators { 266 vdd1_reg: vdd1 { 267 regulator-name = "vddio_ddr_1v2"; 268 regulator-min-microvolt = <1200000>; 269 regulator-max-microvolt = <1200000>; 270 regulator-always-on; 271 }; 272 273 vdd2_reg: vdd2 { 274 regulator-name = "vdd_1v5_gen"; 275 regulator-min-microvolt = <1500000>; 276 regulator-max-microvolt = <1500000>; 277 regulator-always-on; 278 }; 279 280 vddctrl_reg: vddctrl { 281 regulator-name = "vdd_cpu,vdd_sys"; 282 regulator-min-microvolt = <800000>; 283 regulator-max-microvolt = <1250000>; 284 regulator-coupled-with = <&vdd_core>; 285 regulator-coupled-max-spread = <300000>; 286 regulator-max-step-microvolt = <100000>; 287 regulator-always-on; 288 289 nvidia,tegra-cpu-regulator; 290 }; 291 292 vio_reg: vio { 293 regulator-name = "vdd_1v8_gen"; 294 regulator-min-microvolt = <1800000>; 295 regulator-max-microvolt = <1800000>; 296 regulator-always-on; 297 }; 298 299 ldo1_reg: ldo1 { 300 regulator-name = "vdd_pexa,vdd_pexb"; 301 regulator-min-microvolt = <1050000>; 302 regulator-max-microvolt = <1050000>; 303 }; 304 305 ldo2_reg: ldo2 { 306 regulator-name = "vdd_sata,avdd_plle"; 307 regulator-min-microvolt = <1050000>; 308 regulator-max-microvolt = <1050000>; 309 }; 310 311 /* LDO3 is not connected to anything */ 312 313 ldo4_reg: ldo4 { 314 regulator-name = "vdd_rtc"; 315 regulator-min-microvolt = <1200000>; 316 regulator-max-microvolt = <1200000>; 317 regulator-always-on; 318 }; 319 320 ldo5_reg: ldo5 { 321 regulator-name = "vddio_sdmmc,avdd_vdac"; 322 regulator-min-microvolt = <3300000>; 323 regulator-max-microvolt = <3300000>; 324 regulator-always-on; 325 }; 326 327 ldo6_reg: ldo6 { 328 regulator-name = "avdd_dsi_csi,pwrdet_mipi"; 329 regulator-min-microvolt = <1200000>; 330 regulator-max-microvolt = <1200000>; 331 }; 332 333 ldo7_reg: ldo7 { 334 regulator-name = "vdd_pllm,x,u,a_p_c_s"; 335 regulator-min-microvolt = <1200000>; 336 regulator-max-microvolt = <1200000>; 337 regulator-always-on; 338 }; 339 340 ldo8_reg: ldo8 { 341 regulator-name = "vdd_ddr_hs"; 342 regulator-min-microvolt = <1000000>; 343 regulator-max-microvolt = <1000000>; 344 regulator-always-on; 345 }; 346 }; 347 }; 348 349 nct1008: temperature-sensor@4c { 350 compatible = "onnn,nct1008"; 351 reg = <0x4c>; 352 vcc-supply = <&sys_3v3_reg>; 353 interrupt-parent = <&gpio>; 354 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; 355 #thermal-sensor-cells = <1>; 356 }; 357 358 vdd_core: tps62361@60 { 359 compatible = "ti,tps62361"; 360 reg = <0x60>; 361 362 regulator-name = "tps62361-vout"; 363 regulator-min-microvolt = <500000>; 364 regulator-max-microvolt = <1500000>; 365 regulator-coupled-with = <&vddctrl_reg>; 366 regulator-coupled-max-spread = <300000>; 367 regulator-max-step-microvolt = <100000>; 368 regulator-boot-on; 369 regulator-always-on; 370 ti,vsel0-state-high; 371 ti,vsel1-state-high; 372 373 nvidia,tegra-core-regulator; 374 }; 375 }; 376 377 spi@7000da00 { 378 status = "okay"; 379 spi-max-frequency = <25000000>; 380 381 flash@1 { 382 compatible = "winbond,w25q32", "jedec,spi-nor"; 383 reg = <1>; 384 spi-max-frequency = <20000000>; 385 }; 386 }; 387 388 pmc@7000e400 { 389 status = "okay"; 390 nvidia,invert-interrupt; 391 nvidia,suspend-mode = <1>; 392 nvidia,cpu-pwr-good-time = <2000>; 393 nvidia,cpu-pwr-off-time = <200>; 394 nvidia,core-pwr-good-time = <3845 3845>; 395 nvidia,core-pwr-off-time = <0>; 396 nvidia,core-power-req-active-high; 397 nvidia,sys-clock-req-active-high; 398 core-supply = <&vdd_core>; 399 }; 400 401 ahub@70080000 { 402 i2s@70080400 { 403 status = "okay"; 404 }; 405 }; 406 407 mmc@78000000 { 408 status = "okay"; 409 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 410 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 411 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; 412 bus-width = <4>; 413 }; 414 415 mmc@78000600 { 416 status = "okay"; 417 bus-width = <8>; 418 non-removable; 419 }; 420 421 usb@7d008000 { 422 status = "okay"; 423 }; 424 425 usb-phy@7d008000 { 426 vbus-supply = <&usb3_vbus_reg>; 427 status = "okay"; 428 }; 429 430 backlight: backlight { 431 compatible = "pwm-backlight"; 432 433 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 434 power-supply = <&vdd_bl_reg>; 435 pwms = <&pwm 0 5000000>; 436 437 brightness-levels = <0 4 8 16 32 64 128 255>; 438 default-brightness-level = <6>; 439 }; 440 441 clk32k_in: clock-32k { 442 compatible = "fixed-clock"; 443 clock-frequency = <32768>; 444 #clock-cells = <0>; 445 }; 446 447 cpus { 448 cpu0: cpu@0 { 449 cpu-supply = <&vddctrl_reg>; 450 operating-points-v2 = <&cpu0_opp_table>; 451 #cooling-cells = <2>; 452 }; 453 454 cpu1: cpu@1 { 455 cpu-supply = <&vddctrl_reg>; 456 operating-points-v2 = <&cpu0_opp_table>; 457 #cooling-cells = <2>; 458 }; 459 460 cpu2: cpu@2 { 461 cpu-supply = <&vddctrl_reg>; 462 operating-points-v2 = <&cpu0_opp_table>; 463 #cooling-cells = <2>; 464 }; 465 466 cpu3: cpu@3 { 467 cpu-supply = <&vddctrl_reg>; 468 operating-points-v2 = <&cpu0_opp_table>; 469 #cooling-cells = <2>; 470 }; 471 }; 472 473 gpio-keys { 474 compatible = "gpio-keys"; 475 476 key-power { 477 label = "Power"; 478 interrupt-parent = <&pmic>; 479 interrupts = <2 0>; 480 linux,code = <KEY_POWER>; 481 debounce-interval = <100>; 482 wakeup-source; 483 }; 484 485 key-volume-down { 486 label = "Volume Down"; 487 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; 488 linux,code = <KEY_VOLUMEDOWN>; 489 debounce-interval = <10>; 490 }; 491 492 key-volume-up { 493 label = "Volume Up"; 494 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 495 linux,code = <KEY_VOLUMEUP>; 496 debounce-interval = <10>; 497 }; 498 }; 499 500 panel: panel { 501 compatible = "chunghwa,claa101wb01"; 502 ddc-i2c-bus = <&panelddc>; 503 504 power-supply = <&vdd_pnl1_reg>; 505 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; 506 507 backlight = <&backlight>; 508 }; 509 510 vdd_ac_bat_reg: regulator-acbat { 511 compatible = "regulator-fixed"; 512 regulator-name = "vdd_ac_bat"; 513 regulator-min-microvolt = <5000000>; 514 regulator-max-microvolt = <5000000>; 515 regulator-always-on; 516 }; 517 518 cam_1v8_reg: regulator-cam { 519 compatible = "regulator-fixed"; 520 regulator-name = "cam_1v8"; 521 regulator-min-microvolt = <1800000>; 522 regulator-max-microvolt = <1800000>; 523 enable-active-high; 524 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; 525 vin-supply = <&vio_reg>; 526 }; 527 528 cp_5v_reg: regulator-5v0cp { 529 compatible = "regulator-fixed"; 530 regulator-name = "cp_5v"; 531 regulator-min-microvolt = <5000000>; 532 regulator-max-microvolt = <5000000>; 533 regulator-boot-on; 534 regulator-always-on; 535 enable-active-high; 536 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 537 }; 538 539 emmc_3v3_reg: regulator-emmc { 540 compatible = "regulator-fixed"; 541 regulator-name = "emmc_3v3"; 542 regulator-min-microvolt = <3300000>; 543 regulator-max-microvolt = <3300000>; 544 regulator-always-on; 545 regulator-boot-on; 546 enable-active-high; 547 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; 548 vin-supply = <&sys_3v3_reg>; 549 }; 550 551 modem_3v3_reg: regulator-modem { 552 compatible = "regulator-fixed"; 553 regulator-name = "modem_3v3"; 554 regulator-min-microvolt = <3300000>; 555 regulator-max-microvolt = <3300000>; 556 enable-active-high; 557 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; 558 }; 559 560 pex_hvdd_3v3_reg: regulator-pex { 561 compatible = "regulator-fixed"; 562 regulator-name = "pex_hvdd_3v3"; 563 regulator-min-microvolt = <3300000>; 564 regulator-max-microvolt = <3300000>; 565 enable-active-high; 566 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; 567 vin-supply = <&sys_3v3_reg>; 568 }; 569 570 vdd_cam1_ldo_reg: regulator-cam1 { 571 compatible = "regulator-fixed"; 572 regulator-name = "vdd_cam1_ldo"; 573 regulator-min-microvolt = <2800000>; 574 regulator-max-microvolt = <2800000>; 575 enable-active-high; 576 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; 577 vin-supply = <&sys_3v3_reg>; 578 }; 579 580 vdd_cam2_ldo_reg: regulator-cam2 { 581 compatible = "regulator-fixed"; 582 regulator-name = "vdd_cam2_ldo"; 583 regulator-min-microvolt = <2800000>; 584 regulator-max-microvolt = <2800000>; 585 enable-active-high; 586 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; 587 vin-supply = <&sys_3v3_reg>; 588 }; 589 590 vdd_cam3_ldo_reg: regulator-cam3 { 591 compatible = "regulator-fixed"; 592 regulator-name = "vdd_cam3_ldo"; 593 regulator-min-microvolt = <3300000>; 594 regulator-max-microvolt = <3300000>; 595 enable-active-high; 596 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; 597 vin-supply = <&sys_3v3_reg>; 598 }; 599 600 vdd_com_reg: regulator-com { 601 compatible = "regulator-fixed"; 602 regulator-name = "vdd_com"; 603 regulator-min-microvolt = <3300000>; 604 regulator-max-microvolt = <3300000>; 605 regulator-always-on; 606 regulator-boot-on; 607 enable-active-high; 608 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 609 vin-supply = <&sys_3v3_reg>; 610 }; 611 612 vdd_fuse_3v3_reg: regulator-fuse { 613 compatible = "regulator-fixed"; 614 regulator-name = "vdd_fuse_3v3"; 615 regulator-min-microvolt = <3300000>; 616 regulator-max-microvolt = <3300000>; 617 enable-active-high; 618 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; 619 vin-supply = <&sys_3v3_reg>; 620 }; 621 622 vdd_pnl1_reg: regulator-pnl1 { 623 compatible = "regulator-fixed"; 624 regulator-name = "vdd_pnl1"; 625 regulator-min-microvolt = <3300000>; 626 regulator-max-microvolt = <3300000>; 627 regulator-always-on; 628 regulator-boot-on; 629 enable-active-high; 630 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; 631 vin-supply = <&sys_3v3_reg>; 632 }; 633 634 vdd_vid_reg: regulator-vid { 635 compatible = "regulator-fixed"; 636 regulator-name = "vddio_vid"; 637 regulator-min-microvolt = <5000000>; 638 regulator-max-microvolt = <5000000>; 639 enable-active-high; 640 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; 641 gpio-open-drain; 642 vin-supply = <&vdd_5v0_reg>; 643 }; 644 645 sound { 646 compatible = "nvidia,tegra-audio-wm8903-cardhu", 647 "nvidia,tegra-audio-wm8903"; 648 nvidia,model = "NVIDIA Tegra Cardhu"; 649 650 nvidia,audio-routing = 651 "Headphone Jack", "HPOUTR", 652 "Headphone Jack", "HPOUTL", 653 "Int Spk", "ROP", 654 "Int Spk", "RON", 655 "Int Spk", "LOP", 656 "Int Spk", "LON", 657 "Mic Jack", "MICBIAS", 658 "IN1L", "Mic Jack"; 659 660 nvidia,i2s-controller = <&tegra_i2s1>; 661 nvidia,audio-codec = <&wm8903>; 662 663 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 664 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 665 GPIO_ACTIVE_LOW>; 666 667 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 668 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 669 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 670 clock-names = "pll_a", "pll_a_out0", "mclk"; 671 672 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 673 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 674 675 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 676 <&tegra_car TEGRA30_CLK_EXTERN1>; 677 }; 678 679 thermal-zones { 680 cpu-thermal { 681 polling-delay-passive = <1000>; /* milliseconds */ 682 polling-delay = <5000>; /* milliseconds */ 683 684 thermal-sensors = <&nct1008 1>; 685 686 trips { 687 trip0: cpu-alert0 { 688 /* throttle at 57C until temperature drops to 56.8C */ 689 temperature = <57000>; 690 hysteresis = <200>; 691 type = "passive"; 692 }; 693 694 trip1: cpu-crit { 695 /* shut down at 60C */ 696 temperature = <60000>; 697 hysteresis = <2000>; 698 type = "critical"; 699 }; 700 }; 701 702 cooling-maps { 703 map0 { 704 trip = <&trip0>; 705 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 706 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 707 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 708 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 709 }; 710 }; 711 }; 712 }; 713}; 714