xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra30-asus-transformer-common.dtsi (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2724ba675SRob Herring
3724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h>
4724ba675SRob Herring#include <dt-bindings/input/input.h>
5724ba675SRob Herring#include <dt-bindings/thermal/thermal.h>
6724ba675SRob Herring
7724ba675SRob Herring#include "tegra30.dtsi"
8724ba675SRob Herring#include "tegra30-cpu-opp.dtsi"
9724ba675SRob Herring#include "tegra30-cpu-opp-microvolt.dtsi"
10724ba675SRob Herring
11724ba675SRob Herring/ {
12724ba675SRob Herring	chassis-type = "convertible";
13724ba675SRob Herring
14724ba675SRob Herring	aliases {
15724ba675SRob Herring		mmc0 = "/mmc@78000600"; /* eMMC */
16724ba675SRob Herring		mmc1 = "/mmc@78000000"; /* uSD slot */
17724ba675SRob Herring		mmc2 = "/mmc@78000400"; /* WiFi */
18724ba675SRob Herring
19724ba675SRob Herring		rtc0 = &pmic;
20724ba675SRob Herring		rtc1 = "/rtc@7000e000";
21724ba675SRob Herring
22724ba675SRob Herring		display0 = &lcd;
23724ba675SRob Herring		display1 = &hdmi;
24724ba675SRob Herring
25724ba675SRob Herring		serial1 = &uartc; /* Bluetooth */
26724ba675SRob Herring		serial2 = &uartb; /* GPS */
27724ba675SRob Herring	};
28724ba675SRob Herring
29724ba675SRob Herring	/*
30724ba675SRob Herring	 * The decompressor and also some bootloaders rely on a
31724ba675SRob Herring	 * pre-existing /chosen node to be available to insert the
32724ba675SRob Herring	 * command line and merge other ATAGS info.
33724ba675SRob Herring	 */
34724ba675SRob Herring	chosen {};
35724ba675SRob Herring
36724ba675SRob Herring	firmware {
37724ba675SRob Herring		trusted-foundations {
38724ba675SRob Herring			compatible = "tlm,trusted-foundations";
39724ba675SRob Herring			tlm,version-major = <2>;
40724ba675SRob Herring			tlm,version-minor = <8>;
41724ba675SRob Herring		};
42724ba675SRob Herring	};
43724ba675SRob Herring
44724ba675SRob Herring	memory@80000000 {
45724ba675SRob Herring		reg = <0x80000000 0x40000000>;
46724ba675SRob Herring	};
47724ba675SRob Herring
48724ba675SRob Herring	reserved-memory {
49724ba675SRob Herring		#address-cells = <1>;
50724ba675SRob Herring		#size-cells = <1>;
51724ba675SRob Herring		ranges;
52724ba675SRob Herring
53724ba675SRob Herring		linux,cma@80000000 {
54724ba675SRob Herring			compatible = "shared-dma-pool";
55724ba675SRob Herring			alloc-ranges = <0x80000000 0x30000000>;
56724ba675SRob Herring			size = <0x10000000>;		/* 256MiB */
57724ba675SRob Herring			linux,cma-default;
58724ba675SRob Herring			reusable;
59724ba675SRob Herring		};
60724ba675SRob Herring
61724ba675SRob Herring		ramoops@beb00000 {
62724ba675SRob Herring			compatible = "ramoops";
63724ba675SRob Herring			reg = <0xbeb00000 0x10000>;	/* 64kB */
64724ba675SRob Herring			console-size = <0x8000>;	/* 32kB */
65724ba675SRob Herring			record-size = <0x400>;		/*  1kB */
66724ba675SRob Herring			ecc-size = <16>;
67724ba675SRob Herring		};
68724ba675SRob Herring
69724ba675SRob Herring		trustzone@bfe00000 {
70724ba675SRob Herring			reg = <0xbfe00000 0x200000>;	/* 2MB */
71724ba675SRob Herring			no-map;
72724ba675SRob Herring		};
73724ba675SRob Herring	};
74724ba675SRob Herring
75724ba675SRob Herring	host1x@50000000 {
76724ba675SRob Herring		hdmi: hdmi@54280000 {
77724ba675SRob Herring			status = "okay";
78724ba675SRob Herring
79724ba675SRob Herring			hdmi-supply = <&hdmi_5v0_sys>;
80724ba675SRob Herring			pll-supply = <&vdd_1v8_vio>;
81724ba675SRob Herring			vdd-supply = <&vdd_3v3_sys>;
82724ba675SRob Herring
83724ba675SRob Herring			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
84724ba675SRob Herring			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85724ba675SRob Herring		};
86724ba675SRob Herring	};
87724ba675SRob Herring
88724ba675SRob Herring	gpio@6000d000 {
89724ba675SRob Herring		init-lpm-in-hog {
90724ba675SRob Herring			gpio-hog;
91724ba675SRob Herring			gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
92724ba675SRob Herring				<TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
93724ba675SRob Herring			input;
94724ba675SRob Herring		};
95724ba675SRob Herring
96724ba675SRob Herring		init-lpm-out-hog {
97724ba675SRob Herring			gpio-hog;
98724ba675SRob Herring			gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
99724ba675SRob Herring				<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
100724ba675SRob Herring			output-low;
101724ba675SRob Herring		};
102724ba675SRob Herring
103724ba675SRob Herring		usb-charge-limit-hog {
104724ba675SRob Herring			gpio-hog;
105724ba675SRob Herring			gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
106724ba675SRob Herring			output-high;
107724ba675SRob Herring		};
108724ba675SRob Herring	};
109724ba675SRob Herring
110724ba675SRob Herring	vde@6001a000 {
111724ba675SRob Herring		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
112724ba675SRob Herring		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
113724ba675SRob Herring		assigned-clock-rates = <408000000>;
114724ba675SRob Herring	};
115724ba675SRob Herring
116724ba675SRob Herring	pinmux@70000868 {
117724ba675SRob Herring		pinctrl-names = "default";
118724ba675SRob Herring		pinctrl-0 = <&state_default>;
119724ba675SRob Herring
120724ba675SRob Herring		state_default: pinmux {
121724ba675SRob Herring			/* SDMMC1 pinmux */
122724ba675SRob Herring			sdmmc1_clk {
123724ba675SRob Herring				nvidia,pins = "sdmmc1_clk_pz0";
124724ba675SRob Herring				nvidia,function = "sdmmc1";
125724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
127724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128724ba675SRob Herring			};
129724ba675SRob Herring
130724ba675SRob Herring			sdmmc1_cmd {
131724ba675SRob Herring				nvidia,pins = "sdmmc1_dat3_py4",
132724ba675SRob Herring						"sdmmc1_dat2_py5",
133724ba675SRob Herring						"sdmmc1_dat1_py6",
134724ba675SRob Herring						"sdmmc1_dat0_py7",
135724ba675SRob Herring						"sdmmc1_cmd_pz1";
136724ba675SRob Herring				nvidia,function = "sdmmc1";
137724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
138724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
139724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140724ba675SRob Herring			};
141724ba675SRob Herring
142724ba675SRob Herring			sdmmc1_cd {
143724ba675SRob Herring				nvidia,pins = "gmi_iordy_pi5";
144724ba675SRob Herring				nvidia,function = "rsvd1";
145724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
146724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
147724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148724ba675SRob Herring			};
149724ba675SRob Herring
150724ba675SRob Herring			sdmmc1_wp {
151724ba675SRob Herring				nvidia,pins = "vi_d11_pt3";
152724ba675SRob Herring				nvidia,function = "rsvd2";
153724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
154724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
155724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156724ba675SRob Herring			};
157724ba675SRob Herring
158724ba675SRob Herring			/* SDMMC2 pinmux */
159724ba675SRob Herring			vi_d1_pd5 {
160724ba675SRob Herring				nvidia,pins = "vi_d1_pd5",
161724ba675SRob Herring						"vi_d2_pl0",
162724ba675SRob Herring						"vi_d3_pl1",
163724ba675SRob Herring						"vi_d5_pl3",
164724ba675SRob Herring						"vi_d7_pl5";
165724ba675SRob Herring				nvidia,function = "sdmmc2";
166724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169724ba675SRob Herring			};
170724ba675SRob Herring
171724ba675SRob Herring			vi_d8_pl6 {
172724ba675SRob Herring				nvidia,pins = "vi_d8_pl6",
173724ba675SRob Herring						"vi_d9_pl7";
174724ba675SRob Herring				nvidia,function = "sdmmc2";
175724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
177724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178724ba675SRob Herring				nvidia,lock = <0>;
179724ba675SRob Herring				nvidia,io-reset = <0>;
180724ba675SRob Herring			};
181724ba675SRob Herring
182724ba675SRob Herring			/* SDMMC3 pinmux */
183724ba675SRob Herring			sdmmc3_clk {
184724ba675SRob Herring				nvidia,pins = "sdmmc3_clk_pa6";
185724ba675SRob Herring				nvidia,function = "sdmmc3";
186724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
188724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189724ba675SRob Herring			};
190724ba675SRob Herring
191724ba675SRob Herring			sdmmc3_cmd {
192724ba675SRob Herring				nvidia,pins = "sdmmc3_cmd_pa7",
193724ba675SRob Herring						"sdmmc3_dat0_pb7",
194724ba675SRob Herring						"sdmmc3_dat1_pb6",
195724ba675SRob Herring						"sdmmc3_dat2_pb5",
196724ba675SRob Herring						"sdmmc3_dat3_pb4",
197724ba675SRob Herring						"sdmmc3_dat4_pd1",
198724ba675SRob Herring						"sdmmc3_dat5_pd0",
199724ba675SRob Herring						"sdmmc3_dat6_pd3",
200724ba675SRob Herring						"sdmmc3_dat7_pd4";
201724ba675SRob Herring				nvidia,function = "sdmmc3";
202724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
203724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
204724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
205724ba675SRob Herring			};
206724ba675SRob Herring
207724ba675SRob Herring			/* SDMMC4 pinmux */
208724ba675SRob Herring			sdmmc4_clk {
209724ba675SRob Herring				nvidia,pins = "sdmmc4_clk_pcc4";
210724ba675SRob Herring				nvidia,function = "sdmmc4";
211724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
213724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214724ba675SRob Herring			};
215724ba675SRob Herring
216724ba675SRob Herring			sdmmc4_cmd {
217724ba675SRob Herring				nvidia,pins = "sdmmc4_cmd_pt7",
218724ba675SRob Herring						"sdmmc4_dat0_paa0",
219724ba675SRob Herring						"sdmmc4_dat1_paa1",
220724ba675SRob Herring						"sdmmc4_dat2_paa2",
221724ba675SRob Herring						"sdmmc4_dat3_paa3",
222724ba675SRob Herring						"sdmmc4_dat4_paa4",
223724ba675SRob Herring						"sdmmc4_dat5_paa5",
224724ba675SRob Herring						"sdmmc4_dat6_paa6",
225724ba675SRob Herring						"sdmmc4_dat7_paa7";
226724ba675SRob Herring				nvidia,function = "sdmmc4";
227724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
228724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
229724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230724ba675SRob Herring			};
231724ba675SRob Herring
232724ba675SRob Herring			sdmmc4_rst_n {
233724ba675SRob Herring				nvidia,pins = "sdmmc4_rst_n_pcc3";
234724ba675SRob Herring				nvidia,function = "rsvd2";
235724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
236724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238724ba675SRob Herring			};
239724ba675SRob Herring
240724ba675SRob Herring			cam_mclk {
241724ba675SRob Herring				nvidia,pins = "cam_mclk_pcc0";
242724ba675SRob Herring				nvidia,function = "vi_alt3";
243724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
244724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
245724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246724ba675SRob Herring			};
247724ba675SRob Herring
248724ba675SRob Herring			drive_sdmmc4 {
249724ba675SRob Herring				nvidia,pins = "drive_gma",
250724ba675SRob Herring						"drive_gmb",
251724ba675SRob Herring						"drive_gmc",
252724ba675SRob Herring						"drive_gmd";
253724ba675SRob Herring				nvidia,pull-down-strength = <9>;
254724ba675SRob Herring				nvidia,pull-up-strength = <9>;
255724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
256724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
257724ba675SRob Herring			};
258724ba675SRob Herring
259724ba675SRob Herring			/* I2C pinmux */
260724ba675SRob Herring			gen1_i2c {
261724ba675SRob Herring				nvidia,pins = "gen1_i2c_scl_pc4",
262724ba675SRob Herring						"gen1_i2c_sda_pc5";
263724ba675SRob Herring				nvidia,function = "i2c1";
264724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
266724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
268724ba675SRob Herring				nvidia,lock = <0>;
269724ba675SRob Herring			};
270724ba675SRob Herring
271724ba675SRob Herring			gen2_i2c {
272724ba675SRob Herring				nvidia,pins = "gen2_i2c_scl_pt5",
273724ba675SRob Herring						"gen2_i2c_sda_pt6";
274724ba675SRob Herring				nvidia,function = "i2c2";
275724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
277724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
279724ba675SRob Herring				nvidia,lock = <0>;
280724ba675SRob Herring			};
281724ba675SRob Herring
282724ba675SRob Herring			cam_i2c {
283724ba675SRob Herring				nvidia,pins = "cam_i2c_scl_pbb1",
284724ba675SRob Herring						"cam_i2c_sda_pbb2";
285724ba675SRob Herring				nvidia,function = "i2c3";
286724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
290724ba675SRob Herring				nvidia,lock = <0>;
291724ba675SRob Herring			};
292724ba675SRob Herring
293724ba675SRob Herring			ddc_i2c {
294724ba675SRob Herring				nvidia,pins = "ddc_scl_pv4",
295724ba675SRob Herring						"ddc_sda_pv5";
296724ba675SRob Herring				nvidia,function = "i2c4";
297724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
299724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
300724ba675SRob Herring				nvidia,lock = <0>;
301724ba675SRob Herring			};
302724ba675SRob Herring
303724ba675SRob Herring			pwr_i2c {
304724ba675SRob Herring				nvidia,pins = "pwr_i2c_scl_pz6",
305724ba675SRob Herring						"pwr_i2c_sda_pz7";
306724ba675SRob Herring				nvidia,function = "i2cpwr";
307724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
309724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
311724ba675SRob Herring				nvidia,lock = <0>;
312724ba675SRob Herring			};
313724ba675SRob Herring
314724ba675SRob Herring			hotplug_i2c {
315724ba675SRob Herring				nvidia,pins = "pu4";
316724ba675SRob Herring				nvidia,function = "rsvd4";
317724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
318724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
319724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
320724ba675SRob Herring			};
321724ba675SRob Herring
322724ba675SRob Herring			/* HDMI pinmux */
323724ba675SRob Herring			hdmi_cec {
324724ba675SRob Herring				nvidia,pins = "hdmi_cec_pee3";
325724ba675SRob Herring				nvidia,function = "cec";
326724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
328724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330724ba675SRob Herring				nvidia,lock = <0>;
331724ba675SRob Herring			};
332724ba675SRob Herring
333724ba675SRob Herring			hdmi_hpd {
334724ba675SRob Herring				nvidia,pins = "hdmi_int_pn7";
335724ba675SRob Herring				nvidia,function = "hdmi";
336724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
337724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
338724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
339724ba675SRob Herring			};
340724ba675SRob Herring
341724ba675SRob Herring			/* UART-A */
342724ba675SRob Herring			ulpi_data0_po1 {
343724ba675SRob Herring				nvidia,pins = "ulpi_data0_po1";
344724ba675SRob Herring				nvidia,function = "uarta";
345724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
347724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348724ba675SRob Herring			};
349724ba675SRob Herring
350724ba675SRob Herring			ulpi_data1_po2 {
351724ba675SRob Herring				nvidia,pins = "ulpi_data1_po2";
352724ba675SRob Herring				nvidia,function = "uarta";
353724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356724ba675SRob Herring			};
357724ba675SRob Herring
358724ba675SRob Herring			ulpi_data5_po6 {
359724ba675SRob Herring				nvidia,pins = "ulpi_data5_po6";
360724ba675SRob Herring				nvidia,function = "uarta";
361724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
363724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364724ba675SRob Herring			};
365724ba675SRob Herring
366724ba675SRob Herring			ulpi_data7_po0 {
367724ba675SRob Herring				nvidia,pins = "ulpi_data7_po0",
368724ba675SRob Herring						"ulpi_data2_po3",
369724ba675SRob Herring						"ulpi_data3_po4",
370724ba675SRob Herring						"ulpi_data4_po5",
371724ba675SRob Herring						"ulpi_data6_po7";
372724ba675SRob Herring				nvidia,function = "uarta";
373724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
375724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376724ba675SRob Herring			};
377724ba675SRob Herring
378724ba675SRob Herring			/* UART-B */
379724ba675SRob Herring			uartb_txd_rts {
380724ba675SRob Herring				nvidia,pins = "uart2_txd_pc2",
381724ba675SRob Herring						"uart2_rts_n_pj6";
382724ba675SRob Herring				nvidia,function = "uartb";
383724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
385724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386724ba675SRob Herring			};
387724ba675SRob Herring
388724ba675SRob Herring			uartb_rxd_cts {
389724ba675SRob Herring				nvidia,pins = "uart2_rxd_pc3",
390724ba675SRob Herring						"uart2_cts_n_pj5";
391724ba675SRob Herring				nvidia,function = "uartb";
392724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395724ba675SRob Herring			};
396724ba675SRob Herring
397724ba675SRob Herring			/* UART-C */
398724ba675SRob Herring			uartc_rxd_cts {
399724ba675SRob Herring				nvidia,pins = "uart3_cts_n_pa1",
400724ba675SRob Herring						"uart3_rxd_pw7";
401724ba675SRob Herring				nvidia,function = "uartc";
402724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
405724ba675SRob Herring			};
406724ba675SRob Herring
407724ba675SRob Herring			uartc_txd_rts {
408724ba675SRob Herring				nvidia,pins = "uart3_rts_n_pc0",
409724ba675SRob Herring						"uart3_txd_pw6";
410724ba675SRob Herring				nvidia,function = "uartc";
411724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
413724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414724ba675SRob Herring			};
415724ba675SRob Herring
416724ba675SRob Herring			/* UART-D */
417724ba675SRob Herring			ulpi_nxt_py2 {
418724ba675SRob Herring				nvidia,pins = "ulpi_nxt_py2";
419724ba675SRob Herring				nvidia,function = "uartd";
420724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
422724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423724ba675SRob Herring			};
424724ba675SRob Herring
425724ba675SRob Herring			ulpi_clk_py0 {
426724ba675SRob Herring				nvidia,pins = "ulpi_clk_py0",
427724ba675SRob Herring						"ulpi_dir_py1",
428724ba675SRob Herring						"ulpi_stp_py3";
429724ba675SRob Herring				nvidia,function = "uartd";
430724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
432724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433724ba675SRob Herring			};
434724ba675SRob Herring
435724ba675SRob Herring			/* I2S pinmux */
436724ba675SRob Herring			dap_i2s0 {
437724ba675SRob Herring				nvidia,pins = "dap1_fs_pn0",
438724ba675SRob Herring						"dap1_din_pn1",
439724ba675SRob Herring						"dap1_dout_pn2",
440724ba675SRob Herring						"dap1_sclk_pn3";
441724ba675SRob Herring				nvidia,function = "i2s0";
442724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
444724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445724ba675SRob Herring			};
446724ba675SRob Herring
447724ba675SRob Herring			dap_i2s1 {
448724ba675SRob Herring				nvidia,pins = "dap2_fs_pa2",
449724ba675SRob Herring						"dap2_sclk_pa3",
450724ba675SRob Herring						"dap2_din_pa4",
451724ba675SRob Herring						"dap2_dout_pa5";
452724ba675SRob Herring				nvidia,function = "i2s1";
453724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
455724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456724ba675SRob Herring			};
457724ba675SRob Herring
458724ba675SRob Herring			dap3_fs {
459724ba675SRob Herring				nvidia,pins = "dap3_fs_pp0",
460724ba675SRob Herring						"dap3_din_pp1";
461724ba675SRob Herring				nvidia,function = "i2s2";
462724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
464724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465724ba675SRob Herring			};
466724ba675SRob Herring
467724ba675SRob Herring			dap3_dout {
468724ba675SRob Herring				nvidia,pins = "dap3_dout_pp2",
469724ba675SRob Herring						"dap3_sclk_pp3";
470724ba675SRob Herring				nvidia,function = "i2s2";
471724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
473724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474724ba675SRob Herring			};
475724ba675SRob Herring
476724ba675SRob Herring			dap_i2s3 {
477724ba675SRob Herring				nvidia,pins = "dap4_fs_pp4",
478724ba675SRob Herring						"dap4_din_pp5",
479724ba675SRob Herring						"dap4_dout_pp6",
480724ba675SRob Herring						"dap4_sclk_pp7";
481724ba675SRob Herring				nvidia,function = "i2s3";
482724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
484724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
485724ba675SRob Herring			};
486724ba675SRob Herring
487724ba675SRob Herring			/* Sensors pinmux */
488724ba675SRob Herring			nct_irq {
489724ba675SRob Herring				nvidia,pins = "pcc2";
490724ba675SRob Herring				nvidia,function = "i2s4";
491724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
492724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
493724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494724ba675SRob Herring			};
495724ba675SRob Herring
496724ba675SRob Herring			/* Asus EC pinmux */
497724ba675SRob Herring			ec_irqs {
498724ba675SRob Herring				nvidia,pins = "kb_row10_ps2",
499724ba675SRob Herring						"kb_row15_ps7";
500724ba675SRob Herring				nvidia,function = "kbc";
501724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
502724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
503724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504724ba675SRob Herring			};
505724ba675SRob Herring
506724ba675SRob Herring			ec_reqs {
507724ba675SRob Herring				nvidia,pins = "kb_col1_pq1";
508724ba675SRob Herring				nvidia,function = "kbc";
509724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
510724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
511724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512724ba675SRob Herring			};
513724ba675SRob Herring
514724ba675SRob Herring			/* Memory type bootstrap */
515724ba675SRob Herring			mem_boostraps {
516724ba675SRob Herring				nvidia,pins = "gmi_ad4_pg4",
517724ba675SRob Herring						"gmi_ad5_pg5";
518724ba675SRob Herring				nvidia,function = "nand";
519724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
521724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522724ba675SRob Herring			};
523724ba675SRob Herring
524724ba675SRob Herring			/* PCI-e pinmux */
525724ba675SRob Herring			pex_l2_rst_n {
526724ba675SRob Herring				nvidia,pins = "pex_l2_rst_n_pcc6",
527724ba675SRob Herring						"pex_l0_rst_n_pdd1",
528724ba675SRob Herring						"pex_l1_rst_n_pdd5";
529724ba675SRob Herring				nvidia,function = "pcie";
530724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
532724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533724ba675SRob Herring			};
534724ba675SRob Herring
535724ba675SRob Herring			pex_l2_clkreq_n {
536724ba675SRob Herring				nvidia,pins = "pex_l2_clkreq_n_pcc7",
537724ba675SRob Herring						"pex_l0_prsnt_n_pdd0",
538724ba675SRob Herring						"pex_l0_clkreq_n_pdd2",
539724ba675SRob Herring						"pex_wake_n_pdd3",
540724ba675SRob Herring						"pex_l1_prsnt_n_pdd4",
541724ba675SRob Herring						"pex_l1_clkreq_n_pdd6",
542724ba675SRob Herring						"pex_l2_prsnt_n_pdd7";
543724ba675SRob Herring				nvidia,function = "pcie";
544724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
546724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547724ba675SRob Herring			};
548724ba675SRob Herring
549724ba675SRob Herring			/* SPI pinmux */
550724ba675SRob Herring			spi1_mosi_px4 {
551724ba675SRob Herring				nvidia,pins = "spi1_mosi_px4",
552724ba675SRob Herring						"spi1_sck_px5",
553724ba675SRob Herring						"spi1_cs0_n_px6",
554724ba675SRob Herring						"spi1_miso_px7";
555724ba675SRob Herring				nvidia,function = "spi1";
556724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
558724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
559724ba675SRob Herring			};
560724ba675SRob Herring
561724ba675SRob Herring			hp_detect {
562724ba675SRob Herring				nvidia,pins = "spi2_cs1_n_pw2";
563724ba675SRob Herring				nvidia,function = "spi2";
564724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
565724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
566724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567724ba675SRob Herring			};
568724ba675SRob Herring
569724ba675SRob Herring			mic_detect {
570724ba675SRob Herring				nvidia,pins = "spi2_sck_px2";
571724ba675SRob Herring				nvidia,function = "spi2";
572724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
573724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
574724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
575724ba675SRob Herring			};
576724ba675SRob Herring
577724ba675SRob Herring			gmi_a17_pb0 {
578724ba675SRob Herring				nvidia,pins = "gmi_a17_pb0",
579724ba675SRob Herring						"gmi_a16_pj7";
580724ba675SRob Herring				nvidia,function = "spi4";
581724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
583724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
584724ba675SRob Herring			};
585724ba675SRob Herring
586724ba675SRob Herring			gmi_a18_pb1 {
587724ba675SRob Herring				nvidia,pins = "gmi_a18_pb1";
588724ba675SRob Herring				nvidia,function = "spi4";
589724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
590724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
591724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592724ba675SRob Herring			};
593724ba675SRob Herring
594724ba675SRob Herring			gmi_a19_pk7 {
595724ba675SRob Herring				nvidia,pins = "gmi_a19_pk7";
596724ba675SRob Herring				nvidia,function = "spi4";
597724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
599724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600724ba675SRob Herring			};
601724ba675SRob Herring
602724ba675SRob Herring			/* Display A pinmux */
603724ba675SRob Herring			lcd_pwr0_pb2 {
604724ba675SRob Herring				nvidia,pins = "lcd_pwr0_pb2",
605724ba675SRob Herring						"lcd_pclk_pb3",
606724ba675SRob Herring						"lcd_pwr1_pc1",
607724ba675SRob Herring						"lcd_d0_pe0",
608724ba675SRob Herring						"lcd_d1_pe1",
609724ba675SRob Herring						"lcd_d2_pe2",
610724ba675SRob Herring						"lcd_d3_pe3",
611724ba675SRob Herring						"lcd_d4_pe4",
612724ba675SRob Herring						"lcd_d5_pe5",
613724ba675SRob Herring						"lcd_d6_pe6",
614724ba675SRob Herring						"lcd_d7_pe7",
615724ba675SRob Herring						"lcd_d8_pf0",
616724ba675SRob Herring						"lcd_d9_pf1",
617724ba675SRob Herring						"lcd_d10_pf2",
618724ba675SRob Herring						"lcd_d11_pf3",
619724ba675SRob Herring						"lcd_d12_pf4",
620724ba675SRob Herring						"lcd_d13_pf5",
621724ba675SRob Herring						"lcd_d14_pf6",
622724ba675SRob Herring						"lcd_d15_pf7",
623724ba675SRob Herring						"lcd_de_pj1",
624724ba675SRob Herring						"lcd_hsync_pj3",
625724ba675SRob Herring						"lcd_vsync_pj4",
626724ba675SRob Herring						"lcd_d16_pm0",
627724ba675SRob Herring						"lcd_d17_pm1",
628724ba675SRob Herring						"lcd_d18_pm2",
629724ba675SRob Herring						"lcd_d19_pm3",
630724ba675SRob Herring						"lcd_d20_pm4",
631724ba675SRob Herring						"lcd_d21_pm5",
632724ba675SRob Herring						"lcd_d22_pm6",
633724ba675SRob Herring						"lcd_d23_pm7",
634724ba675SRob Herring						"lcd_dc0_pn6",
635724ba675SRob Herring						"lcd_sdin_pz2";
636724ba675SRob Herring				nvidia,function = "displaya";
637724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
639724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
640724ba675SRob Herring			};
641724ba675SRob Herring
642724ba675SRob Herring			lcd_cs0_n_pn4 {
643724ba675SRob Herring				nvidia,pins = "lcd_cs0_n_pn4",
644724ba675SRob Herring						"lcd_sdout_pn5",
645724ba675SRob Herring						"lcd_wr_n_pz3";
646724ba675SRob Herring				nvidia,function = "displaya";
647724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
649724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
650724ba675SRob Herring			};
651724ba675SRob Herring
652724ba675SRob Herring			blink {
653724ba675SRob Herring				nvidia,pins = "clk_32k_out_pa0";
654724ba675SRob Herring				nvidia,function = "blink";
655724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
657724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658724ba675SRob Herring			};
659724ba675SRob Herring
660724ba675SRob Herring			/* KBC keys */
661724ba675SRob Herring			kb_col0_pq0 {
662724ba675SRob Herring				nvidia,pins = "kb_col0_pq0";
663724ba675SRob Herring				nvidia,function = "kbc";
664724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
666724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
667724ba675SRob Herring			};
668724ba675SRob Herring
669724ba675SRob Herring			kb_col1_pq1 {
670724ba675SRob Herring				nvidia,pins = "kb_row1_pr1",
671724ba675SRob Herring						"kb_row3_pr3",
672724ba675SRob Herring						"kb_row8_ps0",
673724ba675SRob Herring						"kb_row14_ps6";
674724ba675SRob Herring				nvidia,function = "kbc";
675724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
676724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
677724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678724ba675SRob Herring			};
679724ba675SRob Herring
680724ba675SRob Herring			kb_col4_pq4 {
681724ba675SRob Herring				nvidia,pins = "kb_col4_pq4",
682724ba675SRob Herring						"kb_col5_pq5",
683724ba675SRob Herring						"kb_col7_pq7",
684724ba675SRob Herring						"kb_row2_pr2",
685724ba675SRob Herring						"kb_row4_pr4",
686724ba675SRob Herring						"kb_row5_pr5",
687724ba675SRob Herring						"kb_row12_ps4",
688724ba675SRob Herring						"kb_row13_ps5";
689724ba675SRob Herring				nvidia,function = "kbc";
690724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
691724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
692724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
693724ba675SRob Herring			};
694724ba675SRob Herring
695724ba675SRob Herring			gmi_wp_n_pc7 {
696724ba675SRob Herring				nvidia,pins = "gmi_wp_n_pc7",
697724ba675SRob Herring						"gmi_wait_pi7",
698724ba675SRob Herring						"gmi_cs3_n_pk4";
699724ba675SRob Herring				nvidia,function = "rsvd1";
700724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
702724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703724ba675SRob Herring			};
704724ba675SRob Herring
705724ba675SRob Herring			gmi_cs0_n_pj0 {
706724ba675SRob Herring				nvidia,pins = "gmi_cs0_n_pj0",
707724ba675SRob Herring						"gmi_cs1_n_pj2",
708724ba675SRob Herring						"gmi_cs2_n_pk3";
709724ba675SRob Herring				nvidia,function = "rsvd1";
710724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
712724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713724ba675SRob Herring			};
714724ba675SRob Herring
715724ba675SRob Herring			vi_pclk_pt0 {
716724ba675SRob Herring				nvidia,pins = "vi_pclk_pt0";
717724ba675SRob Herring				nvidia,function = "rsvd1";
718724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
719724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
720724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721724ba675SRob Herring				nvidia,lock = <0>;
722724ba675SRob Herring				nvidia,io-reset = <0>;
723724ba675SRob Herring			};
724724ba675SRob Herring
725724ba675SRob Herring			/* GPIO keys pinmux */
726724ba675SRob Herring			power_key {
727724ba675SRob Herring				nvidia,pins = "pv0";
728724ba675SRob Herring				nvidia,function = "rsvd1";
729724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
730724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
731724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
732724ba675SRob Herring			};
733724ba675SRob Herring
734724ba675SRob Herring			vol_keys {
735724ba675SRob Herring				nvidia,pins = "kb_col2_pq2",
736724ba675SRob Herring						"kb_col3_pq3";
737724ba675SRob Herring				nvidia,function = "rsvd4";
738724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
740724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741724ba675SRob Herring			};
742724ba675SRob Herring
743724ba675SRob Herring			/* Bluetooth */
744724ba675SRob Herring			bt_shutdown {
745724ba675SRob Herring				nvidia,pins = "pu0";
746724ba675SRob Herring				nvidia,function = "rsvd4";
747724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
749724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
750724ba675SRob Herring			};
751724ba675SRob Herring
752724ba675SRob Herring			bt_dev_wake {
753724ba675SRob Herring				nvidia,pins = "pu1";
754724ba675SRob Herring				nvidia,function = "rsvd1";
755724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
757724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758724ba675SRob Herring			};
759724ba675SRob Herring
760724ba675SRob Herring			bt_host_wake {
761724ba675SRob Herring				nvidia,pins = "pu6";
762724ba675SRob Herring				nvidia,function = "rsvd4";
763724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
765724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766724ba675SRob Herring			};
767724ba675SRob Herring
768724ba675SRob Herring			pu2 {
769724ba675SRob Herring				nvidia,pins = "pu2";
770724ba675SRob Herring				nvidia,function = "rsvd1";
771724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
773724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774724ba675SRob Herring			};
775724ba675SRob Herring
776724ba675SRob Herring			pu3 {
777724ba675SRob Herring				nvidia,pins = "pu3";
778724ba675SRob Herring				nvidia,function = "rsvd4";
779724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
781724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782724ba675SRob Herring			};
783724ba675SRob Herring
784724ba675SRob Herring			pcc1 {
785724ba675SRob Herring				nvidia,pins = "pcc1";
786724ba675SRob Herring				nvidia,function = "rsvd2";
787724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
788724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
789724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
790724ba675SRob Herring			};
791724ba675SRob Herring
792724ba675SRob Herring			pv2 {
793724ba675SRob Herring				nvidia,pins = "pv2";
794724ba675SRob Herring				nvidia,function = "rsvd2";
795724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
797724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798724ba675SRob Herring			};
799724ba675SRob Herring
800724ba675SRob Herring			pv3 {
801724ba675SRob Herring				nvidia,pins = "pv3";
802724ba675SRob Herring				nvidia,function = "rsvd2";
803724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
805724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806724ba675SRob Herring			};
807724ba675SRob Herring
808724ba675SRob Herring			vi_vsync_pd6 {
809724ba675SRob Herring				nvidia,pins = "vi_vsync_pd6",
810724ba675SRob Herring						"vi_hsync_pd7";
811724ba675SRob Herring				nvidia,function = "rsvd2";
812724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
814724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815724ba675SRob Herring				nvidia,lock = <0>;
816724ba675SRob Herring				nvidia,io-reset = <0>;
817724ba675SRob Herring			};
818724ba675SRob Herring
819724ba675SRob Herring			vi_d10_pt2 {
820724ba675SRob Herring				nvidia,pins = "vi_d10_pt2",
821724ba675SRob Herring						"vi_d0_pt4", "pbb0";
822724ba675SRob Herring				nvidia,function = "rsvd2";
823724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
825724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826724ba675SRob Herring			};
827724ba675SRob Herring
828724ba675SRob Herring			kb_row0_pr0 {
829724ba675SRob Herring				nvidia,pins = "kb_row0_pr0";
830724ba675SRob Herring				nvidia,function = "rsvd4";
831724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
832724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
833724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
834724ba675SRob Herring			};
835724ba675SRob Herring
836724ba675SRob Herring			gmi_ad0_pg0 {
837724ba675SRob Herring				nvidia,pins = "gmi_ad0_pg0",
838724ba675SRob Herring						"gmi_ad1_pg1",
839724ba675SRob Herring						"gmi_ad2_pg2",
840724ba675SRob Herring						"gmi_ad3_pg3",
841724ba675SRob Herring						"gmi_ad6_pg6",
842724ba675SRob Herring						"gmi_ad7_pg7",
843724ba675SRob Herring						"gmi_wr_n_pi0",
844724ba675SRob Herring						"gmi_oe_n_pi1",
845724ba675SRob Herring						"gmi_dqs_pi2",
846724ba675SRob Herring						"gmi_adv_n_pk0",
847724ba675SRob Herring						"gmi_clk_pk1";
848724ba675SRob Herring				nvidia,function = "nand";
849724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
851724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
852724ba675SRob Herring			};
853724ba675SRob Herring
854724ba675SRob Herring			gmi_ad13_ph5 {
855724ba675SRob Herring				nvidia,pins = "gmi_ad13_ph5";
856724ba675SRob Herring				nvidia,function = "nand";
857724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
858724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
859724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
860724ba675SRob Herring			};
861724ba675SRob Herring
862724ba675SRob Herring			gmi_ad10_ph2 {
863724ba675SRob Herring				nvidia,pins = "gmi_ad10_ph2",
864724ba675SRob Herring						"gmi_ad11_ph3",
865724ba675SRob Herring						"gmi_ad14_ph6";
866724ba675SRob Herring				nvidia,function = "nand";
867724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
868724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
869724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
870724ba675SRob Herring			};
871724ba675SRob Herring
872724ba675SRob Herring			gmi_ad12_ph4 {
873724ba675SRob Herring				nvidia,pins = "gmi_ad12_ph4",
874724ba675SRob Herring						"gmi_rst_n_pi4",
875724ba675SRob Herring						"gmi_cs7_n_pi6";
876724ba675SRob Herring				nvidia,function = "nand";
877724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
878724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
879724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
880724ba675SRob Herring			};
881724ba675SRob Herring
882724ba675SRob Herring			/* Vibrator control */
883724ba675SRob Herring			vibrator {
884724ba675SRob Herring				nvidia,pins = "gmi_ad15_ph7";
885724ba675SRob Herring				nvidia,function = "nand";
886724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
887724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
888724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
889724ba675SRob Herring			};
890724ba675SRob Herring
891724ba675SRob Herring			/* PWM pimnmux */
892724ba675SRob Herring			pwm_0 {
893724ba675SRob Herring				nvidia,pins = "gmi_ad8_ph0";
894724ba675SRob Herring				nvidia,function = "pwm0";
895724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
897724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
898724ba675SRob Herring			};
899724ba675SRob Herring
900724ba675SRob Herring			pwm_2 {
901724ba675SRob Herring				nvidia,pins = "pu5";
902724ba675SRob Herring				nvidia,function = "pwm2";
903724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
905724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906724ba675SRob Herring			};
907724ba675SRob Herring
908724ba675SRob Herring			gmi_cs6_n_pi3 {
909724ba675SRob Herring				nvidia,pins = "gmi_cs6_n_pi3";
910724ba675SRob Herring				nvidia,function = "gmi";
911724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
912724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
913724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
914724ba675SRob Herring			};
915724ba675SRob Herring
916724ba675SRob Herring			/* Spdif pinmux */
917724ba675SRob Herring			spdif_out {
918724ba675SRob Herring				nvidia,pins = "spdif_out_pk5";
919724ba675SRob Herring				nvidia,function = "spdif";
920724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
921724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
922724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
923724ba675SRob Herring			};
924724ba675SRob Herring
925724ba675SRob Herring			spdif_in {
926724ba675SRob Herring				nvidia,pins = "spdif_in_pk6";
927724ba675SRob Herring				nvidia,function = "spdif";
928724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
929724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
930724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
931724ba675SRob Herring			};
932724ba675SRob Herring
933724ba675SRob Herring			vi_d4_pl2 {
934724ba675SRob Herring				nvidia,pins = "vi_d4_pl2";
935724ba675SRob Herring				nvidia,function = "vi";
936724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
938724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939724ba675SRob Herring			};
940724ba675SRob Herring
941724ba675SRob Herring			vi_d6_pl4 {
942724ba675SRob Herring				nvidia,pins = "vi_d6_pl4";
943724ba675SRob Herring				nvidia,function = "vi";
944724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
946724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
947724ba675SRob Herring				nvidia,lock = <0>;
948724ba675SRob Herring				nvidia,io-reset = <0>;
949724ba675SRob Herring			};
950724ba675SRob Herring
951724ba675SRob Herring			vi_mclk_pt1 {
952724ba675SRob Herring				nvidia,pins = "vi_mclk_pt1";
953724ba675SRob Herring				nvidia,function = "vi";
954724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
955724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
956724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
957724ba675SRob Herring			};
958724ba675SRob Herring
959724ba675SRob Herring			jtag_rtck {
960724ba675SRob Herring				nvidia,pins = "jtag_rtck_pu7";
961724ba675SRob Herring				nvidia,function = "rtck";
962724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
964724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
965724ba675SRob Herring			};
966724ba675SRob Herring
967724ba675SRob Herring			crt_hsync_pv6 {
968724ba675SRob Herring				nvidia,pins = "crt_hsync_pv6",
969724ba675SRob Herring						"crt_vsync_pv7";
970724ba675SRob Herring				nvidia,function = "crt";
971724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
973724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974724ba675SRob Herring			};
975724ba675SRob Herring
976724ba675SRob Herring			clk1_out {
977724ba675SRob Herring				nvidia,pins = "clk1_out_pw4";
978724ba675SRob Herring				nvidia,function = "extperiph1";
979724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
981724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982724ba675SRob Herring			};
983724ba675SRob Herring
984724ba675SRob Herring			clk2_out {
985724ba675SRob Herring				nvidia,pins = "clk2_out_pw5";
986724ba675SRob Herring				nvidia,function = "extperiph2";
987724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
989724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
990724ba675SRob Herring			};
991724ba675SRob Herring
992724ba675SRob Herring			clk3_out {
993724ba675SRob Herring				nvidia,pins = "clk3_out_pee0";
994724ba675SRob Herring				nvidia,function = "extperiph3";
995724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
996724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
997724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
998724ba675SRob Herring			};
999724ba675SRob Herring
1000724ba675SRob Herring			sys_clk_req {
1001724ba675SRob Herring				nvidia,pins = "sys_clk_req_pz5";
1002724ba675SRob Herring				nvidia,function = "sysclk";
1003724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006724ba675SRob Herring			};
1007724ba675SRob Herring
1008724ba675SRob Herring			pbb4 {
1009724ba675SRob Herring				nvidia,pins = "pbb4";
1010724ba675SRob Herring				nvidia,function = "vgp4";
1011724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1012724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1013724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1014724ba675SRob Herring			};
1015724ba675SRob Herring
1016724ba675SRob Herring			pbb5 {
1017724ba675SRob Herring				nvidia,pins = "pbb5";
1018724ba675SRob Herring				nvidia,function = "vgp5";
1019724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1020724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1021724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1022724ba675SRob Herring			};
1023724ba675SRob Herring
1024724ba675SRob Herring			pbb6 {
1025724ba675SRob Herring				nvidia,pins = "pbb6";
1026724ba675SRob Herring				nvidia,function = "vgp6";
1027724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1028724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1029724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1030724ba675SRob Herring			};
1031724ba675SRob Herring
1032724ba675SRob Herring			clk2_req_pcc5 {
1033724ba675SRob Herring				nvidia,pins = "clk2_req_pcc5",
1034724ba675SRob Herring						"clk1_req_pee2";
1035724ba675SRob Herring				nvidia,function = "dap";
1036724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1037724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1038724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1039724ba675SRob Herring			};
1040724ba675SRob Herring
1041724ba675SRob Herring			clk3_req_pee1 {
1042724ba675SRob Herring				nvidia,pins = "clk3_req_pee1";
1043724ba675SRob Herring				nvidia,function = "dev3";
1044724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1045724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1046724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047724ba675SRob Herring			};
1048724ba675SRob Herring
1049724ba675SRob Herring			owr {
1050724ba675SRob Herring				nvidia,pins = "owr";
1051724ba675SRob Herring				nvidia,function = "owr";
1052724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1053724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1054724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1055724ba675SRob Herring			};
1056724ba675SRob Herring
1057724ba675SRob Herring			/* GPIO power/drive control */
1058724ba675SRob Herring			drive_dap1 {
1059724ba675SRob Herring				nvidia,pins = "drive_dap1",
1060724ba675SRob Herring						"drive_dap2",
1061724ba675SRob Herring						"drive_dbg",
1062724ba675SRob Herring						"drive_at5",
1063724ba675SRob Herring						"drive_gme",
1064724ba675SRob Herring						"drive_ddc",
1065724ba675SRob Herring						"drive_ao1",
1066724ba675SRob Herring						"drive_uart3";
1067724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1068724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1069724ba675SRob Herring				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1070724ba675SRob Herring				nvidia,pull-down-strength = <31>;
1071724ba675SRob Herring				nvidia,pull-up-strength = <31>;
1072724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1073724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1074724ba675SRob Herring			};
1075724ba675SRob Herring
1076724ba675SRob Herring			drive_sdio1 {
1077724ba675SRob Herring				nvidia,pins = "drive_sdio1",
1078724ba675SRob Herring						"drive_sdio3";
1079724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1080724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1081724ba675SRob Herring				nvidia,pull-down-strength = <46>;
1082724ba675SRob Herring				nvidia,pull-up-strength = <42>;
1083724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1084724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1085724ba675SRob Herring			};
1086724ba675SRob Herring		};
1087724ba675SRob Herring	};
1088724ba675SRob Herring
1089724ba675SRob Herring	serial@70006040 {
1090724ba675SRob Herring		compatible = "nvidia,tegra30-hsuart";
1091*500b861dSThierry Reding		reset-names = "serial";
1092724ba675SRob Herring		/delete-property/ reg-shift;
1093724ba675SRob Herring		status = "okay";
1094724ba675SRob Herring
1095724ba675SRob Herring		/* Broadcom GPS BCM47511 */
1096724ba675SRob Herring	};
1097724ba675SRob Herring
1098724ba675SRob Herring	serial@70006200 {
1099724ba675SRob Herring		compatible = "nvidia,tegra30-hsuart";
1100*500b861dSThierry Reding		reset-names = "serial";
1101724ba675SRob Herring		/delete-property/ reg-shift;
1102724ba675SRob Herring		status = "okay";
1103724ba675SRob Herring
1104724ba675SRob Herring		nvidia,adjust-baud-rates = <0 9600 100>,
1105724ba675SRob Herring					   <9600 115200 200>,
1106724ba675SRob Herring					   <1000000 4000000 136>;
1107724ba675SRob Herring
1108724ba675SRob Herring		bluetooth {
1109724ba675SRob Herring			max-speed = <4000000>;
1110724ba675SRob Herring
1111724ba675SRob Herring			clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1112724ba675SRob Herring			clock-names = "txco";
1113724ba675SRob Herring
1114724ba675SRob Herring			interrupt-parent = <&gpio>;
1115724ba675SRob Herring			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
1116724ba675SRob Herring			interrupt-names = "host-wakeup";
1117724ba675SRob Herring
1118724ba675SRob Herring			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
1119724ba675SRob Herring			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
1120724ba675SRob Herring
1121724ba675SRob Herring			vbat-supply  = <&vdd_3v3_com>;
1122724ba675SRob Herring			vddio-supply = <&vdd_1v8_vio>;
1123724ba675SRob Herring		};
1124724ba675SRob Herring	};
1125724ba675SRob Herring
1126724ba675SRob Herring	pwm@7000a000 {
1127724ba675SRob Herring		status = "okay";
1128724ba675SRob Herring	};
1129724ba675SRob Herring
1130724ba675SRob Herring	lcd_ddc: i2c@7000c000 {
1131724ba675SRob Herring		status = "okay";
1132724ba675SRob Herring		clock-frequency = <100000>;
1133724ba675SRob Herring	};
1134724ba675SRob Herring
1135724ba675SRob Herring	i2c@7000c400 {
1136724ba675SRob Herring		status = "okay";
1137724ba675SRob Herring		clock-frequency = <400000>;
1138724ba675SRob Herring	};
1139724ba675SRob Herring
1140724ba675SRob Herring	i2c@7000c500 {
1141724ba675SRob Herring		status = "okay";
1142724ba675SRob Herring
1143724ba675SRob Herring		/* Aichi AMI306 digital compass */
1144724ba675SRob Herring		magnetometer@e {
1145724ba675SRob Herring			compatible = "asahi-kasei,ak8974";
1146724ba675SRob Herring			reg = <0x0e>;
1147724ba675SRob Herring
1148724ba675SRob Herring			avdd-supply = <&vdd_3v3_sys>;
1149724ba675SRob Herring			dvdd-supply = <&vdd_1v8_vio>;
1150724ba675SRob Herring		};
1151724ba675SRob Herring
1152724ba675SRob Herring		/* Dynaimage ambient light sensor */
1153724ba675SRob Herring		light-sensor@1c {
1154724ba675SRob Herring			compatible = "dynaimage,al3010";
1155724ba675SRob Herring			reg = <0x1c>;
1156724ba675SRob Herring
1157724ba675SRob Herring			interrupt-parent = <&gpio>;
1158724ba675SRob Herring			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
1159724ba675SRob Herring
1160724ba675SRob Herring			vdd-supply = <&vdd_3v3_sys>;
1161724ba675SRob Herring		};
1162724ba675SRob Herring
1163724ba675SRob Herring		gyroscope@68 {
1164724ba675SRob Herring			compatible = "invensense,mpu3050";
1165724ba675SRob Herring			reg = <0x68>;
1166724ba675SRob Herring
1167724ba675SRob Herring			interrupt-parent = <&gpio>;
1168724ba675SRob Herring			interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1169724ba675SRob Herring
1170724ba675SRob Herring			vdd-supply    = <&vdd_3v3_sys>;
1171724ba675SRob Herring			vlogic-supply = <&vdd_1v8_vio>;
1172724ba675SRob Herring
1173724ba675SRob Herring			i2c-gate {
1174724ba675SRob Herring				#address-cells = <1>;
1175724ba675SRob Herring				#size-cells = <0>;
1176724ba675SRob Herring
1177724ba675SRob Herring				accelerometer@f {
1178724ba675SRob Herring					compatible = "kionix,kxtf9";
1179724ba675SRob Herring					reg = <0x0f>;
1180724ba675SRob Herring
1181724ba675SRob Herring					interrupt-parent = <&gpio>;
1182724ba675SRob Herring					interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1183724ba675SRob Herring
1184724ba675SRob Herring					vdd-supply = <&vdd_1v8_vio>;
1185724ba675SRob Herring					vddio-supply = <&vdd_1v8_vio>;
1186724ba675SRob Herring				};
1187724ba675SRob Herring			};
1188724ba675SRob Herring		};
1189724ba675SRob Herring	};
1190724ba675SRob Herring
1191724ba675SRob Herring	hdmi_ddc: i2c@7000c700 {
1192724ba675SRob Herring		status = "okay";
1193724ba675SRob Herring		clock-frequency = <93750>;
1194724ba675SRob Herring	};
1195724ba675SRob Herring
1196724ba675SRob Herring	i2c@7000d000 {
1197724ba675SRob Herring		status = "okay";
1198724ba675SRob Herring		clock-frequency = <400000>;
1199724ba675SRob Herring
1200724ba675SRob Herring		/* Texas Instruments TPS659110 PMIC */
1201724ba675SRob Herring		pmic: pmic@2d {
1202724ba675SRob Herring			compatible = "ti,tps65911";
1203724ba675SRob Herring			reg = <0x2d>;
1204724ba675SRob Herring
1205724ba675SRob Herring			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1206724ba675SRob Herring			#interrupt-cells = <2>;
1207724ba675SRob Herring			interrupt-controller;
1208724ba675SRob Herring			wakeup-source;
1209724ba675SRob Herring
1210724ba675SRob Herring			ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1211724ba675SRob Herring			ti,system-power-controller;
1212724ba675SRob Herring			ti,sleep-keep-ck32k;
1213724ba675SRob Herring			ti,sleep-enable;
1214724ba675SRob Herring
1215724ba675SRob Herring			#gpio-cells = <2>;
1216724ba675SRob Herring			gpio-controller;
1217724ba675SRob Herring
1218724ba675SRob Herring			vcc1-supply = <&vdd_5v0_bat>;
1219724ba675SRob Herring			vcc2-supply = <&vdd_5v0_bat>;
1220724ba675SRob Herring			vcc3-supply = <&vdd_1v8_vio>;
1221724ba675SRob Herring			vcc4-supply = <&vdd_5v0_sys>;
1222724ba675SRob Herring			vcc5-supply = <&vdd_5v0_bat>;
1223724ba675SRob Herring			vcc6-supply = <&vdd_3v3_sys>;
1224724ba675SRob Herring			vcc7-supply = <&vdd_5v0_bat>;
1225724ba675SRob Herring			vccio-supply = <&vdd_5v0_bat>;
1226724ba675SRob Herring
1227724ba675SRob Herring			pmic-sleep-hog {
1228724ba675SRob Herring				gpio-hog;
1229724ba675SRob Herring				gpios = <2 GPIO_ACTIVE_HIGH>;
1230724ba675SRob Herring				output-high;
1231724ba675SRob Herring			};
1232724ba675SRob Herring
1233724ba675SRob Herring			regulators {
1234724ba675SRob Herring				/* VDD1 is not used by Transformers */
1235724ba675SRob Herring
1236724ba675SRob Herring				vddio_ddr: vdd2 {
1237724ba675SRob Herring					regulator-name = "vddio_ddr";
1238724ba675SRob Herring					regulator-min-microvolt = <1200000>;
1239724ba675SRob Herring					regulator-max-microvolt = <1200000>;
1240724ba675SRob Herring					regulator-always-on;
1241724ba675SRob Herring					regulator-boot-on;
1242724ba675SRob Herring				};
1243724ba675SRob Herring
1244724ba675SRob Herring				vdd_cpu: vddctrl {
1245724ba675SRob Herring					regulator-name = "vdd_cpu,vdd_sys";
1246724ba675SRob Herring					regulator-min-microvolt = <600000>;
1247724ba675SRob Herring					regulator-max-microvolt = <1400000>;
1248724ba675SRob Herring					regulator-coupled-with = <&vdd_core>;
1249724ba675SRob Herring					regulator-coupled-max-spread = <300000>;
1250724ba675SRob Herring					regulator-max-step-microvolt = <100000>;
1251724ba675SRob Herring					regulator-always-on;
1252724ba675SRob Herring					regulator-boot-on;
1253724ba675SRob Herring					ti,regulator-ext-sleep-control = <1>;
1254724ba675SRob Herring
1255724ba675SRob Herring					nvidia,tegra-cpu-regulator;
1256724ba675SRob Herring				};
1257724ba675SRob Herring
1258724ba675SRob Herring				vdd_1v8_vio: vio {
1259724ba675SRob Herring					regulator-name = "vdd_1v8_gen";
1260724ba675SRob Herring					/* FIXME: eMMC won't work, if set to 1.8 V */
1261724ba675SRob Herring					regulator-min-microvolt = <1500000>;
1262724ba675SRob Herring					regulator-max-microvolt = <3300000>;
1263724ba675SRob Herring					regulator-always-on;
1264724ba675SRob Herring					regulator-boot-on;
1265724ba675SRob Herring				};
1266724ba675SRob Herring
1267724ba675SRob Herring				/* eMMC VDD */
1268724ba675SRob Herring				vcore_emmc: ldo1 {
1269724ba675SRob Herring					regulator-name = "vdd_emmc_core";
1270724ba675SRob Herring					regulator-min-microvolt = <3300000>;
1271724ba675SRob Herring					regulator-max-microvolt = <3300000>;
1272724ba675SRob Herring					regulator-always-on;
1273724ba675SRob Herring				};
1274724ba675SRob Herring
1275724ba675SRob Herring				/* uSD slot VDD */
1276724ba675SRob Herring				vdd_usd: ldo2 {
1277724ba675SRob Herring					regulator-name = "vdd_usd";
1278724ba675SRob Herring					regulator-min-microvolt = <3100000>;
1279724ba675SRob Herring					regulator-max-microvolt = <3100000>;
1280724ba675SRob Herring					/* FIXME: Without this, voltage switching fails */
1281724ba675SRob Herring					regulator-always-on;
1282724ba675SRob Herring				};
1283724ba675SRob Herring
1284724ba675SRob Herring				/* uSD slot VDDIO */
1285724ba675SRob Herring				vddio_usd: ldo3 {
1286724ba675SRob Herring					regulator-name = "vddio_usd";
1287724ba675SRob Herring					regulator-min-microvolt = <1800000>;
1288724ba675SRob Herring					regulator-max-microvolt = <3100000>;
1289724ba675SRob Herring				};
1290724ba675SRob Herring
1291724ba675SRob Herring				ldo4 {
1292724ba675SRob Herring					regulator-name = "vdd_rtc";
1293724ba675SRob Herring					regulator-min-microvolt = <1200000>;
1294724ba675SRob Herring					regulator-max-microvolt = <1200000>;
1295724ba675SRob Herring					regulator-always-on;
1296724ba675SRob Herring				};
1297724ba675SRob Herring
1298724ba675SRob Herring				/* LDO5 is not used by Transformers */
1299724ba675SRob Herring
1300724ba675SRob Herring				ldo6 {
1301724ba675SRob Herring					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1302724ba675SRob Herring					regulator-min-microvolt = <1200000>;
1303724ba675SRob Herring					regulator-max-microvolt = <1200000>;
1304724ba675SRob Herring				};
1305724ba675SRob Herring
1306724ba675SRob Herring				ldo7 {
1307724ba675SRob Herring					regulator-name = "vdd_pllm,x,u,a_p_c_s";
1308724ba675SRob Herring					regulator-min-microvolt = <1200000>;
1309724ba675SRob Herring					regulator-max-microvolt = <1200000>;
1310724ba675SRob Herring					regulator-always-on;
1311724ba675SRob Herring					regulator-boot-on;
1312724ba675SRob Herring					ti,regulator-ext-sleep-control = <8>;
1313724ba675SRob Herring				};
1314724ba675SRob Herring
1315724ba675SRob Herring				ldo8 {
1316724ba675SRob Herring					regulator-name = "vdd_ddr_hs";
1317724ba675SRob Herring					regulator-min-microvolt = <1000000>;
1318724ba675SRob Herring					regulator-max-microvolt = <1000000>;
1319724ba675SRob Herring					regulator-always-on;
1320724ba675SRob Herring					ti,regulator-ext-sleep-control = <8>;
1321724ba675SRob Herring				};
1322724ba675SRob Herring			};
1323724ba675SRob Herring		};
1324724ba675SRob Herring
1325724ba675SRob Herring		nct72: temperature-sensor@4c {
1326724ba675SRob Herring			compatible = "onnn,nct1008";
1327724ba675SRob Herring			reg = <0x4c>;
1328724ba675SRob Herring
1329724ba675SRob Herring			interrupt-parent = <&gpio>;
1330724ba675SRob Herring			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1331724ba675SRob Herring
1332724ba675SRob Herring			vcc-supply = <&vdd_3v3_sys>;
1333724ba675SRob Herring			#thermal-sensor-cells = <1>;
1334724ba675SRob Herring		};
1335724ba675SRob Herring
1336724ba675SRob Herring		vdd_core: core-regulator@60 {
1337724ba675SRob Herring			compatible = "ti,tps62361";
1338724ba675SRob Herring			reg = <0x60>;
1339724ba675SRob Herring
1340724ba675SRob Herring			regulator-name = "tps62361-vout";
1341724ba675SRob Herring			regulator-min-microvolt = <500000>;
1342724ba675SRob Herring			regulator-max-microvolt = <1770000>;
1343724ba675SRob Herring			regulator-coupled-with = <&vdd_cpu>;
1344724ba675SRob Herring			regulator-coupled-max-spread = <300000>;
1345724ba675SRob Herring			regulator-max-step-microvolt = <100000>;
1346724ba675SRob Herring			regulator-boot-on;
1347724ba675SRob Herring			regulator-always-on;
1348724ba675SRob Herring			ti,enable-vout-discharge;
1349724ba675SRob Herring			ti,vsel0-state-high;
1350724ba675SRob Herring			ti,vsel1-state-high;
1351724ba675SRob Herring
1352724ba675SRob Herring			nvidia,tegra-core-regulator;
1353724ba675SRob Herring		};
1354724ba675SRob Herring	};
1355724ba675SRob Herring
1356724ba675SRob Herring	pmc@7000e400 {
1357724ba675SRob Herring		status = "okay";
1358724ba675SRob Herring		nvidia,invert-interrupt;
1359724ba675SRob Herring		/* FIXME: LP1 doesn't work at the moment */
1360724ba675SRob Herring		nvidia,suspend-mode = <2>;
1361724ba675SRob Herring		nvidia,cpu-pwr-good-time = <2000>;
1362724ba675SRob Herring		nvidia,cpu-pwr-off-time = <200>;
1363724ba675SRob Herring		nvidia,core-pwr-good-time = <3845 3845>;
1364724ba675SRob Herring		nvidia,core-pwr-off-time = <0>;
1365724ba675SRob Herring		nvidia,core-power-req-active-high;
1366724ba675SRob Herring		nvidia,sys-clock-req-active-high;
1367724ba675SRob Herring		core-supply = <&vdd_core>;
1368724ba675SRob Herring
1369724ba675SRob Herring		/* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC  */
1370724ba675SRob Herring		i2c-thermtrip {
1371724ba675SRob Herring			nvidia,i2c-controller-id = <4>;
1372724ba675SRob Herring			nvidia,bus-addr = <0x2d>;
1373724ba675SRob Herring			nvidia,reg-addr = <0x3f>;
1374724ba675SRob Herring			nvidia,reg-data = <0x81>;
1375724ba675SRob Herring		};
1376724ba675SRob Herring	};
1377724ba675SRob Herring
1378724ba675SRob Herring	hda@70030000 {
1379724ba675SRob Herring		status = "okay";
1380724ba675SRob Herring	};
1381724ba675SRob Herring
1382724ba675SRob Herring	ahub@70080000 {
1383724ba675SRob Herring		i2s@70080400 {		/* i2s1 */
1384724ba675SRob Herring			status = "okay";
1385724ba675SRob Herring		};
1386724ba675SRob Herring
1387724ba675SRob Herring		/* BT SCO */
1388724ba675SRob Herring		i2s@70080600 {		/* i2s3 */
1389724ba675SRob Herring			status = "okay";
1390724ba675SRob Herring		};
1391724ba675SRob Herring	};
1392724ba675SRob Herring
1393724ba675SRob Herring	mmc@78000000 {
1394724ba675SRob Herring		status = "okay";
1395724ba675SRob Herring
1396724ba675SRob Herring		/* FIXME: Full 208Mhz clock rate doesn't work reliably */
1397724ba675SRob Herring		max-frequency = <104000000>;
1398724ba675SRob Herring
1399724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1400724ba675SRob Herring		bus-width = <4>;
1401724ba675SRob Herring
1402724ba675SRob Herring		vmmc-supply = <&vdd_usd>;	/* ldo2 */
1403724ba675SRob Herring		vqmmc-supply = <&vddio_usd>;	/* ldo3 */
1404724ba675SRob Herring	};
1405724ba675SRob Herring
1406724ba675SRob Herring	mmc@78000400 {
1407724ba675SRob Herring		status = "okay";
1408724ba675SRob Herring
1409724ba675SRob Herring		#address-cells = <1>;
1410724ba675SRob Herring		#size-cells = <0>;
1411724ba675SRob Herring
1412724ba675SRob Herring		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1413724ba675SRob Herring		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1414724ba675SRob Herring		assigned-clock-rates = <50000000>;
1415724ba675SRob Herring
1416724ba675SRob Herring		max-frequency = <50000000>;
1417724ba675SRob Herring		keep-power-in-suspend;
1418724ba675SRob Herring		bus-width = <4>;
1419724ba675SRob Herring		non-removable;
1420724ba675SRob Herring
1421724ba675SRob Herring		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1422724ba675SRob Herring		vmmc-supply = <&vdd_3v3_com>;
1423724ba675SRob Herring		vqmmc-supply = <&vdd_1v8_vio>;
1424724ba675SRob Herring
1425724ba675SRob Herring		/* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
1426724ba675SRob Herring		wifi@1 {
1427724ba675SRob Herring			compatible = "brcm,bcm4329-fmac";
1428724ba675SRob Herring			reg = <1>;
1429724ba675SRob Herring
1430724ba675SRob Herring			interrupt-parent = <&gpio>;
1431724ba675SRob Herring			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1432724ba675SRob Herring			interrupt-names = "host-wake";
1433724ba675SRob Herring		};
1434724ba675SRob Herring	};
1435724ba675SRob Herring
1436724ba675SRob Herring	mmc@78000600 {
1437724ba675SRob Herring		status = "okay";
1438724ba675SRob Herring		bus-width = <8>;
1439724ba675SRob Herring		vmmc-supply = <&vcore_emmc>;
1440724ba675SRob Herring		vqmmc-supply = <&vdd_1v8_vio>;
1441724ba675SRob Herring		mmc-ddr-3_3v;
1442724ba675SRob Herring		non-removable;
1443724ba675SRob Herring	};
1444724ba675SRob Herring
1445724ba675SRob Herring	/* USB via ASUS connector */
1446724ba675SRob Herring	usb@7d000000 {
1447724ba675SRob Herring		compatible = "nvidia,tegra30-udc";
1448724ba675SRob Herring		status = "okay";
1449724ba675SRob Herring		dr_mode = "peripheral";
1450724ba675SRob Herring	};
1451724ba675SRob Herring
1452724ba675SRob Herring	usb-phy@7d000000 {
1453724ba675SRob Herring		status = "okay";
1454724ba675SRob Herring		dr_mode = "peripheral";
1455724ba675SRob Herring		nvidia,hssync-start-delay = <0>;
1456724ba675SRob Herring		nvidia,xcvr-lsfslew = <2>;
1457724ba675SRob Herring		nvidia,xcvr-lsrslew = <2>;
1458724ba675SRob Herring		vbus-supply = <&vdd_5v0_sys>;
1459724ba675SRob Herring	};
1460724ba675SRob Herring
1461724ba675SRob Herring	/* Dock's USB port */
1462724ba675SRob Herring	usb@7d008000 {
1463724ba675SRob Herring		status = "okay";
1464724ba675SRob Herring	};
1465724ba675SRob Herring
1466724ba675SRob Herring	usb-phy@7d008000 {
1467724ba675SRob Herring		status = "okay";
1468724ba675SRob Herring		vbus-supply = <&vdd_5v0_bat>;
1469724ba675SRob Herring	};
1470724ba675SRob Herring
1471724ba675SRob Herring	mains: ac-adapter-detect {
1472724ba675SRob Herring		compatible = "gpio-charger";
1473724ba675SRob Herring		charger-type = "mains";
1474724ba675SRob Herring		gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1475724ba675SRob Herring	};
1476724ba675SRob Herring
1477724ba675SRob Herring	backlight: backlight {
1478724ba675SRob Herring		compatible = "pwm-backlight";
1479724ba675SRob Herring
1480724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1481724ba675SRob Herring		power-supply = <&vdd_5v0_bl>;
1482724ba675SRob Herring		pwms = <&pwm 0 4000000>;
1483724ba675SRob Herring
1484724ba675SRob Herring		brightness-levels = <1 255>;
1485724ba675SRob Herring		num-interpolated-steps = <254>;
1486724ba675SRob Herring		default-brightness-level = <40>;
1487724ba675SRob Herring	};
1488724ba675SRob Herring
1489724ba675SRob Herring	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1490724ba675SRob Herring	clk32k_in: clock-32k {
1491724ba675SRob Herring		compatible = "fixed-clock";
1492724ba675SRob Herring		#clock-cells = <0>;
1493724ba675SRob Herring		clock-frequency = <32768>;
1494724ba675SRob Herring		clock-output-names = "pmic-oscillator";
1495724ba675SRob Herring	};
1496724ba675SRob Herring
1497724ba675SRob Herring	cpus {
1498724ba675SRob Herring		cpu0: cpu@0 {
1499724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
1500724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
1501724ba675SRob Herring			#cooling-cells = <2>;
1502724ba675SRob Herring		};
1503724ba675SRob Herring		cpu1: cpu@1 {
1504724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
1505724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
1506724ba675SRob Herring			#cooling-cells = <2>;
1507724ba675SRob Herring		};
1508724ba675SRob Herring		cpu2: cpu@2 {
1509724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
1510724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
1511724ba675SRob Herring			#cooling-cells = <2>;
1512724ba675SRob Herring		};
1513724ba675SRob Herring		cpu3: cpu@3 {
1514724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
1515724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
1516724ba675SRob Herring			#cooling-cells = <2>;
1517724ba675SRob Herring		};
1518724ba675SRob Herring	};
1519724ba675SRob Herring
1520724ba675SRob Herring	extcon-keys {
1521724ba675SRob Herring		compatible = "gpio-keys";
1522724ba675SRob Herring
1523724ba675SRob Herring		switch-dock-hall-sensor {
1524724ba675SRob Herring			label = "Lid sensor";
1525724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1526724ba675SRob Herring			linux,input-type = <EV_SW>;
1527724ba675SRob Herring			linux,code = <SW_LID>;
1528724ba675SRob Herring			debounce-interval = <500>;
1529724ba675SRob Herring			wakeup-event-action = <EV_ACT_ASSERTED>;
1530724ba675SRob Herring			wakeup-source;
1531724ba675SRob Herring		};
1532724ba675SRob Herring
1533724ba675SRob Herring		switch-lineout-detect {
1534724ba675SRob Herring			label = "Audio dock line-out detect";
1535724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
1536724ba675SRob Herring			linux,input-type = <EV_SW>;
1537724ba675SRob Herring			linux,code = <SW_LINEOUT_INSERT>;
1538724ba675SRob Herring			debounce-interval = <10>;
1539724ba675SRob Herring			wakeup-event-action = <EV_ACT_ASSERTED>;
1540724ba675SRob Herring			wakeup-source;
1541724ba675SRob Herring		};
1542724ba675SRob Herring	};
1543724ba675SRob Herring
1544724ba675SRob Herring	gpio-keys {
1545724ba675SRob Herring		compatible = "gpio-keys";
1546724ba675SRob Herring
1547724ba675SRob Herring		key-power {
1548724ba675SRob Herring			label = "Power";
1549724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1550724ba675SRob Herring			linux,code = <KEY_POWER>;
1551724ba675SRob Herring			debounce-interval = <10>;
1552724ba675SRob Herring			wakeup-event-action = <EV_ACT_ASSERTED>;
1553724ba675SRob Herring			wakeup-source;
1554724ba675SRob Herring		};
1555724ba675SRob Herring
1556724ba675SRob Herring		key-volume-down {
1557724ba675SRob Herring			label = "Volume Down";
1558724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1559724ba675SRob Herring			linux,code = <KEY_VOLUMEDOWN>;
1560724ba675SRob Herring			debounce-interval = <10>;
1561724ba675SRob Herring			wakeup-event-action = <EV_ACT_ASSERTED>;
1562724ba675SRob Herring			wakeup-source;
1563724ba675SRob Herring		};
1564724ba675SRob Herring
1565724ba675SRob Herring		key-volume-up {
1566724ba675SRob Herring			label = "Volume Up";
1567724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1568724ba675SRob Herring			linux,code = <KEY_VOLUMEUP>;
1569724ba675SRob Herring			debounce-interval = <10>;
1570724ba675SRob Herring			wakeup-event-action = <EV_ACT_ASSERTED>;
1571724ba675SRob Herring			wakeup-source;
1572724ba675SRob Herring		};
1573724ba675SRob Herring	};
1574724ba675SRob Herring
1575724ba675SRob Herring	vdd_5v0_bat: regulator-bat {
1576724ba675SRob Herring		compatible = "regulator-fixed";
1577724ba675SRob Herring		regulator-name = "vdd_ac_bat";
1578724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1579724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1580724ba675SRob Herring		regulator-always-on;
1581724ba675SRob Herring		regulator-boot-on;
1582724ba675SRob Herring	};
1583724ba675SRob Herring
1584724ba675SRob Herring	vdd_5v0_cp: regulator-sby {
1585724ba675SRob Herring		compatible = "regulator-fixed";
1586724ba675SRob Herring		regulator-name = "vdd_5v0_sby";
1587724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1588724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1589724ba675SRob Herring		regulator-always-on;
1590724ba675SRob Herring		regulator-boot-on;
1591724ba675SRob Herring		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1592724ba675SRob Herring		enable-active-high;
1593724ba675SRob Herring		vin-supply = <&vdd_5v0_bat>;
1594724ba675SRob Herring	};
1595724ba675SRob Herring
1596724ba675SRob Herring	vdd_5v0_sys: regulator-5v {
1597724ba675SRob Herring		compatible = "regulator-fixed";
1598724ba675SRob Herring		regulator-name = "vdd_5v0_sys";
1599724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1600724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1601724ba675SRob Herring		regulator-always-on;
1602724ba675SRob Herring		regulator-boot-on;
1603724ba675SRob Herring		gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1604724ba675SRob Herring		enable-active-high;
1605724ba675SRob Herring		vin-supply = <&vdd_5v0_bat>;
1606724ba675SRob Herring	};
1607724ba675SRob Herring
1608724ba675SRob Herring	vdd_1v5_ddr: regulator-ddr {
1609724ba675SRob Herring		compatible = "regulator-fixed";
1610724ba675SRob Herring		regulator-name = "vdd_ddr";
1611724ba675SRob Herring		regulator-min-microvolt = <1500000>;
1612724ba675SRob Herring		regulator-max-microvolt = <1500000>;
1613724ba675SRob Herring		regulator-always-on;
1614724ba675SRob Herring		regulator-boot-on;
1615724ba675SRob Herring		gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1616724ba675SRob Herring		enable-active-high;
1617724ba675SRob Herring		vin-supply = <&vdd_5v0_bat>;
1618724ba675SRob Herring	};
1619724ba675SRob Herring
1620724ba675SRob Herring	vdd_3v3_sys: regulator-3v {
1621724ba675SRob Herring		compatible = "regulator-fixed";
1622724ba675SRob Herring		regulator-name = "vdd_3v3_sys";
1623724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1624724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1625724ba675SRob Herring		regulator-always-on;
1626724ba675SRob Herring		regulator-boot-on;
1627724ba675SRob Herring		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1628724ba675SRob Herring		enable-active-high;
1629724ba675SRob Herring		vin-supply = <&vdd_5v0_bat>;
1630724ba675SRob Herring	};
1631724ba675SRob Herring
1632724ba675SRob Herring	vdd_pnl: regulator-panel {
1633724ba675SRob Herring		compatible = "regulator-fixed";
1634724ba675SRob Herring		regulator-name = "vdd_panel";
1635724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1636724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1637724ba675SRob Herring		regulator-enable-ramp-delay = <20000>;
1638724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1639724ba675SRob Herring		enable-active-high;
1640724ba675SRob Herring		vin-supply = <&vdd_3v3_sys>;
1641724ba675SRob Herring	};
1642724ba675SRob Herring
1643724ba675SRob Herring	vdd_3v3_com: regulator-com {
1644724ba675SRob Herring		compatible = "regulator-fixed";
1645724ba675SRob Herring		regulator-name = "vdd_3v3_com";
1646724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1647724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1648724ba675SRob Herring		regulator-always-on;
1649724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1650724ba675SRob Herring		enable-active-high;
1651724ba675SRob Herring		vin-supply = <&vdd_3v3_sys>;
1652724ba675SRob Herring	};
1653724ba675SRob Herring
1654724ba675SRob Herring	vdd_5v0_bl: regulator-bl {
1655724ba675SRob Herring		compatible = "regulator-fixed";
1656724ba675SRob Herring		regulator-name = "vdd_5v0_bl";
1657724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1658724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1659724ba675SRob Herring		regulator-boot-on;
1660724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1661724ba675SRob Herring		enable-active-high;
1662724ba675SRob Herring		vin-supply = <&vdd_5v0_bat>;
1663724ba675SRob Herring	};
1664724ba675SRob Herring
1665724ba675SRob Herring	hdmi_5v0_sys: regulator-hdmi {
1666724ba675SRob Herring		compatible = "regulator-fixed";
1667724ba675SRob Herring		regulator-name = "hdmi_5v0_sys";
1668724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1669724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1670724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1671724ba675SRob Herring		enable-active-high;
1672724ba675SRob Herring		vin-supply = <&vdd_5v0_sys>;
1673724ba675SRob Herring	};
1674724ba675SRob Herring
1675724ba675SRob Herring	sound {
1676724ba675SRob Herring		nvidia,i2s-controller = <&tegra_i2s1>;
1677724ba675SRob Herring
1678724ba675SRob Herring		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1679724ba675SRob Herring		nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
1680724ba675SRob Herring		nvidia,coupled-mic-hp-det;
1681724ba675SRob Herring
1682724ba675SRob Herring		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1683724ba675SRob Herring			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1684724ba675SRob Herring			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1685724ba675SRob Herring		clock-names = "pll_a", "pll_a_out0", "mclk";
1686724ba675SRob Herring
1687724ba675SRob Herring		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1688724ba675SRob Herring				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1689724ba675SRob Herring
1690724ba675SRob Herring		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1691724ba675SRob Herring					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1692724ba675SRob Herring	};
1693724ba675SRob Herring
1694724ba675SRob Herring	thermal-zones {
1695724ba675SRob Herring		/*
1696724ba675SRob Herring		 * NCT72 has two sensors:
1697724ba675SRob Herring		 *
1698724ba675SRob Herring		 *	0: internal that monitors ambient/skin temperature
1699724ba675SRob Herring		 *	1: external that is connected to the CPU's diode
1700724ba675SRob Herring		 *
1701724ba675SRob Herring		 * Ideally we should use userspace thermal governor,
1702724ba675SRob Herring		 * but it's a much more complex solution.  The "skin"
1703724ba675SRob Herring		 * zone exists as a simpler solution which prevents
1704724ba675SRob Herring		 * Transformers from getting too hot from a user's
1705724ba675SRob Herring		 * tactile perspective. The CPU zone is intended to
1706724ba675SRob Herring		 * protect silicon from damage.
1707724ba675SRob Herring		 */
1708724ba675SRob Herring
1709724ba675SRob Herring		skin-thermal {
1710724ba675SRob Herring			polling-delay-passive = <1000>; /* milliseconds */
1711724ba675SRob Herring			polling-delay = <5000>; /* milliseconds */
1712724ba675SRob Herring
1713724ba675SRob Herring			thermal-sensors = <&nct72 0>;
1714724ba675SRob Herring
1715724ba675SRob Herring			trips {
1716724ba675SRob Herring				trip0: skin-alert {
1717724ba675SRob Herring					/* throttle at 57C until temperature drops to 56.8C */
1718724ba675SRob Herring					temperature = <57000>;
1719724ba675SRob Herring					hysteresis = <200>;
1720724ba675SRob Herring					type = "passive";
1721724ba675SRob Herring				};
1722724ba675SRob Herring
1723724ba675SRob Herring				trip1: skin-crit {
1724724ba675SRob Herring					/* shut down at 65C */
1725724ba675SRob Herring					temperature = <65000>;
1726724ba675SRob Herring					hysteresis = <2000>;
1727724ba675SRob Herring					type = "critical";
1728724ba675SRob Herring				};
1729724ba675SRob Herring			};
1730724ba675SRob Herring
1731724ba675SRob Herring			cooling-maps {
1732724ba675SRob Herring				map0 {
1733724ba675SRob Herring					trip = <&trip0>;
1734724ba675SRob Herring					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735724ba675SRob Herring							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1736724ba675SRob Herring							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1737724ba675SRob Herring							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1738724ba675SRob Herring							 <&actmon THERMAL_NO_LIMIT
1739724ba675SRob Herring								  THERMAL_NO_LIMIT>;
1740724ba675SRob Herring				};
1741724ba675SRob Herring			};
1742724ba675SRob Herring		};
1743724ba675SRob Herring
1744724ba675SRob Herring		cpu-thermal {
1745724ba675SRob Herring			polling-delay-passive = <1000>; /* milliseconds */
1746724ba675SRob Herring			polling-delay = <5000>; /* milliseconds */
1747724ba675SRob Herring
1748724ba675SRob Herring			thermal-sensors = <&nct72 1>;
1749724ba675SRob Herring
1750724ba675SRob Herring			trips {
1751724ba675SRob Herring				trip2: cpu-alert {
1752724ba675SRob Herring					/* throttle at 75C until temperature drops to 74.8C */
1753724ba675SRob Herring					temperature = <75000>;
1754724ba675SRob Herring					hysteresis = <200>;
1755724ba675SRob Herring					type = "passive";
1756724ba675SRob Herring				};
1757724ba675SRob Herring
1758724ba675SRob Herring				trip3: cpu-crit {
1759724ba675SRob Herring					/* shut down at 90C */
1760724ba675SRob Herring					temperature = <90000>;
1761724ba675SRob Herring					hysteresis = <2000>;
1762724ba675SRob Herring					type = "critical";
1763724ba675SRob Herring				};
1764724ba675SRob Herring			};
1765724ba675SRob Herring
1766724ba675SRob Herring			cooling-maps {
1767724ba675SRob Herring				map1 {
1768724ba675SRob Herring					trip = <&trip2>;
1769724ba675SRob Herring					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770724ba675SRob Herring							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771724ba675SRob Herring							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1772724ba675SRob Herring							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1773724ba675SRob Herring							 <&actmon THERMAL_NO_LIMIT
1774724ba675SRob Herring								  THERMAL_NO_LIMIT>;
1775724ba675SRob Herring				};
1776724ba675SRob Herring			};
1777724ba675SRob Herring		};
1778724ba675SRob Herring	};
1779724ba675SRob Herring
1780724ba675SRob Herring	brcm_wifi_pwrseq: wifi-pwrseq {
1781724ba675SRob Herring		compatible = "mmc-pwrseq-simple";
1782724ba675SRob Herring
1783724ba675SRob Herring		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1784724ba675SRob Herring		clock-names = "ext_clock";
1785724ba675SRob Herring
1786724ba675SRob Herring		reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1787724ba675SRob Herring		post-power-on-delay-ms = <300>;
1788724ba675SRob Herring		power-off-delay-us = <300>;
1789724ba675SRob Herring	};
1790724ba675SRob Herring};
1791