xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra30-asus-tf600t.dts (revision 115e74a29b530d121891238e9551c4bcdf7b04b5)
1*8ae70af2SSvyatoslav Ryhel// SPDX-License-Identifier: GPL-2.0
2*8ae70af2SSvyatoslav Ryhel/dts-v1/;
3*8ae70af2SSvyatoslav Ryhel
4*8ae70af2SSvyatoslav Ryhel#include <dt-bindings/input/gpio-keys.h>
5*8ae70af2SSvyatoslav Ryhel#include <dt-bindings/input/input.h>
6*8ae70af2SSvyatoslav Ryhel#include <dt-bindings/leds/common.h>
7*8ae70af2SSvyatoslav Ryhel#include <dt-bindings/thermal/thermal.h>
8*8ae70af2SSvyatoslav Ryhel
9*8ae70af2SSvyatoslav Ryhel#include "tegra30.dtsi"
10*8ae70af2SSvyatoslav Ryhel#include "tegra30-cpu-opp.dtsi"
11*8ae70af2SSvyatoslav Ryhel#include "tegra30-cpu-opp-microvolt.dtsi"
12*8ae70af2SSvyatoslav Ryhel
13*8ae70af2SSvyatoslav Ryhel/ {
14*8ae70af2SSvyatoslav Ryhel	model = "Asus VivoTab RT TF600T";
15*8ae70af2SSvyatoslav Ryhel	compatible = "asus,tf600t", "nvidia,tegra30";
16*8ae70af2SSvyatoslav Ryhel	chassis-type = "convertible";
17*8ae70af2SSvyatoslav Ryhel
18*8ae70af2SSvyatoslav Ryhel	aliases {
19*8ae70af2SSvyatoslav Ryhel		mmc0 = &sdmmc4; /* eMMC */
20*8ae70af2SSvyatoslav Ryhel		mmc1 = &sdmmc1; /* uSD slot */
21*8ae70af2SSvyatoslav Ryhel		mmc2 = &sdmmc3; /* WiFi */
22*8ae70af2SSvyatoslav Ryhel
23*8ae70af2SSvyatoslav Ryhel		rtc0 = &pmic;
24*8ae70af2SSvyatoslav Ryhel		rtc1 = "/rtc@7000e000";
25*8ae70af2SSvyatoslav Ryhel
26*8ae70af2SSvyatoslav Ryhel		display1 = &hdmi;
27*8ae70af2SSvyatoslav Ryhel
28*8ae70af2SSvyatoslav Ryhel		serial1 = &uartc; /* Bluetooth */
29*8ae70af2SSvyatoslav Ryhel		serial2 = &uartb; /* GPS */
30*8ae70af2SSvyatoslav Ryhel	};
31*8ae70af2SSvyatoslav Ryhel
32*8ae70af2SSvyatoslav Ryhel	/*
33*8ae70af2SSvyatoslav Ryhel	 * The decompressor and also some bootloaders rely on a
34*8ae70af2SSvyatoslav Ryhel	 * pre-existing /chosen node to be available to insert the
35*8ae70af2SSvyatoslav Ryhel	 * command line and merge other ATAGS info.
36*8ae70af2SSvyatoslav Ryhel	 */
37*8ae70af2SSvyatoslav Ryhel	chosen {};
38*8ae70af2SSvyatoslav Ryhel
39*8ae70af2SSvyatoslav Ryhel	memory@80000000 {
40*8ae70af2SSvyatoslav Ryhel		reg = <0x80000000 0x80000000>;
41*8ae70af2SSvyatoslav Ryhel	};
42*8ae70af2SSvyatoslav Ryhel
43*8ae70af2SSvyatoslav Ryhel	reserved-memory {
44*8ae70af2SSvyatoslav Ryhel		#address-cells = <1>;
45*8ae70af2SSvyatoslav Ryhel		#size-cells = <1>;
46*8ae70af2SSvyatoslav Ryhel		ranges;
47*8ae70af2SSvyatoslav Ryhel
48*8ae70af2SSvyatoslav Ryhel		linux,cma@80000000 {
49*8ae70af2SSvyatoslav Ryhel			compatible = "shared-dma-pool";
50*8ae70af2SSvyatoslav Ryhel			alloc-ranges = <0x80000000 0x30000000>;
51*8ae70af2SSvyatoslav Ryhel			size = <0x10000000>;		/* 256MiB */
52*8ae70af2SSvyatoslav Ryhel			linux,cma-default;
53*8ae70af2SSvyatoslav Ryhel			reusable;
54*8ae70af2SSvyatoslav Ryhel		};
55*8ae70af2SSvyatoslav Ryhel	};
56*8ae70af2SSvyatoslav Ryhel
57*8ae70af2SSvyatoslav Ryhel	host1x@50000000 {
58*8ae70af2SSvyatoslav Ryhel		hdmi: hdmi@54280000 {
59*8ae70af2SSvyatoslav Ryhel			status = "okay";
60*8ae70af2SSvyatoslav Ryhel
61*8ae70af2SSvyatoslav Ryhel			hdmi-supply = <&hdmi_5v0_sys>;
62*8ae70af2SSvyatoslav Ryhel			pll-supply = <&vdd_1v8_vio>;
63*8ae70af2SSvyatoslav Ryhel			vdd-supply = <&vdd_3v3_sys>;
64*8ae70af2SSvyatoslav Ryhel
65*8ae70af2SSvyatoslav Ryhel			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
66*8ae70af2SSvyatoslav Ryhel			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
67*8ae70af2SSvyatoslav Ryhel		};
68*8ae70af2SSvyatoslav Ryhel	};
69*8ae70af2SSvyatoslav Ryhel
70*8ae70af2SSvyatoslav Ryhel	vde@6001a000 {
71*8ae70af2SSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
72*8ae70af2SSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
73*8ae70af2SSvyatoslav Ryhel		assigned-clock-rates = <408000000>;
74*8ae70af2SSvyatoslav Ryhel	};
75*8ae70af2SSvyatoslav Ryhel
76*8ae70af2SSvyatoslav Ryhel	pinmux@70000868 {
77*8ae70af2SSvyatoslav Ryhel		pinctrl-names = "default";
78*8ae70af2SSvyatoslav Ryhel		pinctrl-0 = <&state_default>;
79*8ae70af2SSvyatoslav Ryhel
80*8ae70af2SSvyatoslav Ryhel		state_default: pinmux {
81*8ae70af2SSvyatoslav Ryhel			/* SDMMC1 pinmux */
82*8ae70af2SSvyatoslav Ryhel			sdmmc1-clk {
83*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc1_clk_pz0";
84*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc1";
85*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
86*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
87*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
88*8ae70af2SSvyatoslav Ryhel			};
89*8ae70af2SSvyatoslav Ryhel			sdmmc1-cmd {
90*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc1_dat3_py4",
91*8ae70af2SSvyatoslav Ryhel					      "sdmmc1_dat2_py5",
92*8ae70af2SSvyatoslav Ryhel					      "sdmmc1_dat1_py6",
93*8ae70af2SSvyatoslav Ryhel					      "sdmmc1_dat0_py7",
94*8ae70af2SSvyatoslav Ryhel					      "sdmmc1_cmd_pz1";
95*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc1";
96*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
97*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
98*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
99*8ae70af2SSvyatoslav Ryhel			};
100*8ae70af2SSvyatoslav Ryhel			sdmmc1-cd {
101*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_iordy_pi5";
102*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
103*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
104*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
105*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
106*8ae70af2SSvyatoslav Ryhel			};
107*8ae70af2SSvyatoslav Ryhel			sdmmc1-wp {
108*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d11_pt3";
109*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
110*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
111*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
112*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
113*8ae70af2SSvyatoslav Ryhel			};
114*8ae70af2SSvyatoslav Ryhel
115*8ae70af2SSvyatoslav Ryhel			/* SDMMC2 pinmux */
116*8ae70af2SSvyatoslav Ryhel			vi-d1-pd5 {
117*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d1_pd5",
118*8ae70af2SSvyatoslav Ryhel					      "vi_d2_pl0",
119*8ae70af2SSvyatoslav Ryhel					      "vi_d3_pl1",
120*8ae70af2SSvyatoslav Ryhel					      "vi_d5_pl3",
121*8ae70af2SSvyatoslav Ryhel					      "vi_d7_pl5";
122*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc2";
123*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
125*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
126*8ae70af2SSvyatoslav Ryhel			};
127*8ae70af2SSvyatoslav Ryhel			vi-d8-pl6 {
128*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d8_pl6",
129*8ae70af2SSvyatoslav Ryhel					      "vi_d9_pl7";
130*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc2";
131*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
133*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
134*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <0>;
135*8ae70af2SSvyatoslav Ryhel				nvidia,io-reset = <0>;
136*8ae70af2SSvyatoslav Ryhel			};
137*8ae70af2SSvyatoslav Ryhel
138*8ae70af2SSvyatoslav Ryhel			/* SDMMC3 pinmux */
139*8ae70af2SSvyatoslav Ryhel			sdmmc3-clk {
140*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc3_clk_pa6";
141*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc3";
142*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
143*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
144*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
145*8ae70af2SSvyatoslav Ryhel			};
146*8ae70af2SSvyatoslav Ryhel			sdmmc3-cmd {
147*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc3_cmd_pa7",
148*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat0_pb7",
149*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat1_pb6",
150*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat2_pb5",
151*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat3_pb4",
152*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat4_pd1",
153*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat5_pd0",
154*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat6_pd3",
155*8ae70af2SSvyatoslav Ryhel					      "sdmmc3_dat7_pd4";
156*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc3";
157*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
158*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
159*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
160*8ae70af2SSvyatoslav Ryhel			};
161*8ae70af2SSvyatoslav Ryhel
162*8ae70af2SSvyatoslav Ryhel			/* SDMMC4 pinmux */
163*8ae70af2SSvyatoslav Ryhel			sdmmc4-clk {
164*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc4_clk_pcc4";
165*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc4";
166*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169*8ae70af2SSvyatoslav Ryhel			};
170*8ae70af2SSvyatoslav Ryhel			sdmmc4-cmd {
171*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc4_cmd_pt7",
172*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat0_paa0",
173*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat1_paa1",
174*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat2_paa2",
175*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat3_paa3",
176*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat4_paa4",
177*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat5_paa5",
178*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat6_paa6",
179*8ae70af2SSvyatoslav Ryhel					      "sdmmc4_dat7_paa7";
180*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sdmmc4";
181*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
182*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
183*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
184*8ae70af2SSvyatoslav Ryhel			};
185*8ae70af2SSvyatoslav Ryhel			sdmmc4-rst-n {
186*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sdmmc4_rst_n_pcc3";
187*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
188*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
189*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
190*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
191*8ae70af2SSvyatoslav Ryhel			};
192*8ae70af2SSvyatoslav Ryhel			cam-mclk {
193*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "cam_mclk_pcc0";
194*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vi_alt3";
195*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
196*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
197*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
198*8ae70af2SSvyatoslav Ryhel			};
199*8ae70af2SSvyatoslav Ryhel
200*8ae70af2SSvyatoslav Ryhel			/* I2C pinmux */
201*8ae70af2SSvyatoslav Ryhel			gen1-i2c {
202*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gen1_i2c_scl_pc4",
203*8ae70af2SSvyatoslav Ryhel					      "gen1_i2c_sda_pc5";
204*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2c1";
205*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
207*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208*8ae70af2SSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
209*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
210*8ae70af2SSvyatoslav Ryhel			};
211*8ae70af2SSvyatoslav Ryhel			gen2-i2c {
212*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gen2_i2c_scl_pt5",
213*8ae70af2SSvyatoslav Ryhel					      "gen2_i2c_sda_pt6";
214*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2c2";
215*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
217*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218*8ae70af2SSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
219*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
220*8ae70af2SSvyatoslav Ryhel			};
221*8ae70af2SSvyatoslav Ryhel			cam-i2c {
222*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "cam_i2c_scl_pbb1",
223*8ae70af2SSvyatoslav Ryhel					      "cam_i2c_sda_pbb2";
224*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2c3";
225*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
227*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228*8ae70af2SSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
229*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
230*8ae70af2SSvyatoslav Ryhel			};
231*8ae70af2SSvyatoslav Ryhel			ddc-i2c {
232*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ddc_scl_pv4",
233*8ae70af2SSvyatoslav Ryhel					      "ddc_sda_pv5";
234*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2c4";
235*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
239*8ae70af2SSvyatoslav Ryhel			};
240*8ae70af2SSvyatoslav Ryhel			pwr-i2c {
241*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pwr_i2c_scl_pz6",
242*8ae70af2SSvyatoslav Ryhel					      "pwr_i2c_sda_pz7";
243*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2cpwr";
244*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
246*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247*8ae70af2SSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
248*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
249*8ae70af2SSvyatoslav Ryhel			};
250*8ae70af2SSvyatoslav Ryhel			hotplug-i2c {
251*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu4";
252*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
253*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
254*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
255*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
256*8ae70af2SSvyatoslav Ryhel			};
257*8ae70af2SSvyatoslav Ryhel
258*8ae70af2SSvyatoslav Ryhel			/* HDMI pinmux */
259*8ae70af2SSvyatoslav Ryhel			hdmi-cec {
260*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "hdmi_cec_pee3";
261*8ae70af2SSvyatoslav Ryhel				nvidia,function = "cec";
262*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
264*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
265*8ae70af2SSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
266*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <TEGRA_PIN_DISABLE>;
267*8ae70af2SSvyatoslav Ryhel			};
268*8ae70af2SSvyatoslav Ryhel			hdmi-hpd {
269*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "hdmi_int_pn7";
270*8ae70af2SSvyatoslav Ryhel				nvidia,function = "hdmi";
271*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
272*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
273*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
274*8ae70af2SSvyatoslav Ryhel			};
275*8ae70af2SSvyatoslav Ryhel
276*8ae70af2SSvyatoslav Ryhel			/* UART-A */
277*8ae70af2SSvyatoslav Ryhel			ulpi-data0-po1 {
278*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_data0_po1";
279*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uarta";
280*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
281*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
282*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
283*8ae70af2SSvyatoslav Ryhel			};
284*8ae70af2SSvyatoslav Ryhel			ulpi-data1-po2 {
285*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_data1_po2";
286*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uarta";
287*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
288*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
289*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
290*8ae70af2SSvyatoslav Ryhel			};
291*8ae70af2SSvyatoslav Ryhel			ulpi-data5-po6 {
292*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_data5_po6";
293*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uarta";
294*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
296*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
297*8ae70af2SSvyatoslav Ryhel			};
298*8ae70af2SSvyatoslav Ryhel			ulpi-data7-po0 {
299*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_data7_po0",
300*8ae70af2SSvyatoslav Ryhel					      "ulpi_data2_po3",
301*8ae70af2SSvyatoslav Ryhel					      "ulpi_data3_po4",
302*8ae70af2SSvyatoslav Ryhel					      "ulpi_data4_po5",
303*8ae70af2SSvyatoslav Ryhel					      "ulpi_data6_po7";
304*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uarta";
305*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
307*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308*8ae70af2SSvyatoslav Ryhel			};
309*8ae70af2SSvyatoslav Ryhel
310*8ae70af2SSvyatoslav Ryhel			/* UART-B */
311*8ae70af2SSvyatoslav Ryhel			uartb-txd-rts {
312*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "uart2_txd_pc2",
313*8ae70af2SSvyatoslav Ryhel					      "uart2_rts_n_pj6";
314*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartb";
315*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
317*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
318*8ae70af2SSvyatoslav Ryhel			};
319*8ae70af2SSvyatoslav Ryhel			uartb-rxd-cts {
320*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "uart2_rxd_pc3",
321*8ae70af2SSvyatoslav Ryhel					      "uart2_cts_n_pj5";
322*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartb";
323*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
325*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326*8ae70af2SSvyatoslav Ryhel			};
327*8ae70af2SSvyatoslav Ryhel
328*8ae70af2SSvyatoslav Ryhel			/* UART-C */
329*8ae70af2SSvyatoslav Ryhel			uartc-rxd-cts {
330*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "uart3_cts_n_pa1",
331*8ae70af2SSvyatoslav Ryhel					      "uart3_rxd_pw7";
332*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartc";
333*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
335*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336*8ae70af2SSvyatoslav Ryhel			};
337*8ae70af2SSvyatoslav Ryhel			uartc-txd-rts {
338*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "uart3_rts_n_pc0",
339*8ae70af2SSvyatoslav Ryhel					      "uart3_txd_pw6";
340*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartc";
341*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
342*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
343*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
344*8ae70af2SSvyatoslav Ryhel			};
345*8ae70af2SSvyatoslav Ryhel
346*8ae70af2SSvyatoslav Ryhel			/* UART-D */
347*8ae70af2SSvyatoslav Ryhel			ulpi-nxt-py2 {
348*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_nxt_py2";
349*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartd";
350*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
351*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
352*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
353*8ae70af2SSvyatoslav Ryhel			};
354*8ae70af2SSvyatoslav Ryhel			ulpi-clk-py0 {
355*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "ulpi_clk_py0",
356*8ae70af2SSvyatoslav Ryhel					      "ulpi_dir_py1",
357*8ae70af2SSvyatoslav Ryhel					      "ulpi_stp_py3";
358*8ae70af2SSvyatoslav Ryhel				nvidia,function = "uartd";
359*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
361*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
362*8ae70af2SSvyatoslav Ryhel			};
363*8ae70af2SSvyatoslav Ryhel
364*8ae70af2SSvyatoslav Ryhel			/* I2S pinmux */
365*8ae70af2SSvyatoslav Ryhel			dap-i2s0 {
366*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap1_fs_pn0",
367*8ae70af2SSvyatoslav Ryhel					      "dap1_din_pn1",
368*8ae70af2SSvyatoslav Ryhel					      "dap1_dout_pn2",
369*8ae70af2SSvyatoslav Ryhel					      "dap1_sclk_pn3";
370*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s0";
371*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
372*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
373*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
374*8ae70af2SSvyatoslav Ryhel			};
375*8ae70af2SSvyatoslav Ryhel			dap-i2s1 {
376*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap2_fs_pa2",
377*8ae70af2SSvyatoslav Ryhel					      "dap2_sclk_pa3",
378*8ae70af2SSvyatoslav Ryhel					      "dap2_din_pa4",
379*8ae70af2SSvyatoslav Ryhel					      "dap2_dout_pa5";
380*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s1";
381*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
382*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
383*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
384*8ae70af2SSvyatoslav Ryhel			};
385*8ae70af2SSvyatoslav Ryhel			dap3-fs {
386*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap3_fs_pp0";
387*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s2";
388*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
389*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
390*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
391*8ae70af2SSvyatoslav Ryhel			};
392*8ae70af2SSvyatoslav Ryhel			dap3-din {
393*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap3_din_pp1";
394*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s2";
395*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
396*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
397*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
398*8ae70af2SSvyatoslav Ryhel			};
399*8ae70af2SSvyatoslav Ryhel			dap3-dout {
400*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap3_dout_pp2",
401*8ae70af2SSvyatoslav Ryhel					      "dap3_sclk_pp3";
402*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s2";
403*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
404*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
405*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
406*8ae70af2SSvyatoslav Ryhel			};
407*8ae70af2SSvyatoslav Ryhel			dap-i2s3 {
408*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "dap4_fs_pp4",
409*8ae70af2SSvyatoslav Ryhel					      "dap4_din_pp5",
410*8ae70af2SSvyatoslav Ryhel					      "dap4_dout_pp6",
411*8ae70af2SSvyatoslav Ryhel					      "dap4_sclk_pp7";
412*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s3";
413*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
415*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416*8ae70af2SSvyatoslav Ryhel			};
417*8ae70af2SSvyatoslav Ryhel			i2s4 {
418*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pbb7";
419*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s4";
420*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
422*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423*8ae70af2SSvyatoslav Ryhel			};
424*8ae70af2SSvyatoslav Ryhel
425*8ae70af2SSvyatoslav Ryhel			/* Sensors pinmux */
426*8ae70af2SSvyatoslav Ryhel			nct-irq {
427*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pcc2";
428*8ae70af2SSvyatoslav Ryhel				nvidia,function = "i2s4";
429*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
430*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
431*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
432*8ae70af2SSvyatoslav Ryhel			};
433*8ae70af2SSvyatoslav Ryhel			hall {
434*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pbb6";
435*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vgp6";
436*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
437*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
438*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
439*8ae70af2SSvyatoslav Ryhel			};
440*8ae70af2SSvyatoslav Ryhel
441*8ae70af2SSvyatoslav Ryhel			/* Asus EC pinmux */
442*8ae70af2SSvyatoslav Ryhel			ec-irqs {
443*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_row10_ps2",
444*8ae70af2SSvyatoslav Ryhel					      "kb_row15_ps7";
445*8ae70af2SSvyatoslav Ryhel				nvidia,function = "kbc";
446*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
447*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
448*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449*8ae70af2SSvyatoslav Ryhel			};
450*8ae70af2SSvyatoslav Ryhel			ec-reqs {
451*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_col1_pq1";
452*8ae70af2SSvyatoslav Ryhel				nvidia,function = "kbc";
453*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
454*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
455*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456*8ae70af2SSvyatoslav Ryhel			};
457*8ae70af2SSvyatoslav Ryhel
458*8ae70af2SSvyatoslav Ryhel			/* Memory type bootstrap */
459*8ae70af2SSvyatoslav Ryhel			mem-boostraps {
460*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad4_pg4",
461*8ae70af2SSvyatoslav Ryhel					      "gmi_ad5_pg5";
462*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
463*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
464*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
465*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466*8ae70af2SSvyatoslav Ryhel			};
467*8ae70af2SSvyatoslav Ryhel
468*8ae70af2SSvyatoslav Ryhel			/* PCI-e pinmux */
469*8ae70af2SSvyatoslav Ryhel			pex-l2-rst-n {
470*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pex_l2_rst_n_pcc6",
471*8ae70af2SSvyatoslav Ryhel					      "pex_l0_rst_n_pdd1",
472*8ae70af2SSvyatoslav Ryhel					      "pex_l1_rst_n_pdd5";
473*8ae70af2SSvyatoslav Ryhel				nvidia,function = "pcie";
474*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
475*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
476*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477*8ae70af2SSvyatoslav Ryhel			};
478*8ae70af2SSvyatoslav Ryhel			pex-l2-clkreq-n {
479*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pex_l2_clkreq_n_pcc7",
480*8ae70af2SSvyatoslav Ryhel					      "pex_l0_prsnt_n_pdd0",
481*8ae70af2SSvyatoslav Ryhel					      "pex_l0_clkreq_n_pdd2",
482*8ae70af2SSvyatoslav Ryhel					      "pex_wake_n_pdd3",
483*8ae70af2SSvyatoslav Ryhel					      "pex_l1_prsnt_n_pdd4",
484*8ae70af2SSvyatoslav Ryhel					      "pex_l1_clkreq_n_pdd6",
485*8ae70af2SSvyatoslav Ryhel					      "pex_l2_prsnt_n_pdd7";
486*8ae70af2SSvyatoslav Ryhel				nvidia,function = "pcie";
487*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
488*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
489*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
490*8ae70af2SSvyatoslav Ryhel			};
491*8ae70af2SSvyatoslav Ryhel
492*8ae70af2SSvyatoslav Ryhel			/* Display A pinmux */
493*8ae70af2SSvyatoslav Ryhel			lcd-pwr0-pb2 {
494*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "lcd_pwr0_pb2",
495*8ae70af2SSvyatoslav Ryhel					      "lcd_pclk_pb3",
496*8ae70af2SSvyatoslav Ryhel					      "lcd_pwr1_pc1",
497*8ae70af2SSvyatoslav Ryhel					      "lcd_d0_pe0",
498*8ae70af2SSvyatoslav Ryhel					      "lcd_d1_pe1",
499*8ae70af2SSvyatoslav Ryhel					      "lcd_d2_pe2",
500*8ae70af2SSvyatoslav Ryhel					      "lcd_d3_pe3",
501*8ae70af2SSvyatoslav Ryhel					      "lcd_d4_pe4",
502*8ae70af2SSvyatoslav Ryhel					      "lcd_d5_pe5",
503*8ae70af2SSvyatoslav Ryhel					      "lcd_d6_pe6",
504*8ae70af2SSvyatoslav Ryhel					      "lcd_d7_pe7",
505*8ae70af2SSvyatoslav Ryhel					      "lcd_d8_pf0",
506*8ae70af2SSvyatoslav Ryhel					      "lcd_d9_pf1",
507*8ae70af2SSvyatoslav Ryhel					      "lcd_d10_pf2",
508*8ae70af2SSvyatoslav Ryhel					      "lcd_d11_pf3",
509*8ae70af2SSvyatoslav Ryhel					      "lcd_d12_pf4",
510*8ae70af2SSvyatoslav Ryhel					      "lcd_d13_pf5",
511*8ae70af2SSvyatoslav Ryhel					      "lcd_d14_pf6",
512*8ae70af2SSvyatoslav Ryhel					      "lcd_d15_pf7",
513*8ae70af2SSvyatoslav Ryhel					      "lcd_de_pj1",
514*8ae70af2SSvyatoslav Ryhel					      "lcd_hsync_pj3",
515*8ae70af2SSvyatoslav Ryhel					      "lcd_vsync_pj4",
516*8ae70af2SSvyatoslav Ryhel					      "lcd_d16_pm0",
517*8ae70af2SSvyatoslav Ryhel					      "lcd_d17_pm1",
518*8ae70af2SSvyatoslav Ryhel					      "lcd_d18_pm2",
519*8ae70af2SSvyatoslav Ryhel					      "lcd_d19_pm3",
520*8ae70af2SSvyatoslav Ryhel					      "lcd_d20_pm4",
521*8ae70af2SSvyatoslav Ryhel					      "lcd_d21_pm5",
522*8ae70af2SSvyatoslav Ryhel					      "lcd_d22_pm6",
523*8ae70af2SSvyatoslav Ryhel					      "lcd_d23_pm7",
524*8ae70af2SSvyatoslav Ryhel					      "lcd_dc0_pn6",
525*8ae70af2SSvyatoslav Ryhel					      "lcd_sdin_pz2";
526*8ae70af2SSvyatoslav Ryhel				nvidia,function = "displaya";
527*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
528*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
529*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
530*8ae70af2SSvyatoslav Ryhel			};
531*8ae70af2SSvyatoslav Ryhel			lcd-cs0-n-pn4 {
532*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "lcd_sdout_pn5",
533*8ae70af2SSvyatoslav Ryhel					      "lcd_wr_n_pz3",
534*8ae70af2SSvyatoslav Ryhel					      "lcd_pwr2_pc6",
535*8ae70af2SSvyatoslav Ryhel					      "lcd_dc1_pd2";
536*8ae70af2SSvyatoslav Ryhel				nvidia,function = "displaya";
537*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
538*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
539*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
540*8ae70af2SSvyatoslav Ryhel			};
541*8ae70af2SSvyatoslav Ryhel
542*8ae70af2SSvyatoslav Ryhel			blink {
543*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk_32k_out_pa0";
544*8ae70af2SSvyatoslav Ryhel				nvidia,function = "blink";
545*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
547*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
548*8ae70af2SSvyatoslav Ryhel			};
549*8ae70af2SSvyatoslav Ryhel
550*8ae70af2SSvyatoslav Ryhel			/* KBC keys */
551*8ae70af2SSvyatoslav Ryhel			kb-col0 {
552*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_col0_pq0",
553*8ae70af2SSvyatoslav Ryhel					      "kb_row1_pr1",
554*8ae70af2SSvyatoslav Ryhel					      "kb_row3_pr3",
555*8ae70af2SSvyatoslav Ryhel					      "kb_row7_pr7",
556*8ae70af2SSvyatoslav Ryhel					      "kb_row8_ps0";
557*8ae70af2SSvyatoslav Ryhel				nvidia,function = "kbc";
558*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
559*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
560*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
561*8ae70af2SSvyatoslav Ryhel			};
562*8ae70af2SSvyatoslav Ryhel			kb-col5 {
563*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_col5_pq5",
564*8ae70af2SSvyatoslav Ryhel					      "kb_col7_pq7",
565*8ae70af2SSvyatoslav Ryhel					      "kb_row2_pr2",
566*8ae70af2SSvyatoslav Ryhel					      "kb_row4_pr4",
567*8ae70af2SSvyatoslav Ryhel					      "kb_row5_pr5",
568*8ae70af2SSvyatoslav Ryhel					      "kb_row13_ps5";
569*8ae70af2SSvyatoslav Ryhel				nvidia,function = "kbc";
570*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
571*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
572*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
573*8ae70af2SSvyatoslav Ryhel			};
574*8ae70af2SSvyatoslav Ryhel
575*8ae70af2SSvyatoslav Ryhel			gmi-cs0-n-pj0 {
576*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_wp_n_pc7",
577*8ae70af2SSvyatoslav Ryhel					      "gmi_wait_pi7",
578*8ae70af2SSvyatoslav Ryhel					      "gmi_cs0_n_pj0",
579*8ae70af2SSvyatoslav Ryhel					      "gmi_cs1_n_pj2",
580*8ae70af2SSvyatoslav Ryhel					      "gmi_cs2_n_pk3",
581*8ae70af2SSvyatoslav Ryhel					      "gmi_cs3_n_pk4";
582*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
583*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
585*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586*8ae70af2SSvyatoslav Ryhel			};
587*8ae70af2SSvyatoslav Ryhel
588*8ae70af2SSvyatoslav Ryhel			vi-pclk-pt0 {
589*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_pclk_pt0";
590*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
591*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
592*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
593*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
594*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <0>;
595*8ae70af2SSvyatoslav Ryhel				nvidia,io-reset = <0>;
596*8ae70af2SSvyatoslav Ryhel			};
597*8ae70af2SSvyatoslav Ryhel
598*8ae70af2SSvyatoslav Ryhel			/* GPIO keys pinmux */
599*8ae70af2SSvyatoslav Ryhel			power-key {
600*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pv0";
601*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
602*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
603*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
604*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
605*8ae70af2SSvyatoslav Ryhel			};
606*8ae70af2SSvyatoslav Ryhel			vol-keys {
607*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_col3_pq3",
608*8ae70af2SSvyatoslav Ryhel					      "kb_col4_pq4";
609*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
610*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
611*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
612*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
613*8ae70af2SSvyatoslav Ryhel			};
614*8ae70af2SSvyatoslav Ryhel
615*8ae70af2SSvyatoslav Ryhel			/* Bluetooth */
616*8ae70af2SSvyatoslav Ryhel			bt-shutdown {
617*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu0";
618*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
619*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
620*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
621*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
622*8ae70af2SSvyatoslav Ryhel			};
623*8ae70af2SSvyatoslav Ryhel			bt-dev-wake {
624*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu1";
625*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
626*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
627*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
628*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
629*8ae70af2SSvyatoslav Ryhel			};
630*8ae70af2SSvyatoslav Ryhel			bt-host-wake {
631*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu6";
632*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
633*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
634*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
635*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
636*8ae70af2SSvyatoslav Ryhel			};
637*8ae70af2SSvyatoslav Ryhel
638*8ae70af2SSvyatoslav Ryhel			pu2 {
639*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu2";
640*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd1";
641*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
642*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
643*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644*8ae70af2SSvyatoslav Ryhel			};
645*8ae70af2SSvyatoslav Ryhel			pu3 {
646*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu3";
647*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
648*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
650*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651*8ae70af2SSvyatoslav Ryhel			};
652*8ae70af2SSvyatoslav Ryhel			pcc1 {
653*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pcc1";
654*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
655*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
657*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
658*8ae70af2SSvyatoslav Ryhel			};
659*8ae70af2SSvyatoslav Ryhel			pv2 {
660*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pv2";
661*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
662*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
663*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
664*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
665*8ae70af2SSvyatoslav Ryhel			};
666*8ae70af2SSvyatoslav Ryhel			pv3 {
667*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pv3";
668*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
669*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
670*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
671*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
672*8ae70af2SSvyatoslav Ryhel			};
673*8ae70af2SSvyatoslav Ryhel
674*8ae70af2SSvyatoslav Ryhel			vi-vsync-pd6 {
675*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_vsync_pd6",
676*8ae70af2SSvyatoslav Ryhel					      "vi_hsync_pd7";
677*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
678*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
679*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
680*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
681*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <0>;
682*8ae70af2SSvyatoslav Ryhel				nvidia,io-reset = <0>;
683*8ae70af2SSvyatoslav Ryhel			};
684*8ae70af2SSvyatoslav Ryhel			vi-d10-pt2 {
685*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d10_pt2",
686*8ae70af2SSvyatoslav Ryhel					      "vi_d0_pt4",
687*8ae70af2SSvyatoslav Ryhel					      "pbb0";
688*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd2";
689*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
690*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
691*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
692*8ae70af2SSvyatoslav Ryhel			};
693*8ae70af2SSvyatoslav Ryhel			kb-row0-pr0 {
694*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "kb_row0_pr0";
695*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rsvd4";
696*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
697*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
698*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
699*8ae70af2SSvyatoslav Ryhel			};
700*8ae70af2SSvyatoslav Ryhel			gmi-ad0-pg0 {
701*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad0_pg0",
702*8ae70af2SSvyatoslav Ryhel					      "gmi_ad1_pg1",
703*8ae70af2SSvyatoslav Ryhel					      "gmi_ad2_pg2",
704*8ae70af2SSvyatoslav Ryhel					      "gmi_ad3_pg3",
705*8ae70af2SSvyatoslav Ryhel					      "gmi_ad6_pg6",
706*8ae70af2SSvyatoslav Ryhel					      "gmi_ad7_pg7",
707*8ae70af2SSvyatoslav Ryhel					      "gmi_wr_n_pi0",
708*8ae70af2SSvyatoslav Ryhel					      "gmi_oe_n_pi1",
709*8ae70af2SSvyatoslav Ryhel					      "gmi_dqs_pi2",
710*8ae70af2SSvyatoslav Ryhel					      "gmi_adv_n_pk0",
711*8ae70af2SSvyatoslav Ryhel					      "gmi_clk_pk1";
712*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
713*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
714*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
715*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
716*8ae70af2SSvyatoslav Ryhel			};
717*8ae70af2SSvyatoslav Ryhel			gmi-ad13-ph5 {
718*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad13_ph5";
719*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
720*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
721*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
722*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
723*8ae70af2SSvyatoslav Ryhel			};
724*8ae70af2SSvyatoslav Ryhel			gmi-ad10-ph2 {
725*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad10_ph2",
726*8ae70af2SSvyatoslav Ryhel					      "gmi_ad11_ph3",
727*8ae70af2SSvyatoslav Ryhel					      "gmi_ad14_ph6";
728*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
729*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
730*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
731*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
732*8ae70af2SSvyatoslav Ryhel			};
733*8ae70af2SSvyatoslav Ryhel			gmi-ad12-ph4 {
734*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad12_ph4",
735*8ae70af2SSvyatoslav Ryhel					      "gmi_rst_n_pi4",
736*8ae70af2SSvyatoslav Ryhel					      "gmi_cs7_n_pi6";
737*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
738*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
740*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741*8ae70af2SSvyatoslav Ryhel			};
742*8ae70af2SSvyatoslav Ryhel
743*8ae70af2SSvyatoslav Ryhel			/* Vibrator control */
744*8ae70af2SSvyatoslav Ryhel			vibrator {
745*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad11_ph3";
746*8ae70af2SSvyatoslav Ryhel				nvidia,function = "nand";
747*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
748*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
749*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
750*8ae70af2SSvyatoslav Ryhel			};
751*8ae70af2SSvyatoslav Ryhel
752*8ae70af2SSvyatoslav Ryhel			/* PWM pinmux */
753*8ae70af2SSvyatoslav Ryhel			pwm-0 {
754*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_ad8_ph0";
755*8ae70af2SSvyatoslav Ryhel				nvidia,function = "pwm0";
756*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
757*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
758*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
759*8ae70af2SSvyatoslav Ryhel			};
760*8ae70af2SSvyatoslav Ryhel			pwm-2 {
761*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pu5";
762*8ae70af2SSvyatoslav Ryhel				nvidia,function = "pwm2";
763*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
764*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
765*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766*8ae70af2SSvyatoslav Ryhel			};
767*8ae70af2SSvyatoslav Ryhel
768*8ae70af2SSvyatoslav Ryhel			gmi-cs-n {
769*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "gmi_cs4_n_pk2",
770*8ae70af2SSvyatoslav Ryhel					      "gmi_cs6_n_pi3";
771*8ae70af2SSvyatoslav Ryhel				nvidia,function = "gmi";
772*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
773*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
774*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
775*8ae70af2SSvyatoslav Ryhel			};
776*8ae70af2SSvyatoslav Ryhel
777*8ae70af2SSvyatoslav Ryhel			/* Spdif pinmux */
778*8ae70af2SSvyatoslav Ryhel			spdif-out {
779*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "spdif_out_pk5";
780*8ae70af2SSvyatoslav Ryhel				nvidia,function = "spdif";
781*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
782*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
783*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
784*8ae70af2SSvyatoslav Ryhel			};
785*8ae70af2SSvyatoslav Ryhel			spdif-in {
786*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "spdif_in_pk6";
787*8ae70af2SSvyatoslav Ryhel				nvidia,function = "spdif";
788*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
789*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
790*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
791*8ae70af2SSvyatoslav Ryhel			};
792*8ae70af2SSvyatoslav Ryhel
793*8ae70af2SSvyatoslav Ryhel			vi-d4-pl2 {
794*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d4_pl2";
795*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vi";
796*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
797*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
798*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
799*8ae70af2SSvyatoslav Ryhel			};
800*8ae70af2SSvyatoslav Ryhel			vi-d6-pl4 {
801*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_d6_pl4";
802*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vi";
803*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
805*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806*8ae70af2SSvyatoslav Ryhel				nvidia,lock = <0>;
807*8ae70af2SSvyatoslav Ryhel				nvidia,io-reset = <0>;
808*8ae70af2SSvyatoslav Ryhel			};
809*8ae70af2SSvyatoslav Ryhel			vi-mclk-pt1 {
810*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "vi_mclk_pt1";
811*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vi";
812*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
813*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
814*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815*8ae70af2SSvyatoslav Ryhel			};
816*8ae70af2SSvyatoslav Ryhel
817*8ae70af2SSvyatoslav Ryhel			jtag {
818*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "jtag_rtck_pu7";
819*8ae70af2SSvyatoslav Ryhel				nvidia,function = "rtck";
820*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
821*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
822*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
823*8ae70af2SSvyatoslav Ryhel			};
824*8ae70af2SSvyatoslav Ryhel
825*8ae70af2SSvyatoslav Ryhel			crt-sync {
826*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "crt_hsync_pv6",
827*8ae70af2SSvyatoslav Ryhel					      "crt_vsync_pv7";
828*8ae70af2SSvyatoslav Ryhel				nvidia,function = "crt";
829*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
830*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
831*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
832*8ae70af2SSvyatoslav Ryhel			};
833*8ae70af2SSvyatoslav Ryhel
834*8ae70af2SSvyatoslav Ryhel			clk1-out {
835*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk1_out_pw4";
836*8ae70af2SSvyatoslav Ryhel				nvidia,function = "extperiph1";
837*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
838*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
839*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
840*8ae70af2SSvyatoslav Ryhel			};
841*8ae70af2SSvyatoslav Ryhel			clk2-out {
842*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk2_out_pw5";
843*8ae70af2SSvyatoslav Ryhel				nvidia,function = "extperiph2";
844*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
845*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
846*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
847*8ae70af2SSvyatoslav Ryhel			};
848*8ae70af2SSvyatoslav Ryhel			clk3-out {
849*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk3_out_pee0";
850*8ae70af2SSvyatoslav Ryhel				nvidia,function = "extperiph3";
851*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
852*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
853*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
854*8ae70af2SSvyatoslav Ryhel			};
855*8ae70af2SSvyatoslav Ryhel			sys-clk-req {
856*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "sys_clk_req_pz5";
857*8ae70af2SSvyatoslav Ryhel				nvidia,function = "sysclk";
858*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
859*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
860*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
861*8ae70af2SSvyatoslav Ryhel			};
862*8ae70af2SSvyatoslav Ryhel
863*8ae70af2SSvyatoslav Ryhel			pbb3 {
864*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pbb3";
865*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vgp3";
866*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
867*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
868*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
869*8ae70af2SSvyatoslav Ryhel			};
870*8ae70af2SSvyatoslav Ryhel			pbb4 {
871*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pbb4";
872*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vgp4";
873*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
874*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
875*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
876*8ae70af2SSvyatoslav Ryhel			};
877*8ae70af2SSvyatoslav Ryhel			pbb5 {
878*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "pbb5";
879*8ae70af2SSvyatoslav Ryhel				nvidia,function = "vgp5";
880*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
881*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
882*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
883*8ae70af2SSvyatoslav Ryhel			};
884*8ae70af2SSvyatoslav Ryhel
885*8ae70af2SSvyatoslav Ryhel			clk2-req-pcc5 {
886*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk2_req_pcc5",
887*8ae70af2SSvyatoslav Ryhel					      "clk1_req_pee2";
888*8ae70af2SSvyatoslav Ryhel				nvidia,function = "dap";
889*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
890*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
891*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
892*8ae70af2SSvyatoslav Ryhel			};
893*8ae70af2SSvyatoslav Ryhel			clk3-req-pee1 {
894*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "clk3_req_pee1";
895*8ae70af2SSvyatoslav Ryhel				nvidia,function = "dev3";
896*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
897*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
898*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
899*8ae70af2SSvyatoslav Ryhel			};
900*8ae70af2SSvyatoslav Ryhel
901*8ae70af2SSvyatoslav Ryhel			owr {
902*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "owr";
903*8ae70af2SSvyatoslav Ryhel				nvidia,function = "owr";
904*8ae70af2SSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
905*8ae70af2SSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
906*8ae70af2SSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
907*8ae70af2SSvyatoslav Ryhel			};
908*8ae70af2SSvyatoslav Ryhel
909*8ae70af2SSvyatoslav Ryhel			/* GPIO power/drive control */
910*8ae70af2SSvyatoslav Ryhel			drive-dap1 {
911*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "drive_dap1",
912*8ae70af2SSvyatoslav Ryhel					      "drive_dap2",
913*8ae70af2SSvyatoslav Ryhel					      "drive_dbg",
914*8ae70af2SSvyatoslav Ryhel					      "drive_at5",
915*8ae70af2SSvyatoslav Ryhel					      "drive_gme",
916*8ae70af2SSvyatoslav Ryhel					      "drive_ddc",
917*8ae70af2SSvyatoslav Ryhel					      "drive_ao1",
918*8ae70af2SSvyatoslav Ryhel					      "drive_uart3";
919*8ae70af2SSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
920*8ae70af2SSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
921*8ae70af2SSvyatoslav Ryhel				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
922*8ae70af2SSvyatoslav Ryhel				nvidia,pull-down-strength = <31>;
923*8ae70af2SSvyatoslav Ryhel				nvidia,pull-up-strength = <31>;
924*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
925*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
926*8ae70af2SSvyatoslav Ryhel			};
927*8ae70af2SSvyatoslav Ryhel			drive-sdio1 {
928*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "drive_sdio1",
929*8ae70af2SSvyatoslav Ryhel					      "drive_sdio3";
930*8ae70af2SSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
931*8ae70af2SSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
932*8ae70af2SSvyatoslav Ryhel				nvidia,pull-down-strength = <46>;
933*8ae70af2SSvyatoslav Ryhel				nvidia,pull-up-strength = <42>;
934*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
935*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
936*8ae70af2SSvyatoslav Ryhel			};
937*8ae70af2SSvyatoslav Ryhel			drive-sdmmc4 {
938*8ae70af2SSvyatoslav Ryhel				nvidia,pins = "drive_gma",
939*8ae70af2SSvyatoslav Ryhel					      "drive_gmb",
940*8ae70af2SSvyatoslav Ryhel					      "drive_gmc",
941*8ae70af2SSvyatoslav Ryhel					      "drive_gmd";
942*8ae70af2SSvyatoslav Ryhel				nvidia,pull-down-strength = <9>;
943*8ae70af2SSvyatoslav Ryhel				nvidia,pull-up-strength = <9>;
944*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
945*8ae70af2SSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
946*8ae70af2SSvyatoslav Ryhel			};
947*8ae70af2SSvyatoslav Ryhel		};
948*8ae70af2SSvyatoslav Ryhel	};
949*8ae70af2SSvyatoslav Ryhel
950*8ae70af2SSvyatoslav Ryhel	uartb: serial@70006040 {
951*8ae70af2SSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
952*8ae70af2SSvyatoslav Ryhel		reset-names = "serial";
953*8ae70af2SSvyatoslav Ryhel		/delete-property/ reg-shift;
954*8ae70af2SSvyatoslav Ryhel		status = "okay";
955*8ae70af2SSvyatoslav Ryhel
956*8ae70af2SSvyatoslav Ryhel		/* Broadcom GPS BCM47511 */
957*8ae70af2SSvyatoslav Ryhel	};
958*8ae70af2SSvyatoslav Ryhel
959*8ae70af2SSvyatoslav Ryhel	uartc: serial@70006200 {
960*8ae70af2SSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
961*8ae70af2SSvyatoslav Ryhel		reset-names = "serial";
962*8ae70af2SSvyatoslav Ryhel		/delete-property/ reg-shift;
963*8ae70af2SSvyatoslav Ryhel		status = "okay";
964*8ae70af2SSvyatoslav Ryhel
965*8ae70af2SSvyatoslav Ryhel		nvidia,adjust-baud-rates = <0 9600 100>,
966*8ae70af2SSvyatoslav Ryhel					   <9600 115200 200>,
967*8ae70af2SSvyatoslav Ryhel					   <1000000 4000000 136>;
968*8ae70af2SSvyatoslav Ryhel
969*8ae70af2SSvyatoslav Ryhel		/* Azurewave AW-NH665 BCM4330B1 */
970*8ae70af2SSvyatoslav Ryhel		bluetooth {
971*8ae70af2SSvyatoslav Ryhel			compatible = "brcm,bcm4330-bt";
972*8ae70af2SSvyatoslav Ryhel			max-speed = <4000000>;
973*8ae70af2SSvyatoslav Ryhel
974*8ae70af2SSvyatoslav Ryhel			clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
975*8ae70af2SSvyatoslav Ryhel			clock-names = "txco";
976*8ae70af2SSvyatoslav Ryhel
977*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
978*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
979*8ae70af2SSvyatoslav Ryhel			interrupt-names = "host-wakeup";
980*8ae70af2SSvyatoslav Ryhel
981*8ae70af2SSvyatoslav Ryhel			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
982*8ae70af2SSvyatoslav Ryhel			shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
983*8ae70af2SSvyatoslav Ryhel
984*8ae70af2SSvyatoslav Ryhel			vbat-supply = <&vdd_3v3_com>;
985*8ae70af2SSvyatoslav Ryhel			vddio-supply = <&vdd_1v8_vio>;
986*8ae70af2SSvyatoslav Ryhel		};
987*8ae70af2SSvyatoslav Ryhel	};
988*8ae70af2SSvyatoslav Ryhel
989*8ae70af2SSvyatoslav Ryhel	pwm@7000a000 {
990*8ae70af2SSvyatoslav Ryhel		status = "okay";
991*8ae70af2SSvyatoslav Ryhel	};
992*8ae70af2SSvyatoslav Ryhel
993*8ae70af2SSvyatoslav Ryhel	gen1_i2c: i2c@7000c000 {
994*8ae70af2SSvyatoslav Ryhel		status = "okay";
995*8ae70af2SSvyatoslav Ryhel		clock-frequency = <100000>;
996*8ae70af2SSvyatoslav Ryhel
997*8ae70af2SSvyatoslav Ryhel		/* Nuvoton NPCE698LA0BX embedded controller */
998*8ae70af2SSvyatoslav Ryhel	};
999*8ae70af2SSvyatoslav Ryhel
1000*8ae70af2SSvyatoslav Ryhel	i2c@7000c400 {
1001*8ae70af2SSvyatoslav Ryhel		status = "okay";
1002*8ae70af2SSvyatoslav Ryhel		clock-frequency = <400000>;
1003*8ae70af2SSvyatoslav Ryhel
1004*8ae70af2SSvyatoslav Ryhel		/* Atmel Maxtouch MXT1664 HID over I2C */
1005*8ae70af2SSvyatoslav Ryhel		touchscreen@4b {
1006*8ae70af2SSvyatoslav Ryhel			compatible = "hid-over-i2c";
1007*8ae70af2SSvyatoslav Ryhel			reg = <0x4b>;
1008*8ae70af2SSvyatoslav Ryhel
1009*8ae70af2SSvyatoslav Ryhel			hid-descr-addr = <0x0000>;
1010*8ae70af2SSvyatoslav Ryhel
1011*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1012*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>;
1013*8ae70af2SSvyatoslav Ryhel
1014*8ae70af2SSvyatoslav Ryhel			vdd-supply = <&vdd_3v3_sys>;
1015*8ae70af2SSvyatoslav Ryhel			vddl-supply = <&vdd_1v8_vio>;
1016*8ae70af2SSvyatoslav Ryhel		};
1017*8ae70af2SSvyatoslav Ryhel	};
1018*8ae70af2SSvyatoslav Ryhel
1019*8ae70af2SSvyatoslav Ryhel	i2c@7000c500 {
1020*8ae70af2SSvyatoslav Ryhel		status = "okay";
1021*8ae70af2SSvyatoslav Ryhel		clock-frequency = <100000>;
1022*8ae70af2SSvyatoslav Ryhel
1023*8ae70af2SSvyatoslav Ryhel		/* TI TPS61050/61052 Boost Converter */
1024*8ae70af2SSvyatoslav Ryhel		flash-led@33 {
1025*8ae70af2SSvyatoslav Ryhel			compatible = "ti,tps61052";
1026*8ae70af2SSvyatoslav Ryhel			reg = <0x33>;
1027*8ae70af2SSvyatoslav Ryhel
1028*8ae70af2SSvyatoslav Ryhel			led {
1029*8ae70af2SSvyatoslav Ryhel				color = <LED_COLOR_ID_WHITE>;
1030*8ae70af2SSvyatoslav Ryhel			};
1031*8ae70af2SSvyatoslav Ryhel		};
1032*8ae70af2SSvyatoslav Ryhel
1033*8ae70af2SSvyatoslav Ryhel		imu@69 {
1034*8ae70af2SSvyatoslav Ryhel			compatible = "invensense,mpu6050";
1035*8ae70af2SSvyatoslav Ryhel			reg = <0x69>;
1036*8ae70af2SSvyatoslav Ryhel
1037*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1038*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1039*8ae70af2SSvyatoslav Ryhel
1040*8ae70af2SSvyatoslav Ryhel			vdd-supply   = <&vdd_3v3_sys>;
1041*8ae70af2SSvyatoslav Ryhel			vddio-supply = <&vdd_1v8_vio>;
1042*8ae70af2SSvyatoslav Ryhel
1043*8ae70af2SSvyatoslav Ryhel			mount-matrix =	 "0", "-1",  "0",
1044*8ae70af2SSvyatoslav Ryhel					"-1",  "0",  "0",
1045*8ae70af2SSvyatoslav Ryhel					 "0",  "0", "-1";
1046*8ae70af2SSvyatoslav Ryhel
1047*8ae70af2SSvyatoslav Ryhel			/* External I2C interface */
1048*8ae70af2SSvyatoslav Ryhel			i2c-gate {
1049*8ae70af2SSvyatoslav Ryhel				#address-cells = <1>;
1050*8ae70af2SSvyatoslav Ryhel				#size-cells = <0>;
1051*8ae70af2SSvyatoslav Ryhel
1052*8ae70af2SSvyatoslav Ryhel				magnetometer@d {
1053*8ae70af2SSvyatoslav Ryhel					compatible = "asahi-kasei,ak8975";
1054*8ae70af2SSvyatoslav Ryhel					reg = <0x0d>;
1055*8ae70af2SSvyatoslav Ryhel
1056*8ae70af2SSvyatoslav Ryhel					interrupt-parent = <&gpio>;
1057*8ae70af2SSvyatoslav Ryhel					interrupts = <TEGRA_GPIO(D, 5) IRQ_TYPE_EDGE_RISING>;
1058*8ae70af2SSvyatoslav Ryhel
1059*8ae70af2SSvyatoslav Ryhel					vdd-supply = <&vdd_3v3_sys>;
1060*8ae70af2SSvyatoslav Ryhel					vid-supply = <&vdd_1v8_vio>;
1061*8ae70af2SSvyatoslav Ryhel
1062*8ae70af2SSvyatoslav Ryhel					mount-matrix =	 "0", "-1",  "0",
1063*8ae70af2SSvyatoslav Ryhel							"-1",  "0",  "0",
1064*8ae70af2SSvyatoslav Ryhel							 "0",  "0", "-1";
1065*8ae70af2SSvyatoslav Ryhel				};
1066*8ae70af2SSvyatoslav Ryhel			};
1067*8ae70af2SSvyatoslav Ryhel		};
1068*8ae70af2SSvyatoslav Ryhel	};
1069*8ae70af2SSvyatoslav Ryhel
1070*8ae70af2SSvyatoslav Ryhel	hdmi_ddc: i2c@7000c700 {
1071*8ae70af2SSvyatoslav Ryhel		status = "okay";
1072*8ae70af2SSvyatoslav Ryhel		clock-frequency = <93750>;
1073*8ae70af2SSvyatoslav Ryhel	};
1074*8ae70af2SSvyatoslav Ryhel
1075*8ae70af2SSvyatoslav Ryhel	i2c@7000d000 {
1076*8ae70af2SSvyatoslav Ryhel		status = "okay";
1077*8ae70af2SSvyatoslav Ryhel		clock-frequency = <400000>;
1078*8ae70af2SSvyatoslav Ryhel
1079*8ae70af2SSvyatoslav Ryhel		rt5640: audio-codec@1c {
1080*8ae70af2SSvyatoslav Ryhel			compatible = "realtek,rt5640";
1081*8ae70af2SSvyatoslav Ryhel			reg = <0x1c>;
1082*8ae70af2SSvyatoslav Ryhel
1083*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1084*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
1085*8ae70af2SSvyatoslav Ryhel
1086*8ae70af2SSvyatoslav Ryhel			clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1087*8ae70af2SSvyatoslav Ryhel			clock-names = "mclk";
1088*8ae70af2SSvyatoslav Ryhel		};
1089*8ae70af2SSvyatoslav Ryhel
1090*8ae70af2SSvyatoslav Ryhel		/* Texas Instruments TPS659110 PMIC */
1091*8ae70af2SSvyatoslav Ryhel		pmic: pmic@2d {
1092*8ae70af2SSvyatoslav Ryhel			compatible = "ti,tps65911";
1093*8ae70af2SSvyatoslav Ryhel			reg = <0x2d>;
1094*8ae70af2SSvyatoslav Ryhel
1095*8ae70af2SSvyatoslav Ryhel			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1096*8ae70af2SSvyatoslav Ryhel			#interrupt-cells = <2>;
1097*8ae70af2SSvyatoslav Ryhel			interrupt-controller;
1098*8ae70af2SSvyatoslav Ryhel
1099*8ae70af2SSvyatoslav Ryhel			ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1100*8ae70af2SSvyatoslav Ryhel			ti,system-power-controller;
1101*8ae70af2SSvyatoslav Ryhel			ti,sleep-keep-ck32k;
1102*8ae70af2SSvyatoslav Ryhel			ti,sleep-enable;
1103*8ae70af2SSvyatoslav Ryhel
1104*8ae70af2SSvyatoslav Ryhel			#gpio-cells = <2>;
1105*8ae70af2SSvyatoslav Ryhel			gpio-controller;
1106*8ae70af2SSvyatoslav Ryhel
1107*8ae70af2SSvyatoslav Ryhel			vcc1-supply = <&vdd_5v0_bat>;
1108*8ae70af2SSvyatoslav Ryhel			vcc2-supply = <&vdd_5v0_bat>;
1109*8ae70af2SSvyatoslav Ryhel			vcc3-supply = <&vdd_1v8_vio>;
1110*8ae70af2SSvyatoslav Ryhel			vcc4-supply = <&vdd_5v0_sys>;
1111*8ae70af2SSvyatoslav Ryhel			vcc5-supply = <&vdd_5v0_bat>;
1112*8ae70af2SSvyatoslav Ryhel			vcc6-supply = <&vdd_3v3_sys>;
1113*8ae70af2SSvyatoslav Ryhel			vcc7-supply = <&vdd_5v0_bat>;
1114*8ae70af2SSvyatoslav Ryhel			vccio-supply = <&vdd_5v0_bat>;
1115*8ae70af2SSvyatoslav Ryhel
1116*8ae70af2SSvyatoslav Ryhel			pmic-sleep-hog {
1117*8ae70af2SSvyatoslav Ryhel				gpio-hog;
1118*8ae70af2SSvyatoslav Ryhel				gpios = <2 GPIO_ACTIVE_HIGH>;
1119*8ae70af2SSvyatoslav Ryhel				output-high;
1120*8ae70af2SSvyatoslav Ryhel			};
1121*8ae70af2SSvyatoslav Ryhel
1122*8ae70af2SSvyatoslav Ryhel			regulators {
1123*8ae70af2SSvyatoslav Ryhel				vdd_lcd: vdd1 {
1124*8ae70af2SSvyatoslav Ryhel					regulator-name = "vddio_ddr_1v2";
1125*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1126*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1127*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1128*8ae70af2SSvyatoslav Ryhel					regulator-boot-on;
1129*8ae70af2SSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <8>;
1130*8ae70af2SSvyatoslav Ryhel				};
1131*8ae70af2SSvyatoslav Ryhel
1132*8ae70af2SSvyatoslav Ryhel				vddio_ddr: vdd2 {
1133*8ae70af2SSvyatoslav Ryhel					regulator-name = "vddio_ddr";
1134*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1135*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1136*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1137*8ae70af2SSvyatoslav Ryhel					regulator-boot-on;
1138*8ae70af2SSvyatoslav Ryhel				};
1139*8ae70af2SSvyatoslav Ryhel
1140*8ae70af2SSvyatoslav Ryhel				vdd_cpu: vddctrl {
1141*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_cpu,vdd_sys";
1142*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <600000>;
1143*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1400000>;
1144*8ae70af2SSvyatoslav Ryhel					regulator-coupled-with = <&vdd_core>;
1145*8ae70af2SSvyatoslav Ryhel					regulator-coupled-max-spread = <300000>;
1146*8ae70af2SSvyatoslav Ryhel					regulator-max-step-microvolt = <100000>;
1147*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1148*8ae70af2SSvyatoslav Ryhel					regulator-boot-on;
1149*8ae70af2SSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <1>;
1150*8ae70af2SSvyatoslav Ryhel
1151*8ae70af2SSvyatoslav Ryhel					nvidia,tegra-cpu-regulator;
1152*8ae70af2SSvyatoslav Ryhel				};
1153*8ae70af2SSvyatoslav Ryhel
1154*8ae70af2SSvyatoslav Ryhel				vdd_1v8_vio: vio {
1155*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_1v8_gen";
1156*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1800000>;
1157*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1800000>;
1158*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1159*8ae70af2SSvyatoslav Ryhel					regulator-boot-on;
1160*8ae70af2SSvyatoslav Ryhel				};
1161*8ae70af2SSvyatoslav Ryhel
1162*8ae70af2SSvyatoslav Ryhel				/* eMMC VDD */
1163*8ae70af2SSvyatoslav Ryhel				vcore_emmc: ldo1 {
1164*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_emmc_core";
1165*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1000000>;
1166*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <3300000>;
1167*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1168*8ae70af2SSvyatoslav Ryhel				};
1169*8ae70af2SSvyatoslav Ryhel
1170*8ae70af2SSvyatoslav Ryhel				/* ldo2 and ldo3 are not used by TF600T */
1171*8ae70af2SSvyatoslav Ryhel
1172*8ae70af2SSvyatoslav Ryhel				ldo4 {
1173*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_rtc";
1174*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1175*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1176*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1177*8ae70af2SSvyatoslav Ryhel				};
1178*8ae70af2SSvyatoslav Ryhel
1179*8ae70af2SSvyatoslav Ryhel				/* uSD slot VDDIO */
1180*8ae70af2SSvyatoslav Ryhel				vddio_usd: ldo5 {
1181*8ae70af2SSvyatoslav Ryhel					regulator-name = "vddio_sdmmc";
1182*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1800000>;
1183*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <3300000>;
1184*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1185*8ae70af2SSvyatoslav Ryhel				};
1186*8ae70af2SSvyatoslav Ryhel
1187*8ae70af2SSvyatoslav Ryhel				avdd_dsi_csi: ldo6 {
1188*8ae70af2SSvyatoslav Ryhel					regulator-name = "avdd_dsi_csi";
1189*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1190*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1191*8ae70af2SSvyatoslav Ryhel				};
1192*8ae70af2SSvyatoslav Ryhel
1193*8ae70af2SSvyatoslav Ryhel				ldo7 {
1194*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_pllm,x,u,a_p_c_s";
1195*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1196*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1197*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1198*8ae70af2SSvyatoslav Ryhel					regulator-boot-on;
1199*8ae70af2SSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <8>;
1200*8ae70af2SSvyatoslav Ryhel				};
1201*8ae70af2SSvyatoslav Ryhel
1202*8ae70af2SSvyatoslav Ryhel				ldo8 {
1203*8ae70af2SSvyatoslav Ryhel					regulator-name = "vdd_ddr_hs";
1204*8ae70af2SSvyatoslav Ryhel					regulator-min-microvolt = <1000000>;
1205*8ae70af2SSvyatoslav Ryhel					regulator-max-microvolt = <1000000>;
1206*8ae70af2SSvyatoslav Ryhel					regulator-always-on;
1207*8ae70af2SSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <8>;
1208*8ae70af2SSvyatoslav Ryhel				};
1209*8ae70af2SSvyatoslav Ryhel			};
1210*8ae70af2SSvyatoslav Ryhel		};
1211*8ae70af2SSvyatoslav Ryhel
1212*8ae70af2SSvyatoslav Ryhel		/* Capella CM3218 ambient light sensor */
1213*8ae70af2SSvyatoslav Ryhel		light-sensor@48 {
1214*8ae70af2SSvyatoslav Ryhel			compatible = "capella,cm32181";
1215*8ae70af2SSvyatoslav Ryhel			reg = <0x48>;
1216*8ae70af2SSvyatoslav Ryhel
1217*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1218*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_EDGE_RISING>;
1219*8ae70af2SSvyatoslav Ryhel
1220*8ae70af2SSvyatoslav Ryhel			vdd-supply = <&vdd_3v3_als>;
1221*8ae70af2SSvyatoslav Ryhel		};
1222*8ae70af2SSvyatoslav Ryhel
1223*8ae70af2SSvyatoslav Ryhel		nct72: temperature-sensor@4c {
1224*8ae70af2SSvyatoslav Ryhel			compatible = "onnn,nct1008";
1225*8ae70af2SSvyatoslav Ryhel			reg = <0x4c>;
1226*8ae70af2SSvyatoslav Ryhel
1227*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1228*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1229*8ae70af2SSvyatoslav Ryhel
1230*8ae70af2SSvyatoslav Ryhel			vcc-supply = <&vdd_3v3_sys>;
1231*8ae70af2SSvyatoslav Ryhel			#thermal-sensor-cells = <1>;
1232*8ae70af2SSvyatoslav Ryhel		};
1233*8ae70af2SSvyatoslav Ryhel
1234*8ae70af2SSvyatoslav Ryhel		vdd_core: core-regulator@60 {
1235*8ae70af2SSvyatoslav Ryhel			compatible = "ti,tps62361";
1236*8ae70af2SSvyatoslav Ryhel			reg = <0x60>;
1237*8ae70af2SSvyatoslav Ryhel
1238*8ae70af2SSvyatoslav Ryhel			regulator-name = "tps62361-vout";
1239*8ae70af2SSvyatoslav Ryhel			regulator-min-microvolt = <500000>;
1240*8ae70af2SSvyatoslav Ryhel			regulator-max-microvolt = <1770000>;
1241*8ae70af2SSvyatoslav Ryhel			regulator-coupled-with = <&vdd_cpu>;
1242*8ae70af2SSvyatoslav Ryhel			regulator-coupled-max-spread = <300000>;
1243*8ae70af2SSvyatoslav Ryhel			regulator-max-step-microvolt = <100000>;
1244*8ae70af2SSvyatoslav Ryhel			regulator-boot-on;
1245*8ae70af2SSvyatoslav Ryhel			regulator-always-on;
1246*8ae70af2SSvyatoslav Ryhel			ti,enable-vout-discharge;
1247*8ae70af2SSvyatoslav Ryhel			ti,vsel0-state-high;
1248*8ae70af2SSvyatoslav Ryhel			ti,vsel1-state-high;
1249*8ae70af2SSvyatoslav Ryhel
1250*8ae70af2SSvyatoslav Ryhel			nvidia,tegra-core-regulator;
1251*8ae70af2SSvyatoslav Ryhel		};
1252*8ae70af2SSvyatoslav Ryhel	};
1253*8ae70af2SSvyatoslav Ryhel
1254*8ae70af2SSvyatoslav Ryhel	pmc@7000e400 {
1255*8ae70af2SSvyatoslav Ryhel		status = "okay";
1256*8ae70af2SSvyatoslav Ryhel		nvidia,invert-interrupt;
1257*8ae70af2SSvyatoslav Ryhel		nvidia,suspend-mode = <2>;
1258*8ae70af2SSvyatoslav Ryhel		nvidia,cpu-pwr-good-time = <2000>;
1259*8ae70af2SSvyatoslav Ryhel		nvidia,cpu-pwr-off-time = <200>;
1260*8ae70af2SSvyatoslav Ryhel		nvidia,core-pwr-good-time = <3845 3845>;
1261*8ae70af2SSvyatoslav Ryhel		nvidia,core-pwr-off-time = <0>;
1262*8ae70af2SSvyatoslav Ryhel		nvidia,core-power-req-active-high;
1263*8ae70af2SSvyatoslav Ryhel		nvidia,sys-clock-req-active-high;
1264*8ae70af2SSvyatoslav Ryhel		core-supply = <&vdd_core>;
1265*8ae70af2SSvyatoslav Ryhel
1266*8ae70af2SSvyatoslav Ryhel		i2c-thermtrip {
1267*8ae70af2SSvyatoslav Ryhel			nvidia,i2c-controller-id = <4>;
1268*8ae70af2SSvyatoslav Ryhel			nvidia,bus-addr = <0x2d>;
1269*8ae70af2SSvyatoslav Ryhel			nvidia,reg-addr = <0x3f>;
1270*8ae70af2SSvyatoslav Ryhel			nvidia,reg-data = <0x81>;
1271*8ae70af2SSvyatoslav Ryhel		};
1272*8ae70af2SSvyatoslav Ryhel	};
1273*8ae70af2SSvyatoslav Ryhel
1274*8ae70af2SSvyatoslav Ryhel	spi@7000da00 {
1275*8ae70af2SSvyatoslav Ryhel		status = "okay";
1276*8ae70af2SSvyatoslav Ryhel		spi-max-frequency = <25000000>;
1277*8ae70af2SSvyatoslav Ryhel
1278*8ae70af2SSvyatoslav Ryhel		flash@1 {
1279*8ae70af2SSvyatoslav Ryhel			compatible = "winbond,w25q32", "jedec,spi-nor";
1280*8ae70af2SSvyatoslav Ryhel			reg = <1>;
1281*8ae70af2SSvyatoslav Ryhel
1282*8ae70af2SSvyatoslav Ryhel			spi-max-frequency = <20000000>;
1283*8ae70af2SSvyatoslav Ryhel			vcc-supply = <&vdd_3v3_sys>;
1284*8ae70af2SSvyatoslav Ryhel		};
1285*8ae70af2SSvyatoslav Ryhel	};
1286*8ae70af2SSvyatoslav Ryhel
1287*8ae70af2SSvyatoslav Ryhel	memory-controller@7000f000 {
1288*8ae70af2SSvyatoslav Ryhel		emc-timings-0 {
1289*8ae70af2SSvyatoslav Ryhel			/* Elpida 2GB 750 MHZ */
1290*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <0>;
1291*8ae70af2SSvyatoslav Ryhel
1292*8ae70af2SSvyatoslav Ryhel			timing-25500000 {
1293*8ae70af2SSvyatoslav Ryhel				clock-frequency = <25500000>;
1294*8ae70af2SSvyatoslav Ryhel
1295*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00020001 0xc0000010
1296*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1297*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1298*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1299*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0502 0x75e30303 0x001f0000 >;
1300*8ae70af2SSvyatoslav Ryhel			};
1301*8ae70af2SSvyatoslav Ryhel
1302*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1303*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1304*8ae70af2SSvyatoslav Ryhel
1305*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00010001 0xc0000010
1306*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1307*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1308*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1309*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0502 0x74e30303 0x001f0000 >;
1310*8ae70af2SSvyatoslav Ryhel			};
1311*8ae70af2SSvyatoslav Ryhel
1312*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1313*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1314*8ae70af2SSvyatoslav Ryhel
1315*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000001 0xc0000018
1316*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000000
1317*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1318*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1319*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0503 0x74430504 0x001f0000 >;
1320*8ae70af2SSvyatoslav Ryhel			};
1321*8ae70af2SSvyatoslav Ryhel
1322*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1323*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1324*8ae70af2SSvyatoslav Ryhel
1325*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000003 0xc0000025
1326*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000005 0x00000002
1327*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000001 0x00000003 0x00000008
1328*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1329*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0505 0x74040a06 0x001f0000 >;
1330*8ae70af2SSvyatoslav Ryhel			};
1331*8ae70af2SSvyatoslav Ryhel
1332*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1333*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1334*8ae70af2SSvyatoslav Ryhel
1335*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000005 0xc0000044
1336*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000002 0x00000009 0x00000005
1337*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000001 0x00000002 0x00000008
1338*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000003 0x00000006
1339*8ae70af2SSvyatoslav Ryhel					0x06030202 0x000d0709 0x7086110a 0x001f0000 >;
1340*8ae70af2SSvyatoslav Ryhel			};
1341*8ae70af2SSvyatoslav Ryhel
1342*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
1343*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
1344*8ae70af2SSvyatoslav Ryhel
1345*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x0000000b 0xc0000087
1346*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000005 0x00000012 0x0000000c
1347*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000002 0x00000003 0x0000000c
1348*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000004 0x00000008
1349*8ae70af2SSvyatoslav Ryhel					0x08040202 0x00160d12 0x710c2213 0x001f0000 >;
1350*8ae70af2SSvyatoslav Ryhel			};
1351*8ae70af2SSvyatoslav Ryhel		};
1352*8ae70af2SSvyatoslav Ryhel
1353*8ae70af2SSvyatoslav Ryhel		emc-timings-1 {
1354*8ae70af2SSvyatoslav Ryhel			/* Hynix 2GB 750 MHZ */
1355*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <1>;
1356*8ae70af2SSvyatoslav Ryhel
1357*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1358*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1359*8ae70af2SSvyatoslav Ryhel
1360*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00010003 0xc0000010
1361*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1362*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1363*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1364*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0502 0x74630303 0x001f0000 >;
1365*8ae70af2SSvyatoslav Ryhel			};
1366*8ae70af2SSvyatoslav Ryhel
1367*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1368*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1369*8ae70af2SSvyatoslav Ryhel
1370*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000003 0xc0000018
1371*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000000
1372*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1373*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1374*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
1375*8ae70af2SSvyatoslav Ryhel			};
1376*8ae70af2SSvyatoslav Ryhel
1377*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1378*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1379*8ae70af2SSvyatoslav Ryhel
1380*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000006 0xc0000025
1381*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000005 0x00000002
1382*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000001 0x00000003 0x00000008
1383*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1384*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
1385*8ae70af2SSvyatoslav Ryhel			};
1386*8ae70af2SSvyatoslav Ryhel
1387*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1388*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1389*8ae70af2SSvyatoslav Ryhel
1390*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x0000000b 0xc0000044
1391*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000002 0x00000009 0x00000005
1392*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000001 0x00000002 0x00000008
1393*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000003 0x00000006
1394*8ae70af2SSvyatoslav Ryhel					0x06030202 0x000c0609 0x7086110a 0x001f0000 >;
1395*8ae70af2SSvyatoslav Ryhel			};
1396*8ae70af2SSvyatoslav Ryhel
1397*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
1398*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
1399*8ae70af2SSvyatoslav Ryhel
1400*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000016 0xc0000087
1401*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000004 0x00000012 0x0000000c
1402*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000002 0x00000003 0x0000000c
1403*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000004 0x00000008
1404*8ae70af2SSvyatoslav Ryhel					0x08040202 0x00150c12 0x710c2213 0x001f0000 >;
1405*8ae70af2SSvyatoslav Ryhel			};
1406*8ae70af2SSvyatoslav Ryhel		};
1407*8ae70af2SSvyatoslav Ryhel
1408*8ae70af2SSvyatoslav Ryhel		emc-timings-2 {
1409*8ae70af2SSvyatoslav Ryhel			/* Micron 2GB 750 MHZ */
1410*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <2>;
1411*8ae70af2SSvyatoslav Ryhel
1412*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1413*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1414*8ae70af2SSvyatoslav Ryhel
1415*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00010003 0xc0000010
1416*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1417*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1418*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1419*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0502 0x73430303 0x001f0000 >;
1420*8ae70af2SSvyatoslav Ryhel			};
1421*8ae70af2SSvyatoslav Ryhel
1422*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1423*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1424*8ae70af2SSvyatoslav Ryhel
1425*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000003 0xc0000018
1426*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000000
1427*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1428*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1429*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0503 0x74430504 0x001f0000 >;
1430*8ae70af2SSvyatoslav Ryhel			};
1431*8ae70af2SSvyatoslav Ryhel
1432*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1433*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1434*8ae70af2SSvyatoslav Ryhel
1435*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000006 0xc0000025
1436*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000001 0x00000005 0x00000002
1437*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000001 0x00000003 0x00000008
1438*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1439*8ae70af2SSvyatoslav Ryhel					0x06020102 0x000a0505 0x74040a06 0x001f0000 >;
1440*8ae70af2SSvyatoslav Ryhel			};
1441*8ae70af2SSvyatoslav Ryhel
1442*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1443*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1444*8ae70af2SSvyatoslav Ryhel
1445*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x0000000b 0xc0000044
1446*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000002 0x00000009 0x00000005
1447*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000001 0x00000002 0x00000008
1448*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000003 0x00000006
1449*8ae70af2SSvyatoslav Ryhel					0x06030202 0x000d0709 0x7086110a 0x001f0000 >;
1450*8ae70af2SSvyatoslav Ryhel			};
1451*8ae70af2SSvyatoslav Ryhel
1452*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
1453*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
1454*8ae70af2SSvyatoslav Ryhel
1455*8ae70af2SSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000016 0xc0000087
1456*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000005 0x00000012 0x0000000c
1457*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000003 0x00000003 0x0000000c
1458*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000004 0x00000008
1459*8ae70af2SSvyatoslav Ryhel					0x08040202 0x00160d12 0x710c2213 0x001f0000 >;
1460*8ae70af2SSvyatoslav Ryhel			};
1461*8ae70af2SSvyatoslav Ryhel		};
1462*8ae70af2SSvyatoslav Ryhel	};
1463*8ae70af2SSvyatoslav Ryhel
1464*8ae70af2SSvyatoslav Ryhel	memory-controller@7000f400 {
1465*8ae70af2SSvyatoslav Ryhel		emc-timings-0 {
1466*8ae70af2SSvyatoslav Ryhel			/* Elpida 2GB 750 MHZ */
1467*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <0>;
1468*8ae70af2SSvyatoslav Ryhel
1469*8ae70af2SSvyatoslav Ryhel			timing-25500000 {
1470*8ae70af2SSvyatoslav Ryhel				clock-frequency = <25500000>;
1471*8ae70af2SSvyatoslav Ryhel
1472*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1473*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1474*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1475*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1476*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1477*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1478*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1479*8ae70af2SSvyatoslav Ryhel
1480*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000001
1481*8ae70af2SSvyatoslav Ryhel					0x00000007 0x00000000 0x00000000 0x00000002
1482*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1483*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1484*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1485*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x000000c0 0x00000000 0x00000030
1486*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1487*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000008 0x00000008
1488*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000001 0x00000000 0x00000004
1489*8ae70af2SSvyatoslav Ryhel					0x00000005 0x000000c7 0x00000006 0x00000004
1490*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1491*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1492*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1493*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1494*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1495*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1496*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1497*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1498*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1499*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1500*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1501*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1502*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
1503*8ae70af2SSvyatoslav Ryhel			};
1504*8ae70af2SSvyatoslav Ryhel
1505*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1506*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1507*8ae70af2SSvyatoslav Ryhel
1508*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1509*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1510*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1511*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1512*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1513*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1514*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1515*8ae70af2SSvyatoslav Ryhel
1516*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000002
1517*8ae70af2SSvyatoslav Ryhel					0x0000000f 0x00000001 0x00000000 0x00000002
1518*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1519*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1520*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1521*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000181 0x00000000 0x00000060
1522*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1523*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000010 0x00000010
1524*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000002 0x00000000 0x00000004
1525*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000018e 0x00000006 0x00000004
1526*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1527*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1528*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1529*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1530*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1531*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1532*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1533*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1534*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1535*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1536*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1537*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1538*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
1539*8ae70af2SSvyatoslav Ryhel			};
1540*8ae70af2SSvyatoslav Ryhel
1541*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1542*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1543*8ae70af2SSvyatoslav Ryhel
1544*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1545*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1546*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1547*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1548*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1549*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1550*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1551*8ae70af2SSvyatoslav Ryhel
1552*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000004
1553*8ae70af2SSvyatoslav Ryhel					0x0000001e 0x00000003 0x00000001 0x00000002
1554*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000001
1555*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000003 0x00000001 0x00000000
1556*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1557*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000303 0x00000000 0x000000c0
1558*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1559*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000020 0x00000020
1560*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000004 0x00000000 0x00000004
1561*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000031c 0x00000006 0x00000004
1562*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1563*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1564*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1565*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1566*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1567*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1568*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1569*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1570*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1571*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1572*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1573*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1574*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
1575*8ae70af2SSvyatoslav Ryhel			};
1576*8ae70af2SSvyatoslav Ryhel
1577*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1578*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1579*8ae70af2SSvyatoslav Ryhel
1580*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1581*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1582*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1583*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1584*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1585*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1586*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1587*8ae70af2SSvyatoslav Ryhel
1588*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000009
1589*8ae70af2SSvyatoslav Ryhel					0x0000003d 0x00000007 0x00000002 0x00000002
1590*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000002
1591*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000003 0x00000001 0x00000000
1592*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000006 0x00000004 0x0000000a
1593*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000607 0x00000000 0x00000181
1594*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1595*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000040 0x00000040
1596*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000007 0x00000000 0x00000004
1597*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000638 0x00000007 0x00000004
1598*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x004400a4
1599*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00080000 0x00080000 0x00080000
1600*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00080000 0x00080000 0x00080000
1601*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00000000 0x00000000 0x00000000
1602*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1603*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1604*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1605*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00080000 0x00080000 0x00080000
1606*8ae70af2SSvyatoslav Ryhel					0x00080000 0x000002a0 0x0800211c 0x00000000
1607*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1608*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00020000
1609*8ae70af2SSvyatoslav Ryhel					0x00000100 0x000c000c 0xa0f10000 0x00000000
1610*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
1611*8ae70af2SSvyatoslav Ryhel			};
1612*8ae70af2SSvyatoslav Ryhel
1613*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1614*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1615*8ae70af2SSvyatoslav Ryhel
1616*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1617*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1618*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200040>;
1619*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000521>;
1620*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1621*8ae70af2SSvyatoslav Ryhel
1622*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000011
1623*8ae70af2SSvyatoslav Ryhel					0x0000006f 0x0000000c 0x00000004 0x00000003
1624*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000002 0x0000000a 0x00000004
1625*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000002 0x00000001 0x00000000
1626*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000006 0x00000004 0x0000000a
1627*8ae70af2SSvyatoslav Ryhel					0x0000000c 0x00000b2d 0x00000000 0x000002cb
1628*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000008 0x00000001 0x00000000
1629*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000075 0x00000200
1630*8ae70af2SSvyatoslav Ryhel					0x00000004 0x0000000c 0x00000000 0x00000004
1631*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000b6d 0x00000000 0x00000004
1632*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00007088 0x00200084
1633*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00034000 0x00034000 0x00034000
1634*8ae70af2SSvyatoslav Ryhel					0x00034000 0x00014000 0x00014000 0x00014000
1635*8ae70af2SSvyatoslav Ryhel					0x00014000 0x00000000 0x00000000 0x00000000
1636*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1637*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1638*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1639*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00048000 0x00048000 0x00048000
1640*8ae70af2SSvyatoslav Ryhel					0x00048000 0x000002a0 0x0600013d 0x00000000
1641*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f508 0x05057404 0x54000007
1642*8ae70af2SSvyatoslav Ryhel					0x080001e8 0x06000021 0x00000802 0x00020000
1643*8ae70af2SSvyatoslav Ryhel					0x00000100 0x0150000c 0xa0f10000 0x00000000
1644*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000174b 0xe8000000 0xff00ff89 >;
1645*8ae70af2SSvyatoslav Ryhel			};
1646*8ae70af2SSvyatoslav Ryhel
1647*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
1648*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
1649*8ae70af2SSvyatoslav Ryhel
1650*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1651*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1652*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200058>;
1653*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000d71>;
1654*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1655*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1656*8ae70af2SSvyatoslav Ryhel
1657*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000023
1658*8ae70af2SSvyatoslav Ryhel					0x000000df 0x00000019 0x00000009 0x00000005
1659*8ae70af2SSvyatoslav Ryhel					0x0000000d 0x00000004 0x00000013 0x00000009
1660*8ae70af2SSvyatoslav Ryhel					0x00000009 0x00000003 0x00000001 0x00000000
1661*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000b 0x00000009 0x0000000b
1662*8ae70af2SSvyatoslav Ryhel					0x00000011 0x0000169a 0x00000000 0x000005a6
1663*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000010 0x00000001 0x00000000
1664*8ae70af2SSvyatoslav Ryhel					0x0000000e 0x00000018 0x000000e9 0x00000200
1665*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000017 0x00000000 0x00000007
1666*8ae70af2SSvyatoslav Ryhel					0x00000008 0x000016da 0x0000000c 0x00000004
1667*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00005088 0xf0080191
1668*8ae70af2SSvyatoslav Ryhel					0x00008000 0x0000000a 0x0000000a 0x0000000a
1669*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000008 0x00000008 0x00000008
1670*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000000 0x00000000 0x00000000
1671*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1672*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1673*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1674*8ae70af2SSvyatoslav Ryhel					0x00000000 0x0000000a 0x0000000a 0x0000000a
1675*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x000002a0 0x0600013d 0x22220000
1676*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f501 0x07077404 0x54000000
1677*8ae70af2SSvyatoslav Ryhel					0x080001e8 0x06000021 0x00000802 0x00020000
1678*8ae70af2SSvyatoslav Ryhel					0x00000100 0x00df000c 0xa0f10000 0x00000000
1679*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80002d93 0xf8000000 0xff00ff49 >;
1680*8ae70af2SSvyatoslav Ryhel			};
1681*8ae70af2SSvyatoslav Ryhel		};
1682*8ae70af2SSvyatoslav Ryhel
1683*8ae70af2SSvyatoslav Ryhel		emc-timings-1 {
1684*8ae70af2SSvyatoslav Ryhel			/* Hynix 2GB 750 MHZ */
1685*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <1>;
1686*8ae70af2SSvyatoslav Ryhel
1687*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1688*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1689*8ae70af2SSvyatoslav Ryhel
1690*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1691*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1692*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1693*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1694*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1695*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1696*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1697*8ae70af2SSvyatoslav Ryhel
1698*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000002
1699*8ae70af2SSvyatoslav Ryhel					0x0000000d 0x00000001 0x00000000 0x00000002
1700*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1701*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1702*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1703*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000181 0x00000000 0x00000060
1704*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1705*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x0000000e 0x0000000e
1706*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000002 0x00000000 0x00000004
1707*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000018e 0x00000006 0x00000004
1708*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1709*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1710*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1711*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1712*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1713*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1714*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1715*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1716*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1717*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1718*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1719*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1720*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
1721*8ae70af2SSvyatoslav Ryhel			};
1722*8ae70af2SSvyatoslav Ryhel
1723*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1724*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1725*8ae70af2SSvyatoslav Ryhel
1726*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1727*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1728*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1729*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1730*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1731*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1732*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1733*8ae70af2SSvyatoslav Ryhel
1734*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000004
1735*8ae70af2SSvyatoslav Ryhel					0x0000001a 0x00000003 0x00000001 0x00000002
1736*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000001
1737*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000003 0x00000001 0x00000000
1738*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1739*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000303 0x00000000 0x000000c0
1740*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1741*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x0000001c 0x0000001c
1742*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000004 0x00000000 0x00000004
1743*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000031c 0x00000006 0x00000004
1744*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1745*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1746*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1747*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1748*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1749*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1750*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1751*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1752*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1753*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1754*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1755*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1756*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
1757*8ae70af2SSvyatoslav Ryhel			};
1758*8ae70af2SSvyatoslav Ryhel
1759*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1760*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1761*8ae70af2SSvyatoslav Ryhel
1762*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1763*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1764*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1765*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1766*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1767*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1768*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1769*8ae70af2SSvyatoslav Ryhel
1770*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000009
1771*8ae70af2SSvyatoslav Ryhel					0x00000035 0x00000007 0x00000002 0x00000002
1772*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000002
1773*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000003 0x00000001 0x00000000
1774*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000006 0x00000004 0x0000000a
1775*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000607 0x00000000 0x00000181
1776*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1777*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000038 0x00000038
1778*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000007 0x00000000 0x00000004
1779*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000638 0x00000007 0x00000004
1780*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x004400a4
1781*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00080000 0x00080000 0x00080000
1782*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00080000 0x00080000 0x00080000
1783*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00000000 0x00000000 0x00000000
1784*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1785*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1786*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1787*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00080000 0x00080000 0x00080000
1788*8ae70af2SSvyatoslav Ryhel					0x00080000 0x000002a0 0x0800211c 0x00000000
1789*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1790*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00020000
1791*8ae70af2SSvyatoslav Ryhel					0x00000100 0x000c000c 0xa0f10000 0x00000000
1792*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
1793*8ae70af2SSvyatoslav Ryhel			};
1794*8ae70af2SSvyatoslav Ryhel
1795*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1796*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1797*8ae70af2SSvyatoslav Ryhel
1798*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1799*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1800*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200040>;
1801*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000521>;
1802*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1803*8ae70af2SSvyatoslav Ryhel
1804*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000011
1805*8ae70af2SSvyatoslav Ryhel					0x00000060 0x0000000c 0x00000003 0x00000004
1806*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000002 0x0000000a 0x00000003
1807*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000002 0x00000001 0x00000000
1808*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000006 0x00000004 0x0000000a
1809*8ae70af2SSvyatoslav Ryhel					0x0000000c 0x00000b2d 0x00000000 0x000002cb
1810*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000008 0x00000001 0x00000000
1811*8ae70af2SSvyatoslav Ryhel					0x00000007 0x00000010 0x00000066 0x00000200
1812*8ae70af2SSvyatoslav Ryhel					0x00000004 0x0000000c 0x00000000 0x00000004
1813*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000b6d 0x00000000 0x00000004
1814*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00007288 0x00200084
1815*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00044000 0x00044000 0x00044000
1816*8ae70af2SSvyatoslav Ryhel					0x00044000 0x00014000 0x00014000 0x00014000
1817*8ae70af2SSvyatoslav Ryhel					0x00014000 0x00000000 0x00000000 0x00000000
1818*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1819*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1820*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1821*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00048000 0x00048000 0x00048000
1822*8ae70af2SSvyatoslav Ryhel					0x00048000 0x000002a0 0x0600013d 0x00000000
1823*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f508 0x05057404 0x54000007
1824*8ae70af2SSvyatoslav Ryhel					0x08000168 0x06000021 0x00000802 0x00020000
1825*8ae70af2SSvyatoslav Ryhel					0x00000100 0x015f000c 0xa0f10000 0x00000000
1826*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000174b 0xe8000000 0xff00ff89 >;
1827*8ae70af2SSvyatoslav Ryhel			};
1828*8ae70af2SSvyatoslav Ryhel
1829*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
1830*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
1831*8ae70af2SSvyatoslav Ryhel
1832*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1833*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1834*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200058>;
1835*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000d71>;
1836*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1837*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1838*8ae70af2SSvyatoslav Ryhel
1839*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000023
1840*8ae70af2SSvyatoslav Ryhel					0x000000c1 0x00000019 0x00000008 0x00000005
1841*8ae70af2SSvyatoslav Ryhel					0x0000000d 0x00000004 0x00000013 0x00000008
1842*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000003 0x00000001 0x00000000
1843*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000b 0x00000009 0x0000000b
1844*8ae70af2SSvyatoslav Ryhel					0x00000011 0x0000169a 0x00000000 0x000005a6
1845*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000010 0x00000001 0x00000000
1846*8ae70af2SSvyatoslav Ryhel					0x0000000e 0x00000018 0x000000cb 0x00000200
1847*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000017 0x00000000 0x00000007
1848*8ae70af2SSvyatoslav Ryhel					0x00000008 0x000016da 0x0000000c 0x00000004
1849*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00005088 0xf0080191
1850*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00008008 0x00000008 0x00000008
1851*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000008 0x00000008 0x00000008
1852*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000000 0x00000000 0x00000000
1853*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1854*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1855*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1856*8ae70af2SSvyatoslav Ryhel					0x00000000 0x0000000a 0x0000000a 0x0000000a
1857*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x000002a0 0x0800013d 0x22220000
1858*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f501 0x07077404 0x54000000
1859*8ae70af2SSvyatoslav Ryhel					0x080001e8 0x08000021 0x00000802 0x00020000
1860*8ae70af2SSvyatoslav Ryhel					0x00000100 0x00fd000c 0xa0f10000 0x00000000
1861*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80002d93 0xe8000000 0xff00ff49 >;
1862*8ae70af2SSvyatoslav Ryhel			};
1863*8ae70af2SSvyatoslav Ryhel		};
1864*8ae70af2SSvyatoslav Ryhel
1865*8ae70af2SSvyatoslav Ryhel		emc-timings-2 {
1866*8ae70af2SSvyatoslav Ryhel			/* Micron 2GB 750 MHZ */
1867*8ae70af2SSvyatoslav Ryhel			nvidia,ram-code = <2>;
1868*8ae70af2SSvyatoslav Ryhel
1869*8ae70af2SSvyatoslav Ryhel			timing-51000000 {
1870*8ae70af2SSvyatoslav Ryhel				clock-frequency = <51000000>;
1871*8ae70af2SSvyatoslav Ryhel
1872*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1873*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1874*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200008>;
1875*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1876*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1877*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1878*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1879*8ae70af2SSvyatoslav Ryhel
1880*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000002
1881*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000001 0x00000000 0x00000002
1882*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1883*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1884*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1885*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000181 0x00000000 0x00000060
1886*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1887*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000009 0x00000009
1888*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000002 0x00000000 0x00000004
1889*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000018e 0x00000006 0x00000004
1890*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1891*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1892*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1893*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1894*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1895*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1896*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1897*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1898*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1899*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1900*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1901*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1902*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
1903*8ae70af2SSvyatoslav Ryhel			};
1904*8ae70af2SSvyatoslav Ryhel
1905*8ae70af2SSvyatoslav Ryhel			timing-102000000 {
1906*8ae70af2SSvyatoslav Ryhel				clock-frequency = <102000000>;
1907*8ae70af2SSvyatoslav Ryhel
1908*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1909*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1910*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1911*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1912*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1913*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1914*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1915*8ae70af2SSvyatoslav Ryhel
1916*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000004
1917*8ae70af2SSvyatoslav Ryhel					0x0000001e 0x00000003 0x00000001 0x00000002
1918*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000001
1919*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000003 0x00000001 0x00000000
1920*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x0000000a
1921*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000303 0x00000000 0x000000c0
1922*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1923*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000020 0x00000020
1924*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000004 0x00000000 0x00000004
1925*8ae70af2SSvyatoslav Ryhel					0x00000005 0x0000031c 0x00000006 0x00000004
1926*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1927*8ae70af2SSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1928*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1929*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1930*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1931*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1932*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1933*8ae70af2SSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1934*8ae70af2SSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1935*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1936*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1937*8ae70af2SSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1938*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
1939*8ae70af2SSvyatoslav Ryhel			};
1940*8ae70af2SSvyatoslav Ryhel
1941*8ae70af2SSvyatoslav Ryhel			timing-204000000 {
1942*8ae70af2SSvyatoslav Ryhel				clock-frequency = <204000000>;
1943*8ae70af2SSvyatoslav Ryhel
1944*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1945*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1946*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200048>;
1947*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1948*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1949*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1950*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1951*8ae70af2SSvyatoslav Ryhel
1952*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000009
1953*8ae70af2SSvyatoslav Ryhel					0x0000003d 0x00000007 0x00000002 0x00000002
1954*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000002
1955*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000003 0x00000001 0x00000000
1956*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000006 0x00000004 0x0000000a
1957*8ae70af2SSvyatoslav Ryhel					0x0000000b 0x00000607 0x00000000 0x00000181
1958*8ae70af2SSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1959*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000040 0x00000040
1960*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000007 0x00000000 0x00000004
1961*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000638 0x00000007 0x00000004
1962*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x004400a4
1963*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00080000 0x00080000 0x00080000
1964*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00080000 0x00080000 0x00080000
1965*8ae70af2SSvyatoslav Ryhel					0x00080000 0x00000000 0x00000000 0x00000000
1966*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1967*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1968*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1969*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00080000 0x00080000 0x00080000
1970*8ae70af2SSvyatoslav Ryhel					0x00080000 0x000002a0 0x0800211c 0x00000000
1971*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1972*8ae70af2SSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00020000
1973*8ae70af2SSvyatoslav Ryhel					0x00000100 0x000c000c 0xa0f10000 0x00000000
1974*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
1975*8ae70af2SSvyatoslav Ryhel			};
1976*8ae70af2SSvyatoslav Ryhel
1977*8ae70af2SSvyatoslav Ryhel			timing-375000000 {
1978*8ae70af2SSvyatoslav Ryhel				clock-frequency = <375000000>;
1979*8ae70af2SSvyatoslav Ryhel
1980*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1981*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1982*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200040>;
1983*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000521>;
1984*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1985*8ae70af2SSvyatoslav Ryhel
1986*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000011
1987*8ae70af2SSvyatoslav Ryhel					0x0000006f 0x0000000c 0x00000004 0x00000003
1988*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000002 0x0000000a 0x00000004
1989*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000002 0x00000001 0x00000000
1990*8ae70af2SSvyatoslav Ryhel					0x00000004 0x00000006 0x00000004 0x0000000a
1991*8ae70af2SSvyatoslav Ryhel					0x0000000c 0x00000b2d 0x00000000 0x000002cb
1992*8ae70af2SSvyatoslav Ryhel					0x00000001 0x00000008 0x00000001 0x00000000
1993*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000075 0x00000200
1994*8ae70af2SSvyatoslav Ryhel					0x00000004 0x0000000c 0x00000000 0x00000004
1995*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000b6d 0x00000000 0x00000004
1996*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00007088 0x00200084
1997*8ae70af2SSvyatoslav Ryhel					0x00008000 0x00044000 0x00044000 0x00044000
1998*8ae70af2SSvyatoslav Ryhel					0x00044000 0x00014000 0x00014000 0x00014000
1999*8ae70af2SSvyatoslav Ryhel					0x00014000 0x00000000 0x00000000 0x00000000
2000*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2001*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2002*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2003*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00048000 0x00048000 0x00048000
2004*8ae70af2SSvyatoslav Ryhel					0x00048000 0x000002a0 0x0800013d 0x00000000
2005*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f508 0x05057404 0x54000007
2006*8ae70af2SSvyatoslav Ryhel					0x080001e8 0x08000021 0x00000802 0x00020000
2007*8ae70af2SSvyatoslav Ryhel					0x00000100 0x0150000c 0xa0f10000 0x00000000
2008*8ae70af2SSvyatoslav Ryhel					0x00000000 0x8000174b 0xe8000000 0xff00ff89 >;
2009*8ae70af2SSvyatoslav Ryhel			};
2010*8ae70af2SSvyatoslav Ryhel
2011*8ae70af2SSvyatoslav Ryhel			timing-750000000 {
2012*8ae70af2SSvyatoslav Ryhel				clock-frequency = <750000000>;
2013*8ae70af2SSvyatoslav Ryhel
2014*8ae70af2SSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
2015*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
2016*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200058>;
2017*8ae70af2SSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000d71>;
2018*8ae70af2SSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
2019*8ae70af2SSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
2020*8ae70af2SSvyatoslav Ryhel
2021*8ae70af2SSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000023
2022*8ae70af2SSvyatoslav Ryhel					0x000000df 0x00000019 0x00000009 0x00000005
2023*8ae70af2SSvyatoslav Ryhel					0x0000000d 0x00000004 0x00000013 0x00000009
2024*8ae70af2SSvyatoslav Ryhel					0x00000009 0x00000006 0x00000001 0x00000000
2025*8ae70af2SSvyatoslav Ryhel					0x00000007 0x0000000b 0x00000009 0x0000000b
2026*8ae70af2SSvyatoslav Ryhel					0x00000011 0x0000169a 0x00000000 0x000005a6
2027*8ae70af2SSvyatoslav Ryhel					0x00000003 0x00000010 0x00000001 0x00000000
2028*8ae70af2SSvyatoslav Ryhel					0x0000000e 0x00000018 0x000000e9 0x00000200
2029*8ae70af2SSvyatoslav Ryhel					0x00000005 0x00000017 0x00000000 0x00000007
2030*8ae70af2SSvyatoslav Ryhel					0x00000008 0x000016da 0x0000000c 0x00000004
2031*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00005088 0xf0080191
2032*8ae70af2SSvyatoslav Ryhel					0x00008000 0x0000800a 0x0000000a 0x0000000a
2033*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x00000008 0x00000008 0x00000008
2034*8ae70af2SSvyatoslav Ryhel					0x00000008 0x00000000 0x00000000 0x00000000
2035*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2036*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2037*8ae70af2SSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
2038*8ae70af2SSvyatoslav Ryhel					0x00000000 0x007fc00a 0x0000000a 0x0000000a
2039*8ae70af2SSvyatoslav Ryhel					0x0000000a 0x000002a0 0x0800013d 0x22220000
2040*8ae70af2SSvyatoslav Ryhel					0x77fff884 0x01f1f501 0x07077404 0x54000000
2041*8ae70af2SSvyatoslav Ryhel					0x080001e8 0x08000021 0x00000802 0x00020000
2042*8ae70af2SSvyatoslav Ryhel					0x00000100 0x00df000c 0xa0f10000 0x00000000
2043*8ae70af2SSvyatoslav Ryhel					0x00000000 0x80002d93 0xf8000000 0xff00ff49 >;
2044*8ae70af2SSvyatoslav Ryhel			};
2045*8ae70af2SSvyatoslav Ryhel		};
2046*8ae70af2SSvyatoslav Ryhel	};
2047*8ae70af2SSvyatoslav Ryhel
2048*8ae70af2SSvyatoslav Ryhel	hda@70030000 {
2049*8ae70af2SSvyatoslav Ryhel		status = "okay";
2050*8ae70af2SSvyatoslav Ryhel	};
2051*8ae70af2SSvyatoslav Ryhel
2052*8ae70af2SSvyatoslav Ryhel	ahub@70080000 {
2053*8ae70af2SSvyatoslav Ryhel		i2s@70080400 {		/* i2s1 */
2054*8ae70af2SSvyatoslav Ryhel			status = "okay";
2055*8ae70af2SSvyatoslav Ryhel		};
2056*8ae70af2SSvyatoslav Ryhel
2057*8ae70af2SSvyatoslav Ryhel		/* BT SCO */
2058*8ae70af2SSvyatoslav Ryhel		i2s@70080600 {		/* i2s3 */
2059*8ae70af2SSvyatoslav Ryhel			status = "okay";
2060*8ae70af2SSvyatoslav Ryhel		};
2061*8ae70af2SSvyatoslav Ryhel	};
2062*8ae70af2SSvyatoslav Ryhel
2063*8ae70af2SSvyatoslav Ryhel	sdmmc1: mmc@78000000 {
2064*8ae70af2SSvyatoslav Ryhel		status = "okay";
2065*8ae70af2SSvyatoslav Ryhel		bus-width = <4>;
2066*8ae70af2SSvyatoslav Ryhel
2067*8ae70af2SSvyatoslav Ryhel		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
2068*8ae70af2SSvyatoslav Ryhel		power-gpios =  <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
2069*8ae70af2SSvyatoslav Ryhel
2070*8ae70af2SSvyatoslav Ryhel		vmmc-supply = <&vdd_3v3_sys>;
2071*8ae70af2SSvyatoslav Ryhel		vqmmc-supply = <&vddio_usd>;
2072*8ae70af2SSvyatoslav Ryhel	};
2073*8ae70af2SSvyatoslav Ryhel
2074*8ae70af2SSvyatoslav Ryhel	sdmmc3: mmc@78000400 {
2075*8ae70af2SSvyatoslav Ryhel		status = "okay";
2076*8ae70af2SSvyatoslav Ryhel
2077*8ae70af2SSvyatoslav Ryhel		#address-cells = <1>;
2078*8ae70af2SSvyatoslav Ryhel		#size-cells = <0>;
2079*8ae70af2SSvyatoslav Ryhel
2080*8ae70af2SSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
2081*8ae70af2SSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
2082*8ae70af2SSvyatoslav Ryhel		assigned-clock-rates = <50000000>;
2083*8ae70af2SSvyatoslav Ryhel
2084*8ae70af2SSvyatoslav Ryhel		max-frequency = <50000000>;
2085*8ae70af2SSvyatoslav Ryhel		keep-power-in-suspend;
2086*8ae70af2SSvyatoslav Ryhel		bus-width = <4>;
2087*8ae70af2SSvyatoslav Ryhel		non-removable;
2088*8ae70af2SSvyatoslav Ryhel
2089*8ae70af2SSvyatoslav Ryhel		mmc-pwrseq = <&brcm_wifi_pwrseq>;
2090*8ae70af2SSvyatoslav Ryhel		vmmc-supply = <&vdd_3v3_com>;
2091*8ae70af2SSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
2092*8ae70af2SSvyatoslav Ryhel
2093*8ae70af2SSvyatoslav Ryhel		/* Azurewave AW-NH665 BCM4330B1 */
2094*8ae70af2SSvyatoslav Ryhel		wifi@1 {
2095*8ae70af2SSvyatoslav Ryhel			compatible = "brcm,bcm4329-fmac";
2096*8ae70af2SSvyatoslav Ryhel			reg = <1>;
2097*8ae70af2SSvyatoslav Ryhel
2098*8ae70af2SSvyatoslav Ryhel			interrupt-parent = <&gpio>;
2099*8ae70af2SSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
2100*8ae70af2SSvyatoslav Ryhel			interrupt-names = "host-wake";
2101*8ae70af2SSvyatoslav Ryhel		};
2102*8ae70af2SSvyatoslav Ryhel	};
2103*8ae70af2SSvyatoslav Ryhel
2104*8ae70af2SSvyatoslav Ryhel	sdmmc4: mmc@78000600 {
2105*8ae70af2SSvyatoslav Ryhel		status = "okay";
2106*8ae70af2SSvyatoslav Ryhel		bus-width = <8>;
2107*8ae70af2SSvyatoslav Ryhel
2108*8ae70af2SSvyatoslav Ryhel		non-removable;
2109*8ae70af2SSvyatoslav Ryhel		mmc-ddr-1_8v;
2110*8ae70af2SSvyatoslav Ryhel
2111*8ae70af2SSvyatoslav Ryhel		vmmc-supply = <&vcore_emmc>;
2112*8ae70af2SSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
2113*8ae70af2SSvyatoslav Ryhel	};
2114*8ae70af2SSvyatoslav Ryhel
2115*8ae70af2SSvyatoslav Ryhel	/* USB via ASUS connector */
2116*8ae70af2SSvyatoslav Ryhel	usb@7d000000 {
2117*8ae70af2SSvyatoslav Ryhel		compatible = "nvidia,tegra30-udc";
2118*8ae70af2SSvyatoslav Ryhel		status = "okay";
2119*8ae70af2SSvyatoslav Ryhel		dr_mode = "peripheral";
2120*8ae70af2SSvyatoslav Ryhel	};
2121*8ae70af2SSvyatoslav Ryhel
2122*8ae70af2SSvyatoslav Ryhel	usb-phy@7d000000 {
2123*8ae70af2SSvyatoslav Ryhel		status = "okay";
2124*8ae70af2SSvyatoslav Ryhel		dr_mode = "peripheral";
2125*8ae70af2SSvyatoslav Ryhel		nvidia,hssync-start-delay = <0>;
2126*8ae70af2SSvyatoslav Ryhel		nvidia,xcvr-lsfslew = <2>;
2127*8ae70af2SSvyatoslav Ryhel		nvidia,xcvr-lsrslew = <2>;
2128*8ae70af2SSvyatoslav Ryhel		vbus-supply = <&vdd_5v0_sys>;
2129*8ae70af2SSvyatoslav Ryhel	};
2130*8ae70af2SSvyatoslav Ryhel
2131*8ae70af2SSvyatoslav Ryhel	/* Dock's USB port */
2132*8ae70af2SSvyatoslav Ryhel	usb@7d008000 {
2133*8ae70af2SSvyatoslav Ryhel		status = "okay";
2134*8ae70af2SSvyatoslav Ryhel	};
2135*8ae70af2SSvyatoslav Ryhel
2136*8ae70af2SSvyatoslav Ryhel	usb-phy@7d008000 {
2137*8ae70af2SSvyatoslav Ryhel		status = "okay";
2138*8ae70af2SSvyatoslav Ryhel		vbus-supply = <&vdd_5v0_bat>;
2139*8ae70af2SSvyatoslav Ryhel	};
2140*8ae70af2SSvyatoslav Ryhel
2141*8ae70af2SSvyatoslav Ryhel	backlight: backlight {
2142*8ae70af2SSvyatoslav Ryhel		compatible = "pwm-backlight";
2143*8ae70af2SSvyatoslav Ryhel
2144*8ae70af2SSvyatoslav Ryhel		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
2145*8ae70af2SSvyatoslav Ryhel		power-supply = <&vdd_5v0_bl>;
2146*8ae70af2SSvyatoslav Ryhel		pwms = <&pwm 0 71428>;
2147*8ae70af2SSvyatoslav Ryhel
2148*8ae70af2SSvyatoslav Ryhel		brightness-levels = <1 255>;
2149*8ae70af2SSvyatoslav Ryhel		num-interpolated-steps = <254>;
2150*8ae70af2SSvyatoslav Ryhel		default-brightness-level = <15>;
2151*8ae70af2SSvyatoslav Ryhel	};
2152*8ae70af2SSvyatoslav Ryhel
2153*8ae70af2SSvyatoslav Ryhel	pad_battery: battery-pad {
2154*8ae70af2SSvyatoslav Ryhel		compatible = "simple-battery";
2155*8ae70af2SSvyatoslav Ryhel		device-chemistry = "lithium-ion-polymer";
2156*8ae70af2SSvyatoslav Ryhel		charge-full-design-microamp-hours = <6760000>;
2157*8ae70af2SSvyatoslav Ryhel		energy-full-design-microwatt-hours = <25000000>;
2158*8ae70af2SSvyatoslav Ryhel		operating-range-celsius = <0 45>;
2159*8ae70af2SSvyatoslav Ryhel	};
2160*8ae70af2SSvyatoslav Ryhel
2161*8ae70af2SSvyatoslav Ryhel	dock_battery: battery-dock {
2162*8ae70af2SSvyatoslav Ryhel		compatible = "simple-battery";
2163*8ae70af2SSvyatoslav Ryhel		device-chemistry = "lithium-ion-polymer";
2164*8ae70af2SSvyatoslav Ryhel		charge-full-design-microamp-hours = <2980000>;
2165*8ae70af2SSvyatoslav Ryhel		energy-full-design-microwatt-hours = <22000000>;
2166*8ae70af2SSvyatoslav Ryhel		operating-range-celsius = <0 45>;
2167*8ae70af2SSvyatoslav Ryhel	};
2168*8ae70af2SSvyatoslav Ryhel
2169*8ae70af2SSvyatoslav Ryhel	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
2170*8ae70af2SSvyatoslav Ryhel	clk32k_in: clock-32k {
2171*8ae70af2SSvyatoslav Ryhel		compatible = "fixed-clock";
2172*8ae70af2SSvyatoslav Ryhel		#clock-cells = <0>;
2173*8ae70af2SSvyatoslav Ryhel		clock-frequency = <32768>;
2174*8ae70af2SSvyatoslav Ryhel		clock-output-names = "pmic-oscillator";
2175*8ae70af2SSvyatoslav Ryhel	};
2176*8ae70af2SSvyatoslav Ryhel
2177*8ae70af2SSvyatoslav Ryhel	cpus {
2178*8ae70af2SSvyatoslav Ryhel		cpu0: cpu@0 {
2179*8ae70af2SSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
2180*8ae70af2SSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
2181*8ae70af2SSvyatoslav Ryhel			#cooling-cells = <2>;
2182*8ae70af2SSvyatoslav Ryhel		};
2183*8ae70af2SSvyatoslav Ryhel		cpu1: cpu@1 {
2184*8ae70af2SSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
2185*8ae70af2SSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
2186*8ae70af2SSvyatoslav Ryhel			#cooling-cells = <2>;
2187*8ae70af2SSvyatoslav Ryhel		};
2188*8ae70af2SSvyatoslav Ryhel		cpu2: cpu@2 {
2189*8ae70af2SSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
2190*8ae70af2SSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
2191*8ae70af2SSvyatoslav Ryhel			#cooling-cells = <2>;
2192*8ae70af2SSvyatoslav Ryhel		};
2193*8ae70af2SSvyatoslav Ryhel		cpu3: cpu@3 {
2194*8ae70af2SSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
2195*8ae70af2SSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
2196*8ae70af2SSvyatoslav Ryhel			#cooling-cells = <2>;
2197*8ae70af2SSvyatoslav Ryhel		};
2198*8ae70af2SSvyatoslav Ryhel	};
2199*8ae70af2SSvyatoslav Ryhel
2200*8ae70af2SSvyatoslav Ryhel	extcon-keys {
2201*8ae70af2SSvyatoslav Ryhel		compatible = "gpio-keys";
2202*8ae70af2SSvyatoslav Ryhel
2203*8ae70af2SSvyatoslav Ryhel		switch-dock-hall-sensor {
2204*8ae70af2SSvyatoslav Ryhel			label = "Lid sensor";
2205*8ae70af2SSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>;
2206*8ae70af2SSvyatoslav Ryhel			linux,input-type = <EV_SW>;
2207*8ae70af2SSvyatoslav Ryhel			linux,code = <SW_LID>;
2208*8ae70af2SSvyatoslav Ryhel			debounce-interval = <500>;
2209*8ae70af2SSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
2210*8ae70af2SSvyatoslav Ryhel			wakeup-source;
2211*8ae70af2SSvyatoslav Ryhel		};
2212*8ae70af2SSvyatoslav Ryhel
2213*8ae70af2SSvyatoslav Ryhel		switch-lineout-detect {
2214*8ae70af2SSvyatoslav Ryhel			label = "Audio dock line-out detect";
2215*8ae70af2SSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
2216*8ae70af2SSvyatoslav Ryhel			linux,input-type = <EV_SW>;
2217*8ae70af2SSvyatoslav Ryhel			linux,code = <SW_LINEOUT_INSERT>;
2218*8ae70af2SSvyatoslav Ryhel			debounce-interval = <10>;
2219*8ae70af2SSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
2220*8ae70af2SSvyatoslav Ryhel			wakeup-source;
2221*8ae70af2SSvyatoslav Ryhel		};
2222*8ae70af2SSvyatoslav Ryhel	};
2223*8ae70af2SSvyatoslav Ryhel
2224*8ae70af2SSvyatoslav Ryhel	gpio-keys {
2225*8ae70af2SSvyatoslav Ryhel		compatible = "gpio-keys";
2226*8ae70af2SSvyatoslav Ryhel
2227*8ae70af2SSvyatoslav Ryhel		key-power {
2228*8ae70af2SSvyatoslav Ryhel			label = "Power";
2229*8ae70af2SSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
2230*8ae70af2SSvyatoslav Ryhel			linux,code = <KEY_POWER>;
2231*8ae70af2SSvyatoslav Ryhel			debounce-interval = <10>;
2232*8ae70af2SSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
2233*8ae70af2SSvyatoslav Ryhel			wakeup-source;
2234*8ae70af2SSvyatoslav Ryhel		};
2235*8ae70af2SSvyatoslav Ryhel
2236*8ae70af2SSvyatoslav Ryhel		key-volume-down {
2237*8ae70af2SSvyatoslav Ryhel			label = "Volume Down";
2238*8ae70af2SSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
2239*8ae70af2SSvyatoslav Ryhel			linux,code = <KEY_VOLUMEDOWN>;
2240*8ae70af2SSvyatoslav Ryhel			debounce-interval = <10>;
2241*8ae70af2SSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
2242*8ae70af2SSvyatoslav Ryhel			wakeup-source;
2243*8ae70af2SSvyatoslav Ryhel		};
2244*8ae70af2SSvyatoslav Ryhel
2245*8ae70af2SSvyatoslav Ryhel		key-volume-up {
2246*8ae70af2SSvyatoslav Ryhel			label = "Volume Up";
2247*8ae70af2SSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
2248*8ae70af2SSvyatoslav Ryhel			linux,code = <KEY_VOLUMEUP>;
2249*8ae70af2SSvyatoslav Ryhel			debounce-interval = <10>;
2250*8ae70af2SSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
2251*8ae70af2SSvyatoslav Ryhel			wakeup-source;
2252*8ae70af2SSvyatoslav Ryhel		};
2253*8ae70af2SSvyatoslav Ryhel	};
2254*8ae70af2SSvyatoslav Ryhel
2255*8ae70af2SSvyatoslav Ryhel	haptic-feedback {
2256*8ae70af2SSvyatoslav Ryhel		compatible = "gpio-vibrator";
2257*8ae70af2SSvyatoslav Ryhel		enable-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
2258*8ae70af2SSvyatoslav Ryhel		vcc-supply = <&vdd_3v3_sys>;
2259*8ae70af2SSvyatoslav Ryhel	};
2260*8ae70af2SSvyatoslav Ryhel
2261*8ae70af2SSvyatoslav Ryhel	opp-table-actmon {
2262*8ae70af2SSvyatoslav Ryhel		/delete-node/ opp-800000000;
2263*8ae70af2SSvyatoslav Ryhel		/delete-node/ opp-900000000;
2264*8ae70af2SSvyatoslav Ryhel	};
2265*8ae70af2SSvyatoslav Ryhel
2266*8ae70af2SSvyatoslav Ryhel	opp-table-emc {
2267*8ae70af2SSvyatoslav Ryhel		/delete-node/ opp-800000000-1300;
2268*8ae70af2SSvyatoslav Ryhel		/delete-node/ opp-900000000-1350;
2269*8ae70af2SSvyatoslav Ryhel	};
2270*8ae70af2SSvyatoslav Ryhel
2271*8ae70af2SSvyatoslav Ryhel	brcm_wifi_pwrseq: pwrseq-wifi {
2272*8ae70af2SSvyatoslav Ryhel		compatible = "mmc-pwrseq-simple";
2273*8ae70af2SSvyatoslav Ryhel
2274*8ae70af2SSvyatoslav Ryhel		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
2275*8ae70af2SSvyatoslav Ryhel		clock-names = "ext_clock";
2276*8ae70af2SSvyatoslav Ryhel
2277*8ae70af2SSvyatoslav Ryhel		reset-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
2278*8ae70af2SSvyatoslav Ryhel		post-power-on-delay-ms = <300>;
2279*8ae70af2SSvyatoslav Ryhel		power-off-delay-us = <300>;
2280*8ae70af2SSvyatoslav Ryhel	};
2281*8ae70af2SSvyatoslav Ryhel
2282*8ae70af2SSvyatoslav Ryhel	vdd_5v0_bat: regulator-bat {
2283*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2284*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_ac_bat";
2285*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
2286*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
2287*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2288*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2289*8ae70af2SSvyatoslav Ryhel	};
2290*8ae70af2SSvyatoslav Ryhel
2291*8ae70af2SSvyatoslav Ryhel	vdd_5v0_cp: regulator-sby {
2292*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2293*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_5v0_sby";
2294*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
2295*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
2296*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2297*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2298*8ae70af2SSvyatoslav Ryhel		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
2299*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2300*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
2301*8ae70af2SSvyatoslav Ryhel	};
2302*8ae70af2SSvyatoslav Ryhel
2303*8ae70af2SSvyatoslav Ryhel	vdd_5v0_sys: regulator-5v {
2304*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2305*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_5v0_sys";
2306*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
2307*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
2308*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2309*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2310*8ae70af2SSvyatoslav Ryhel		gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
2311*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2312*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
2313*8ae70af2SSvyatoslav Ryhel	};
2314*8ae70af2SSvyatoslav Ryhel
2315*8ae70af2SSvyatoslav Ryhel	vdd_1v5_ddr: regulator-ddr {
2316*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2317*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_ddr";
2318*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <1500000>;
2319*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <1500000>;
2320*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2321*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2322*8ae70af2SSvyatoslav Ryhel		gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
2323*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2324*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
2325*8ae70af2SSvyatoslav Ryhel	};
2326*8ae70af2SSvyatoslav Ryhel
2327*8ae70af2SSvyatoslav Ryhel	vdd_3v3_sys: regulator-3v {
2328*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2329*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_3v3_sys";
2330*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
2331*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
2332*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2333*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2334*8ae70af2SSvyatoslav Ryhel		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
2335*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2336*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
2337*8ae70af2SSvyatoslav Ryhel	};
2338*8ae70af2SSvyatoslav Ryhel
2339*8ae70af2SSvyatoslav Ryhel	vdd_3v3_com: regulator-com {
2340*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2341*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_3v3_com";
2342*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
2343*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
2344*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2345*8ae70af2SSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
2346*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2347*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_3v3_sys>;
2348*8ae70af2SSvyatoslav Ryhel	};
2349*8ae70af2SSvyatoslav Ryhel
2350*8ae70af2SSvyatoslav Ryhel	vdd_3v3_als: regulator-als {
2351*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2352*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_3v3_als";
2353*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
2354*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
2355*8ae70af2SSvyatoslav Ryhel		regulator-always-on;
2356*8ae70af2SSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
2357*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2358*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_3v3_sys>;
2359*8ae70af2SSvyatoslav Ryhel	};
2360*8ae70af2SSvyatoslav Ryhel
2361*8ae70af2SSvyatoslav Ryhel	vdd_5v0_bl: regulator-bl {
2362*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2363*8ae70af2SSvyatoslav Ryhel		regulator-name = "vdd_5v0_bl";
2364*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
2365*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
2366*8ae70af2SSvyatoslav Ryhel		regulator-boot-on;
2367*8ae70af2SSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
2368*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2369*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
2370*8ae70af2SSvyatoslav Ryhel	};
2371*8ae70af2SSvyatoslav Ryhel
2372*8ae70af2SSvyatoslav Ryhel	hdmi_5v0_sys: regulator-hdmi {
2373*8ae70af2SSvyatoslav Ryhel		compatible = "regulator-fixed";
2374*8ae70af2SSvyatoslav Ryhel		regulator-name = "hdmi_5v0_sys";
2375*8ae70af2SSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
2376*8ae70af2SSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
2377*8ae70af2SSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
2378*8ae70af2SSvyatoslav Ryhel		enable-active-high;
2379*8ae70af2SSvyatoslav Ryhel		vin-supply = <&vdd_5v0_sys>;
2380*8ae70af2SSvyatoslav Ryhel	};
2381*8ae70af2SSvyatoslav Ryhel
2382*8ae70af2SSvyatoslav Ryhel	sound {
2383*8ae70af2SSvyatoslav Ryhel		compatible = "asus,tegra-audio-rt5640-tf600t",
2384*8ae70af2SSvyatoslav Ryhel			     "nvidia,tegra-audio-rt5640";
2385*8ae70af2SSvyatoslav Ryhel		nvidia,model = "Asus VivoTab RT TF600T RT5640";
2386*8ae70af2SSvyatoslav Ryhel
2387*8ae70af2SSvyatoslav Ryhel		nvidia,audio-routing =
2388*8ae70af2SSvyatoslav Ryhel			"Headphones", "HPOR",
2389*8ae70af2SSvyatoslav Ryhel			"Headphones", "HPOL",
2390*8ae70af2SSvyatoslav Ryhel			"Speakers", "SPORP",
2391*8ae70af2SSvyatoslav Ryhel			"Speakers", "SPORN",
2392*8ae70af2SSvyatoslav Ryhel			"Speakers", "SPOLP",
2393*8ae70af2SSvyatoslav Ryhel			"Speakers", "SPOLN",
2394*8ae70af2SSvyatoslav Ryhel			"DMIC1", "Mic Jack";
2395*8ae70af2SSvyatoslav Ryhel
2396*8ae70af2SSvyatoslav Ryhel		nvidia,i2s-controller = <&tegra_i2s1>;
2397*8ae70af2SSvyatoslav Ryhel		nvidia,audio-codec = <&rt5640>;
2398*8ae70af2SSvyatoslav Ryhel
2399*8ae70af2SSvyatoslav Ryhel		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
2400*8ae70af2SSvyatoslav Ryhel		nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
2401*8ae70af2SSvyatoslav Ryhel		nvidia,coupled-mic-hp-det;
2402*8ae70af2SSvyatoslav Ryhel
2403*8ae70af2SSvyatoslav Ryhel		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
2404*8ae70af2SSvyatoslav Ryhel			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2405*8ae70af2SSvyatoslav Ryhel			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2406*8ae70af2SSvyatoslav Ryhel		clock-names = "pll_a", "pll_a_out0", "mclk";
2407*8ae70af2SSvyatoslav Ryhel
2408*8ae70af2SSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
2409*8ae70af2SSvyatoslav Ryhel				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
2410*8ae70af2SSvyatoslav Ryhel
2411*8ae70af2SSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2412*8ae70af2SSvyatoslav Ryhel					 <&tegra_car TEGRA30_CLK_EXTERN1>;
2413*8ae70af2SSvyatoslav Ryhel	};
2414*8ae70af2SSvyatoslav Ryhel
2415*8ae70af2SSvyatoslav Ryhel	thermal-zones {
2416*8ae70af2SSvyatoslav Ryhel		/*
2417*8ae70af2SSvyatoslav Ryhel		 * NCT72 has two sensors:
2418*8ae70af2SSvyatoslav Ryhel		 *
2419*8ae70af2SSvyatoslav Ryhel		 *	0: internal that monitors ambient/skin temperature
2420*8ae70af2SSvyatoslav Ryhel		 *	1: external that is connected to the CPU's diode
2421*8ae70af2SSvyatoslav Ryhel		 *
2422*8ae70af2SSvyatoslav Ryhel		 * Ideally we should use userspace thermal governor,
2423*8ae70af2SSvyatoslav Ryhel		 * but it's a much more complex solution.  The "skin"
2424*8ae70af2SSvyatoslav Ryhel		 * zone exists as a simpler solution which prevents
2425*8ae70af2SSvyatoslav Ryhel		 * Transformers from getting too hot from a user's
2426*8ae70af2SSvyatoslav Ryhel		 * tactile perspective. The CPU zone is intended to
2427*8ae70af2SSvyatoslav Ryhel		 * protect silicon from damage.
2428*8ae70af2SSvyatoslav Ryhel		 */
2429*8ae70af2SSvyatoslav Ryhel
2430*8ae70af2SSvyatoslav Ryhel		skin-thermal {
2431*8ae70af2SSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
2432*8ae70af2SSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
2433*8ae70af2SSvyatoslav Ryhel
2434*8ae70af2SSvyatoslav Ryhel			thermal-sensors = <&nct72 0>;
2435*8ae70af2SSvyatoslav Ryhel
2436*8ae70af2SSvyatoslav Ryhel			trips {
2437*8ae70af2SSvyatoslav Ryhel				trip0: skin-alert {
2438*8ae70af2SSvyatoslav Ryhel					/* throttle at 57C until temperature drops to 56.8C */
2439*8ae70af2SSvyatoslav Ryhel					temperature = <57000>;
2440*8ae70af2SSvyatoslav Ryhel					hysteresis = <200>;
2441*8ae70af2SSvyatoslav Ryhel					type = "passive";
2442*8ae70af2SSvyatoslav Ryhel				};
2443*8ae70af2SSvyatoslav Ryhel
2444*8ae70af2SSvyatoslav Ryhel				trip1: skin-crit {
2445*8ae70af2SSvyatoslav Ryhel					/* shut down at 65C */
2446*8ae70af2SSvyatoslav Ryhel					temperature = <65000>;
2447*8ae70af2SSvyatoslav Ryhel					hysteresis = <2000>;
2448*8ae70af2SSvyatoslav Ryhel					type = "critical";
2449*8ae70af2SSvyatoslav Ryhel				};
2450*8ae70af2SSvyatoslav Ryhel			};
2451*8ae70af2SSvyatoslav Ryhel
2452*8ae70af2SSvyatoslav Ryhel			cooling-maps {
2453*8ae70af2SSvyatoslav Ryhel				map0 {
2454*8ae70af2SSvyatoslav Ryhel					trip = <&trip0>;
2455*8ae70af2SSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2456*8ae70af2SSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2457*8ae70af2SSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2458*8ae70af2SSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2459*8ae70af2SSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
2460*8ae70af2SSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
2461*8ae70af2SSvyatoslav Ryhel				};
2462*8ae70af2SSvyatoslav Ryhel			};
2463*8ae70af2SSvyatoslav Ryhel		};
2464*8ae70af2SSvyatoslav Ryhel
2465*8ae70af2SSvyatoslav Ryhel		cpu-thermal {
2466*8ae70af2SSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
2467*8ae70af2SSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
2468*8ae70af2SSvyatoslav Ryhel
2469*8ae70af2SSvyatoslav Ryhel			thermal-sensors = <&nct72 1>;
2470*8ae70af2SSvyatoslav Ryhel
2471*8ae70af2SSvyatoslav Ryhel			trips {
2472*8ae70af2SSvyatoslav Ryhel				trip2: cpu-alert {
2473*8ae70af2SSvyatoslav Ryhel					/* throttle at 75C until temperature drops to 74.8C */
2474*8ae70af2SSvyatoslav Ryhel					temperature = <75000>;
2475*8ae70af2SSvyatoslav Ryhel					hysteresis = <200>;
2476*8ae70af2SSvyatoslav Ryhel					type = "passive";
2477*8ae70af2SSvyatoslav Ryhel				};
2478*8ae70af2SSvyatoslav Ryhel
2479*8ae70af2SSvyatoslav Ryhel				trip3: cpu-crit {
2480*8ae70af2SSvyatoslav Ryhel					/* shut down at 90C */
2481*8ae70af2SSvyatoslav Ryhel					temperature = <90000>;
2482*8ae70af2SSvyatoslav Ryhel					hysteresis = <2000>;
2483*8ae70af2SSvyatoslav Ryhel					type = "critical";
2484*8ae70af2SSvyatoslav Ryhel				};
2485*8ae70af2SSvyatoslav Ryhel			};
2486*8ae70af2SSvyatoslav Ryhel
2487*8ae70af2SSvyatoslav Ryhel			cooling-maps {
2488*8ae70af2SSvyatoslav Ryhel				map1 {
2489*8ae70af2SSvyatoslav Ryhel					trip = <&trip2>;
2490*8ae70af2SSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2491*8ae70af2SSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2492*8ae70af2SSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2493*8ae70af2SSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2494*8ae70af2SSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
2495*8ae70af2SSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
2496*8ae70af2SSvyatoslav Ryhel				};
2497*8ae70af2SSvyatoslav Ryhel			};
2498*8ae70af2SSvyatoslav Ryhel		};
2499*8ae70af2SSvyatoslav Ryhel	};
2500*8ae70af2SSvyatoslav Ryhel};
2501