xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra30-asus-p1801-t.dts (revision 115e74a29b530d121891238e9551c4bcdf7b04b5)
1*118a745eSSvyatoslav Ryhel// SPDX-License-Identifier: GPL-2.0
2*118a745eSSvyatoslav Ryhel/dts-v1/;
3*118a745eSSvyatoslav Ryhel
4*118a745eSSvyatoslav Ryhel#include <dt-bindings/input/gpio-keys.h>
5*118a745eSSvyatoslav Ryhel#include <dt-bindings/input/input.h>
6*118a745eSSvyatoslav Ryhel#include <dt-bindings/thermal/thermal.h>
7*118a745eSSvyatoslav Ryhel
8*118a745eSSvyatoslav Ryhel#include "tegra30.dtsi"
9*118a745eSSvyatoslav Ryhel#include "tegra30-cpu-opp.dtsi"
10*118a745eSSvyatoslav Ryhel#include "tegra30-cpu-opp-microvolt.dtsi"
11*118a745eSSvyatoslav Ryhel
12*118a745eSSvyatoslav Ryhel/ {
13*118a745eSSvyatoslav Ryhel	model = "Asus Portable AiO P1801-T";
14*118a745eSSvyatoslav Ryhel	compatible = "asus,p1801-t", "nvidia,tegra30";
15*118a745eSSvyatoslav Ryhel	chassis-type = "convertible";
16*118a745eSSvyatoslav Ryhel
17*118a745eSSvyatoslav Ryhel	aliases {
18*118a745eSSvyatoslav Ryhel		mmc0 = &sdmmc4; /* eMMC */
19*118a745eSSvyatoslav Ryhel		mmc1 = &sdmmc1; /* uSD slot */
20*118a745eSSvyatoslav Ryhel		mmc2 = &sdmmc3; /* WiFi */
21*118a745eSSvyatoslav Ryhel
22*118a745eSSvyatoslav Ryhel		rtc0 = &pmic;
23*118a745eSSvyatoslav Ryhel		rtc1 = "/rtc@7000e000";
24*118a745eSSvyatoslav Ryhel
25*118a745eSSvyatoslav Ryhel		display0 = &hdmi;
26*118a745eSSvyatoslav Ryhel
27*118a745eSSvyatoslav Ryhel		serial1 = &uartc; /* Bluetooth */
28*118a745eSSvyatoslav Ryhel		serial2 = &uartb; /* GPS */
29*118a745eSSvyatoslav Ryhel	};
30*118a745eSSvyatoslav Ryhel
31*118a745eSSvyatoslav Ryhel	/*
32*118a745eSSvyatoslav Ryhel	 * The decompressor and also some bootloaders rely on a
33*118a745eSSvyatoslav Ryhel	 * pre-existing /chosen node to be available to insert the
34*118a745eSSvyatoslav Ryhel	 * command line and merge other ATAGS info.
35*118a745eSSvyatoslav Ryhel	 */
36*118a745eSSvyatoslav Ryhel	chosen {};
37*118a745eSSvyatoslav Ryhel
38*118a745eSSvyatoslav Ryhel	firmware {
39*118a745eSSvyatoslav Ryhel		trusted-foundations {
40*118a745eSSvyatoslav Ryhel			compatible = "tlm,trusted-foundations";
41*118a745eSSvyatoslav Ryhel			tlm,version-major = <2>;
42*118a745eSSvyatoslav Ryhel			tlm,version-minor = <8>;
43*118a745eSSvyatoslav Ryhel		};
44*118a745eSSvyatoslav Ryhel	};
45*118a745eSSvyatoslav Ryhel
46*118a745eSSvyatoslav Ryhel	memory@80000000 {
47*118a745eSSvyatoslav Ryhel		reg = <0x80000000 0x80000000>;
48*118a745eSSvyatoslav Ryhel	};
49*118a745eSSvyatoslav Ryhel
50*118a745eSSvyatoslav Ryhel	reserved-memory {
51*118a745eSSvyatoslav Ryhel		#address-cells = <1>;
52*118a745eSSvyatoslav Ryhel		#size-cells = <1>;
53*118a745eSSvyatoslav Ryhel		ranges;
54*118a745eSSvyatoslav Ryhel
55*118a745eSSvyatoslav Ryhel		linux,cma@80000000 {
56*118a745eSSvyatoslav Ryhel			compatible = "shared-dma-pool";
57*118a745eSSvyatoslav Ryhel			alloc-ranges = <0x80000000 0x30000000>;
58*118a745eSSvyatoslav Ryhel			size = <0x10000000>;		/* 256MiB */
59*118a745eSSvyatoslav Ryhel			linux,cma-default;
60*118a745eSSvyatoslav Ryhel			reusable;
61*118a745eSSvyatoslav Ryhel		};
62*118a745eSSvyatoslav Ryhel
63*118a745eSSvyatoslav Ryhel		framebuffer@abe01000 {
64*118a745eSSvyatoslav Ryhel			reg = <0xabe01000 (1920 * 1080 * 4)>;
65*118a745eSSvyatoslav Ryhel			no-map;
66*118a745eSSvyatoslav Ryhel		};
67*118a745eSSvyatoslav Ryhel
68*118a745eSSvyatoslav Ryhel		trustzone@bfe00000 {
69*118a745eSSvyatoslav Ryhel			reg = <0xbfe00000 0x200000>;	/* 2MB */
70*118a745eSSvyatoslav Ryhel			no-map;
71*118a745eSSvyatoslav Ryhel		};
72*118a745eSSvyatoslav Ryhel
73*118a745eSSvyatoslav Ryhel		ramoops@fea00000 {
74*118a745eSSvyatoslav Ryhel			compatible = "ramoops";
75*118a745eSSvyatoslav Ryhel			reg = <0xfea00000 0x10000>;	/* 64kB */
76*118a745eSSvyatoslav Ryhel			console-size = <0x8000>;	/* 32kB */
77*118a745eSSvyatoslav Ryhel			record-size = <0x400>;		/*  1kB */
78*118a745eSSvyatoslav Ryhel			ecc-size = <16>;
79*118a745eSSvyatoslav Ryhel		};
80*118a745eSSvyatoslav Ryhel	};
81*118a745eSSvyatoslav Ryhel
82*118a745eSSvyatoslav Ryhel	host1x@50000000 {
83*118a745eSSvyatoslav Ryhel		hdmi: hdmi@54280000 {
84*118a745eSSvyatoslav Ryhel			status = "okay";
85*118a745eSSvyatoslav Ryhel
86*118a745eSSvyatoslav Ryhel			hdmi-supply = <&hdmi_5v0_sys>;
87*118a745eSSvyatoslav Ryhel			pll-supply = <&vdd_1v8_vio>;
88*118a745eSSvyatoslav Ryhel			vdd-supply = <&vdd_3v3_sys>;
89*118a745eSSvyatoslav Ryhel
90*118a745eSSvyatoslav Ryhel			port {
91*118a745eSSvyatoslav Ryhel				hdmi_out: endpoint {
92*118a745eSSvyatoslav Ryhel					remote-endpoint = <&bridge_in>;
93*118a745eSSvyatoslav Ryhel				};
94*118a745eSSvyatoslav Ryhel			};
95*118a745eSSvyatoslav Ryhel		};
96*118a745eSSvyatoslav Ryhel	};
97*118a745eSSvyatoslav Ryhel
98*118a745eSSvyatoslav Ryhel	gpio@6000d000 {
99*118a745eSSvyatoslav Ryhel		init-lpm-in-hog {
100*118a745eSSvyatoslav Ryhel			gpio-hog;
101*118a745eSSvyatoslav Ryhel			gpios = <TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
102*118a745eSSvyatoslav Ryhel			input;
103*118a745eSSvyatoslav Ryhel		};
104*118a745eSSvyatoslav Ryhel
105*118a745eSSvyatoslav Ryhel		init-lpm-out-hog {
106*118a745eSSvyatoslav Ryhel			gpio-hog;
107*118a745eSSvyatoslav Ryhel			gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
108*118a745eSSvyatoslav Ryhel				<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
109*118a745eSSvyatoslav Ryhel			output-low;
110*118a745eSSvyatoslav Ryhel		};
111*118a745eSSvyatoslav Ryhel
112*118a745eSSvyatoslav Ryhel		tp-vendor-hog {
113*118a745eSSvyatoslav Ryhel			gpio-hog;
114*118a745eSSvyatoslav Ryhel			gpios = <TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
115*118a745eSSvyatoslav Ryhel			input;
116*118a745eSSvyatoslav Ryhel		};
117*118a745eSSvyatoslav Ryhel	};
118*118a745eSSvyatoslav Ryhel
119*118a745eSSvyatoslav Ryhel	vde@6001a000 {
120*118a745eSSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
121*118a745eSSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
122*118a745eSSvyatoslav Ryhel		assigned-clock-rates = <408000000>;
123*118a745eSSvyatoslav Ryhel	};
124*118a745eSSvyatoslav Ryhel
125*118a745eSSvyatoslav Ryhel	pinmux@70000868 {
126*118a745eSSvyatoslav Ryhel		pinctrl-names = "default";
127*118a745eSSvyatoslav Ryhel		pinctrl-0 = <&state_default>;
128*118a745eSSvyatoslav Ryhel
129*118a745eSSvyatoslav Ryhel		state_default: pinmux {
130*118a745eSSvyatoslav Ryhel			/* SDMMC1 pinmux */
131*118a745eSSvyatoslav Ryhel			sdmmc1-clk {
132*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc1_clk_pz0";
133*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc1";
134*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
135*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
136*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
137*118a745eSSvyatoslav Ryhel			};
138*118a745eSSvyatoslav Ryhel			sdmmc1-cmd {
139*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc1_dat3_py4",
140*118a745eSSvyatoslav Ryhel					      "sdmmc1_dat2_py5",
141*118a745eSSvyatoslav Ryhel					      "sdmmc1_dat1_py6",
142*118a745eSSvyatoslav Ryhel					      "sdmmc1_dat0_py7",
143*118a745eSSvyatoslav Ryhel					      "sdmmc1_cmd_pz1";
144*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc1";
145*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
146*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
147*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148*118a745eSSvyatoslav Ryhel			};
149*118a745eSSvyatoslav Ryhel			sdmmc1-cd {
150*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_iordy_pi5";
151*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
152*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
153*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
154*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
155*118a745eSSvyatoslav Ryhel			};
156*118a745eSSvyatoslav Ryhel			sdmmc1-wp {
157*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d11_pt3";
158*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
159*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
160*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
161*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
162*118a745eSSvyatoslav Ryhel			};
163*118a745eSSvyatoslav Ryhel
164*118a745eSSvyatoslav Ryhel			/* SDMMC2 pinmux */
165*118a745eSSvyatoslav Ryhel			vi-d1-pd5 {
166*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d1_pd5",
167*118a745eSSvyatoslav Ryhel					      "vi_d2_pl0",
168*118a745eSSvyatoslav Ryhel					      "vi_d3_pl1",
169*118a745eSSvyatoslav Ryhel					      "vi_d5_pl3",
170*118a745eSSvyatoslav Ryhel					      "vi_d7_pl5";
171*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc2";
172*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
174*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
175*118a745eSSvyatoslav Ryhel			};
176*118a745eSSvyatoslav Ryhel			vi-d8-pl6 {
177*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d8_pl6",
178*118a745eSSvyatoslav Ryhel					      "vi_d9_pl7";
179*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc2";
180*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
182*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
183*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
184*118a745eSSvyatoslav Ryhel				nvidia,io-reset = <0>;
185*118a745eSSvyatoslav Ryhel			};
186*118a745eSSvyatoslav Ryhel
187*118a745eSSvyatoslav Ryhel			/* SDMMC3 pinmux */
188*118a745eSSvyatoslav Ryhel			sdmmc3-clk {
189*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc3_clk_pa6";
190*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc3";
191*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
193*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194*118a745eSSvyatoslav Ryhel			};
195*118a745eSSvyatoslav Ryhel			sdmmc3-cmd {
196*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc3_cmd_pa7",
197*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat0_pb7",
198*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat1_pb6",
199*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat2_pb5",
200*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat3_pb4",
201*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat4_pd1",
202*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat5_pd0",
203*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat6_pd3",
204*118a745eSSvyatoslav Ryhel					      "sdmmc3_dat7_pd4";
205*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc3";
206*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
207*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
208*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209*118a745eSSvyatoslav Ryhel			};
210*118a745eSSvyatoslav Ryhel
211*118a745eSSvyatoslav Ryhel			/* SDMMC4 pinmux */
212*118a745eSSvyatoslav Ryhel			sdmmc4-clk {
213*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_clk_pcc4";
214*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc4";
215*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
217*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218*118a745eSSvyatoslav Ryhel			};
219*118a745eSSvyatoslav Ryhel			sdmmc4-cmd {
220*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_cmd_pt7",
221*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat0_paa0",
222*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat1_paa1",
223*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat2_paa2",
224*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat3_paa3",
225*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat4_paa4",
226*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat5_paa5",
227*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat6_paa6",
228*118a745eSSvyatoslav Ryhel					      "sdmmc4_dat7_paa7";
229*118a745eSSvyatoslav Ryhel				nvidia,function = "sdmmc4";
230*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
231*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
232*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
233*118a745eSSvyatoslav Ryhel			};
234*118a745eSSvyatoslav Ryhel			sdmmc4-rst-n {
235*118a745eSSvyatoslav Ryhel				nvidia,pins = "sdmmc4_rst_n_pcc3";
236*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
237*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
239*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240*118a745eSSvyatoslav Ryhel			};
241*118a745eSSvyatoslav Ryhel			cam-mclk {
242*118a745eSSvyatoslav Ryhel				nvidia,pins = "cam_mclk_pcc0";
243*118a745eSSvyatoslav Ryhel				nvidia,function = "vi_alt3";
244*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
245*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
246*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247*118a745eSSvyatoslav Ryhel			};
248*118a745eSSvyatoslav Ryhel			drive-sdmmc4 {
249*118a745eSSvyatoslav Ryhel				nvidia,pins = "drive_gma",
250*118a745eSSvyatoslav Ryhel					      "drive_gmb",
251*118a745eSSvyatoslav Ryhel					      "drive_gmc",
252*118a745eSSvyatoslav Ryhel					      "drive_gmd";
253*118a745eSSvyatoslav Ryhel				nvidia,pull-down-strength = <9>;
254*118a745eSSvyatoslav Ryhel				nvidia,pull-up-strength = <9>;
255*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
256*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
257*118a745eSSvyatoslav Ryhel			};
258*118a745eSSvyatoslav Ryhel
259*118a745eSSvyatoslav Ryhel			/* I2C pinmux */
260*118a745eSSvyatoslav Ryhel			gen1-i2c {
261*118a745eSSvyatoslav Ryhel				nvidia,pins = "gen1_i2c_scl_pc4",
262*118a745eSSvyatoslav Ryhel					      "gen1_i2c_sda_pc5";
263*118a745eSSvyatoslav Ryhel				nvidia,function = "i2c1";
264*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
266*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267*118a745eSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
268*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
269*118a745eSSvyatoslav Ryhel			};
270*118a745eSSvyatoslav Ryhel			gen2-i2c {
271*118a745eSSvyatoslav Ryhel				nvidia,pins = "gen2_i2c_scl_pt5",
272*118a745eSSvyatoslav Ryhel					      "gen2_i2c_sda_pt6";
273*118a745eSSvyatoslav Ryhel				nvidia,function = "i2c2";
274*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
276*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
277*118a745eSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
278*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
279*118a745eSSvyatoslav Ryhel			};
280*118a745eSSvyatoslav Ryhel			cam-i2c {
281*118a745eSSvyatoslav Ryhel				nvidia,pins = "cam_i2c_scl_pbb1",
282*118a745eSSvyatoslav Ryhel					      "cam_i2c_sda_pbb2";
283*118a745eSSvyatoslav Ryhel				nvidia,function = "i2c3";
284*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
285*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
286*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
287*118a745eSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
288*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
289*118a745eSSvyatoslav Ryhel			};
290*118a745eSSvyatoslav Ryhel			ddc-i2c {
291*118a745eSSvyatoslav Ryhel				nvidia,pins = "ddc_scl_pv4",
292*118a745eSSvyatoslav Ryhel					      "ddc_sda_pv5";
293*118a745eSSvyatoslav Ryhel				nvidia,function = "i2c4";
294*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
296*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
297*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
298*118a745eSSvyatoslav Ryhel			};
299*118a745eSSvyatoslav Ryhel			pwr-i2c {
300*118a745eSSvyatoslav Ryhel				nvidia,pins = "pwr_i2c_scl_pz6",
301*118a745eSSvyatoslav Ryhel					      "pwr_i2c_sda_pz7";
302*118a745eSSvyatoslav Ryhel				nvidia,function = "i2cpwr";
303*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
304*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
305*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306*118a745eSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
307*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
308*118a745eSSvyatoslav Ryhel			};
309*118a745eSSvyatoslav Ryhel			hotplug-i2c {
310*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu4";
311*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
312*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
313*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
314*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315*118a745eSSvyatoslav Ryhel			};
316*118a745eSSvyatoslav Ryhel
317*118a745eSSvyatoslav Ryhel			/* HDMI pinmux */
318*118a745eSSvyatoslav Ryhel			hdmi-cec {
319*118a745eSSvyatoslav Ryhel				nvidia,pins = "hdmi_cec_pee3";
320*118a745eSSvyatoslav Ryhel				nvidia,function = "cec";
321*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
323*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
324*118a745eSSvyatoslav Ryhel				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
325*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
326*118a745eSSvyatoslav Ryhel			};
327*118a745eSSvyatoslav Ryhel			hdmi-hpd {
328*118a745eSSvyatoslav Ryhel				nvidia,pins = "hdmi_int_pn7";
329*118a745eSSvyatoslav Ryhel				nvidia,function = "hdmi";
330*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
332*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333*118a745eSSvyatoslav Ryhel			};
334*118a745eSSvyatoslav Ryhel
335*118a745eSSvyatoslav Ryhel			/* UART-A */
336*118a745eSSvyatoslav Ryhel			ulpi-data0-po1 {
337*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_data0_po1";
338*118a745eSSvyatoslav Ryhel				nvidia,function = "uarta";
339*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
340*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
341*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
342*118a745eSSvyatoslav Ryhel			};
343*118a745eSSvyatoslav Ryhel			ulpi-data1-po2 {
344*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_data1_po2";
345*118a745eSSvyatoslav Ryhel				nvidia,function = "uarta";
346*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
347*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
348*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
349*118a745eSSvyatoslav Ryhel			};
350*118a745eSSvyatoslav Ryhel			ulpi-data5-po6 {
351*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_data5_po6";
352*118a745eSSvyatoslav Ryhel				nvidia,function = "uarta";
353*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356*118a745eSSvyatoslav Ryhel			};
357*118a745eSSvyatoslav Ryhel			ulpi-data7-po0 {
358*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_data7_po0",
359*118a745eSSvyatoslav Ryhel					      "ulpi_data2_po3",
360*118a745eSSvyatoslav Ryhel					      "ulpi_data3_po4",
361*118a745eSSvyatoslav Ryhel					      "ulpi_data4_po5",
362*118a745eSSvyatoslav Ryhel					      "ulpi_data6_po7";
363*118a745eSSvyatoslav Ryhel				nvidia,function = "uarta";
364*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
366*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
367*118a745eSSvyatoslav Ryhel			};
368*118a745eSSvyatoslav Ryhel
369*118a745eSSvyatoslav Ryhel			/* UART-B */
370*118a745eSSvyatoslav Ryhel			uartb-txd-rts {
371*118a745eSSvyatoslav Ryhel				nvidia,pins = "uart2_txd_pc2",
372*118a745eSSvyatoslav Ryhel					      "uart2_rts_n_pj6";
373*118a745eSSvyatoslav Ryhel				nvidia,function = "uartb";
374*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
375*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
376*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377*118a745eSSvyatoslav Ryhel			};
378*118a745eSSvyatoslav Ryhel			uartb-rxd-cts {
379*118a745eSSvyatoslav Ryhel				nvidia,pins = "uart2_rxd_pc3",
380*118a745eSSvyatoslav Ryhel					      "uart2_cts_n_pj5";
381*118a745eSSvyatoslav Ryhel				nvidia,function = "uartb";
382*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
383*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
384*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
385*118a745eSSvyatoslav Ryhel			};
386*118a745eSSvyatoslav Ryhel
387*118a745eSSvyatoslav Ryhel			/* UART-C */
388*118a745eSSvyatoslav Ryhel			uartc-rxd-cts {
389*118a745eSSvyatoslav Ryhel				nvidia,pins = "uart3_cts_n_pa1",
390*118a745eSSvyatoslav Ryhel					      "uart3_rxd_pw7";
391*118a745eSSvyatoslav Ryhel				nvidia,function = "uartc";
392*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395*118a745eSSvyatoslav Ryhel			};
396*118a745eSSvyatoslav Ryhel			uartc-txd-rts {
397*118a745eSSvyatoslav Ryhel				nvidia,pins = "uart3_rts_n_pc0",
398*118a745eSSvyatoslav Ryhel					      "uart3_txd_pw6";
399*118a745eSSvyatoslav Ryhel				nvidia,function = "uartc";
400*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
401*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
402*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
403*118a745eSSvyatoslav Ryhel			};
404*118a745eSSvyatoslav Ryhel
405*118a745eSSvyatoslav Ryhel			/* UART-D */
406*118a745eSSvyatoslav Ryhel			ulpi-nxt-py2 {
407*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_nxt_py2";
408*118a745eSSvyatoslav Ryhel				nvidia,function = "uartd";
409*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
410*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
411*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
412*118a745eSSvyatoslav Ryhel			};
413*118a745eSSvyatoslav Ryhel			ulpi-clk-py0 {
414*118a745eSSvyatoslav Ryhel				nvidia,pins = "ulpi_clk_py0",
415*118a745eSSvyatoslav Ryhel					      "ulpi_dir_py1",
416*118a745eSSvyatoslav Ryhel					      "ulpi_stp_py3";
417*118a745eSSvyatoslav Ryhel				nvidia,function = "uartd";
418*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
419*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
420*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
421*118a745eSSvyatoslav Ryhel			};
422*118a745eSSvyatoslav Ryhel
423*118a745eSSvyatoslav Ryhel			/* I2S pinmux */
424*118a745eSSvyatoslav Ryhel			dap-i2s0 {
425*118a745eSSvyatoslav Ryhel				nvidia,pins = "dap1_fs_pn0",
426*118a745eSSvyatoslav Ryhel					      "dap1_din_pn1",
427*118a745eSSvyatoslav Ryhel					      "dap1_dout_pn2",
428*118a745eSSvyatoslav Ryhel					      "dap1_sclk_pn3";
429*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s0";
430*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
432*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
433*118a745eSSvyatoslav Ryhel			};
434*118a745eSSvyatoslav Ryhel			dap-i2s1 {
435*118a745eSSvyatoslav Ryhel				nvidia,pins = "dap2_fs_pa2",
436*118a745eSSvyatoslav Ryhel					      "dap2_sclk_pa3",
437*118a745eSSvyatoslav Ryhel					      "dap2_din_pa4",
438*118a745eSSvyatoslav Ryhel					      "dap2_dout_pa5";
439*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s1";
440*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
441*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
442*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
443*118a745eSSvyatoslav Ryhel			};
444*118a745eSSvyatoslav Ryhel			dap3-fs {
445*118a745eSSvyatoslav Ryhel				nvidia,pins = "dap3_fs_pp0",
446*118a745eSSvyatoslav Ryhel					      "dap3_din_pp1";
447*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s2";
448*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
449*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
450*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451*118a745eSSvyatoslav Ryhel			};
452*118a745eSSvyatoslav Ryhel			dap3-dout {
453*118a745eSSvyatoslav Ryhel				nvidia,pins = "dap3_dout_pp2",
454*118a745eSSvyatoslav Ryhel					      "dap3_sclk_pp3";
455*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s2";
456*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
457*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
458*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
459*118a745eSSvyatoslav Ryhel			};
460*118a745eSSvyatoslav Ryhel			dap-i2s3 {
461*118a745eSSvyatoslav Ryhel				nvidia,pins = "dap4_fs_pp4",
462*118a745eSSvyatoslav Ryhel					      "dap4_din_pp5",
463*118a745eSSvyatoslav Ryhel					      "dap4_dout_pp6",
464*118a745eSSvyatoslav Ryhel					      "dap4_sclk_pp7";
465*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s3";
466*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
468*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469*118a745eSSvyatoslav Ryhel			};
470*118a745eSSvyatoslav Ryhel
471*118a745eSSvyatoslav Ryhel			/* sensors pinmux */
472*118a745eSSvyatoslav Ryhel			nct-irq {
473*118a745eSSvyatoslav Ryhel				nvidia,pins = "pcc2";
474*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s4";
475*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
476*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
477*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
478*118a745eSSvyatoslav Ryhel			};
479*118a745eSSvyatoslav Ryhel
480*118a745eSSvyatoslav Ryhel			/* Asus EC pinmux */
481*118a745eSSvyatoslav Ryhel			ec-irqs {
482*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_row10_ps2",
483*118a745eSSvyatoslav Ryhel					      "kb_row15_ps7";
484*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
485*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
486*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
487*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
488*118a745eSSvyatoslav Ryhel			};
489*118a745eSSvyatoslav Ryhel			ec-reqs {
490*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_col1_pq1";
491*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
492*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
493*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
494*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495*118a745eSSvyatoslav Ryhel			};
496*118a745eSSvyatoslav Ryhel
497*118a745eSSvyatoslav Ryhel			/* memory type bootstrap */
498*118a745eSSvyatoslav Ryhel			mem-boostraps {
499*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad4_pg4",
500*118a745eSSvyatoslav Ryhel					      "gmi_ad5_pg5";
501*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
502*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
504*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505*118a745eSSvyatoslav Ryhel			};
506*118a745eSSvyatoslav Ryhel
507*118a745eSSvyatoslav Ryhel			/* PCI-e pinmux */
508*118a745eSSvyatoslav Ryhel			pex-l2-rst-n {
509*118a745eSSvyatoslav Ryhel				nvidia,pins = "pex_l2_rst_n_pcc6",
510*118a745eSSvyatoslav Ryhel					      "pex_l0_rst_n_pdd1",
511*118a745eSSvyatoslav Ryhel					      "pex_l1_rst_n_pdd5";
512*118a745eSSvyatoslav Ryhel				nvidia,function = "pcie";
513*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
514*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
515*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
516*118a745eSSvyatoslav Ryhel			};
517*118a745eSSvyatoslav Ryhel			pex-l2-clkreq-n {
518*118a745eSSvyatoslav Ryhel				nvidia,pins = "pex_l2_clkreq_n_pcc7",
519*118a745eSSvyatoslav Ryhel					      "pex_l0_prsnt_n_pdd0",
520*118a745eSSvyatoslav Ryhel					      "pex_l0_clkreq_n_pdd2",
521*118a745eSSvyatoslav Ryhel					      "pex_wake_n_pdd3",
522*118a745eSSvyatoslav Ryhel					      "pex_l1_prsnt_n_pdd4",
523*118a745eSSvyatoslav Ryhel					      "pex_l1_clkreq_n_pdd6",
524*118a745eSSvyatoslav Ryhel					      "pex_l2_prsnt_n_pdd7";
525*118a745eSSvyatoslav Ryhel				nvidia,function = "pcie";
526*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
527*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
528*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
529*118a745eSSvyatoslav Ryhel			};
530*118a745eSSvyatoslav Ryhel
531*118a745eSSvyatoslav Ryhel			/* SPI pinmux */
532*118a745eSSvyatoslav Ryhel			spi1-mosi-px4 {
533*118a745eSSvyatoslav Ryhel				nvidia,pins = "spi1_mosi_px4",
534*118a745eSSvyatoslav Ryhel					      "spi1_sck_px5",
535*118a745eSSvyatoslav Ryhel					      "spi1_cs0_n_px6",
536*118a745eSSvyatoslav Ryhel					      "spi1_miso_px7";
537*118a745eSSvyatoslav Ryhel				nvidia,function = "spi1";
538*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
539*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
540*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
541*118a745eSSvyatoslav Ryhel			};
542*118a745eSSvyatoslav Ryhel			spi2-cs1-n-pw2 {
543*118a745eSSvyatoslav Ryhel				nvidia,pins = "spi2_cs1_n_pw2";
544*118a745eSSvyatoslav Ryhel				nvidia,function = "spi2";
545*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
546*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
547*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
548*118a745eSSvyatoslav Ryhel			};
549*118a745eSSvyatoslav Ryhel			spi2-sck-px2 {
550*118a745eSSvyatoslav Ryhel				nvidia,pins = "spi2_sck_px2";
551*118a745eSSvyatoslav Ryhel				nvidia,function = "spi2";
552*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
553*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
554*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555*118a745eSSvyatoslav Ryhel			};
556*118a745eSSvyatoslav Ryhel			gmi-a17-pb0 {
557*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_a17_pb0",
558*118a745eSSvyatoslav Ryhel					      "gmi_a16_pj7";
559*118a745eSSvyatoslav Ryhel				nvidia,function = "spi4";
560*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
562*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
563*118a745eSSvyatoslav Ryhel			};
564*118a745eSSvyatoslav Ryhel			gmi-a18-pb1 {
565*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_a18_pb1";
566*118a745eSSvyatoslav Ryhel				nvidia,function = "spi4";
567*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
568*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
569*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570*118a745eSSvyatoslav Ryhel			};
571*118a745eSSvyatoslav Ryhel			gmi-a19-pk7 {
572*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_a19_pk7";
573*118a745eSSvyatoslav Ryhel				nvidia,function = "spi4";
574*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
576*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577*118a745eSSvyatoslav Ryhel			};
578*118a745eSSvyatoslav Ryhel
579*118a745eSSvyatoslav Ryhel			/* Display A pinmux */
580*118a745eSSvyatoslav Ryhel			lcd-pwr0-pb2 {
581*118a745eSSvyatoslav Ryhel				nvidia,pins = "lcd_pwr0_pb2",
582*118a745eSSvyatoslav Ryhel					      "lcd_pclk_pb3",
583*118a745eSSvyatoslav Ryhel					      "lcd_pwr1_pc1",
584*118a745eSSvyatoslav Ryhel					      "lcd_d0_pe0",
585*118a745eSSvyatoslav Ryhel					      "lcd_d1_pe1",
586*118a745eSSvyatoslav Ryhel					      "lcd_d2_pe2",
587*118a745eSSvyatoslav Ryhel					      "lcd_d3_pe3",
588*118a745eSSvyatoslav Ryhel					      "lcd_d4_pe4",
589*118a745eSSvyatoslav Ryhel					      "lcd_d5_pe5",
590*118a745eSSvyatoslav Ryhel					      "lcd_d6_pe6",
591*118a745eSSvyatoslav Ryhel					      "lcd_d7_pe7",
592*118a745eSSvyatoslav Ryhel					      "lcd_d8_pf0",
593*118a745eSSvyatoslav Ryhel					      "lcd_d9_pf1",
594*118a745eSSvyatoslav Ryhel					      "lcd_d10_pf2",
595*118a745eSSvyatoslav Ryhel					      "lcd_d11_pf3",
596*118a745eSSvyatoslav Ryhel					      "lcd_d12_pf4",
597*118a745eSSvyatoslav Ryhel					      "lcd_d13_pf5",
598*118a745eSSvyatoslav Ryhel					      "lcd_d14_pf6",
599*118a745eSSvyatoslav Ryhel					      "lcd_d15_pf7",
600*118a745eSSvyatoslav Ryhel					      "lcd_de_pj1",
601*118a745eSSvyatoslav Ryhel					      "lcd_hsync_pj3",
602*118a745eSSvyatoslav Ryhel					      "lcd_vsync_pj4",
603*118a745eSSvyatoslav Ryhel					      "lcd_d16_pm0",
604*118a745eSSvyatoslav Ryhel					      "lcd_d17_pm1",
605*118a745eSSvyatoslav Ryhel					      "lcd_d18_pm2",
606*118a745eSSvyatoslav Ryhel					      "lcd_d19_pm3",
607*118a745eSSvyatoslav Ryhel					      "lcd_d20_pm4",
608*118a745eSSvyatoslav Ryhel					      "lcd_d21_pm5",
609*118a745eSSvyatoslav Ryhel					      "lcd_d22_pm6",
610*118a745eSSvyatoslav Ryhel					      "lcd_d23_pm7",
611*118a745eSSvyatoslav Ryhel					      "lcd_dc0_pn6",
612*118a745eSSvyatoslav Ryhel					      "lcd_sdin_pz2";
613*118a745eSSvyatoslav Ryhel				nvidia,function = "displaya";
614*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
615*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
616*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
617*118a745eSSvyatoslav Ryhel			};
618*118a745eSSvyatoslav Ryhel			lcd-cs0-n-pn4 {
619*118a745eSSvyatoslav Ryhel				nvidia,pins = "lcd_cs0_n_pn4",
620*118a745eSSvyatoslav Ryhel					      "lcd_sdout_pn5",
621*118a745eSSvyatoslav Ryhel					      "lcd_wr_n_pz3";
622*118a745eSSvyatoslav Ryhel				nvidia,function = "displaya";
623*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
624*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
625*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
626*118a745eSSvyatoslav Ryhel			};
627*118a745eSSvyatoslav Ryhel
628*118a745eSSvyatoslav Ryhel			blink {
629*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk_32k_out_pa0";
630*118a745eSSvyatoslav Ryhel				nvidia,function = "blink";
631*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
632*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
633*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
634*118a745eSSvyatoslav Ryhel			};
635*118a745eSSvyatoslav Ryhel
636*118a745eSSvyatoslav Ryhel			/* KBC keys */
637*118a745eSSvyatoslav Ryhel			kb-col0-pq0 {
638*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_col0_pq0";
639*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
640*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
641*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
642*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
643*118a745eSSvyatoslav Ryhel			};
644*118a745eSSvyatoslav Ryhel			kb-col1-pq1 {
645*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_row1_pr1",
646*118a745eSSvyatoslav Ryhel					      "kb_row3_pr3",
647*118a745eSSvyatoslav Ryhel					      "kb_row14_ps6";
648*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
649*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
650*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
651*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
652*118a745eSSvyatoslav Ryhel			};
653*118a745eSSvyatoslav Ryhel			kb-col4-pq4 {
654*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_col4_pq4",
655*118a745eSSvyatoslav Ryhel					      "kb_col5_pq5",
656*118a745eSSvyatoslav Ryhel					      "kb_col7_pq7",
657*118a745eSSvyatoslav Ryhel					      "kb_row2_pr2",
658*118a745eSSvyatoslav Ryhel					      "kb_row4_pr4",
659*118a745eSSvyatoslav Ryhel					      "kb_row5_pr5",
660*118a745eSSvyatoslav Ryhel					      "kb_row12_ps4",
661*118a745eSSvyatoslav Ryhel					      "kb_row13_ps5";
662*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
663*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
664*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
665*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
666*118a745eSSvyatoslav Ryhel			};
667*118a745eSSvyatoslav Ryhel
668*118a745eSSvyatoslav Ryhel			gmi-wp-n-pc7 {
669*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_wp_n_pc7",
670*118a745eSSvyatoslav Ryhel					      "gmi_wait_pi7",
671*118a745eSSvyatoslav Ryhel					      "gmi_cs3_n_pk4";
672*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
673*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
674*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
675*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
676*118a745eSSvyatoslav Ryhel			};
677*118a745eSSvyatoslav Ryhel			gmi-cs0-n-pj0 {
678*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_cs0_n_pj0",
679*118a745eSSvyatoslav Ryhel					      "gmi_cs1_n_pj2",
680*118a745eSSvyatoslav Ryhel					      "gmi_cs2_n_pk3";
681*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
682*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
684*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
685*118a745eSSvyatoslav Ryhel			};
686*118a745eSSvyatoslav Ryhel			vi-pclk-pt0 {
687*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_pclk_pt0";
688*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
689*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
690*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
691*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
692*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
693*118a745eSSvyatoslav Ryhel				nvidia,io-reset = <0>;
694*118a745eSSvyatoslav Ryhel			};
695*118a745eSSvyatoslav Ryhel
696*118a745eSSvyatoslav Ryhel			/* GPIO keys pinmux */
697*118a745eSSvyatoslav Ryhel			power-key {
698*118a745eSSvyatoslav Ryhel				nvidia,pins = "pv0";
699*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
700*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
701*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
702*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
703*118a745eSSvyatoslav Ryhel			};
704*118a745eSSvyatoslav Ryhel			vol-keys {
705*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_col2_pq2",
706*118a745eSSvyatoslav Ryhel					      "kb_col3_pq3";
707*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
708*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
709*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
710*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
711*118a745eSSvyatoslav Ryhel			};
712*118a745eSSvyatoslav Ryhel
713*118a745eSSvyatoslav Ryhel			/* Bluetooth */
714*118a745eSSvyatoslav Ryhel			bt-shutdown {
715*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu0";
716*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
717*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
718*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
719*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
720*118a745eSSvyatoslav Ryhel			};
721*118a745eSSvyatoslav Ryhel			bt-dev-wake {
722*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu1";
723*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
724*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
725*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
726*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
727*118a745eSSvyatoslav Ryhel			};
728*118a745eSSvyatoslav Ryhel			bt-host-wake {
729*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu6";
730*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
731*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
732*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
733*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
734*118a745eSSvyatoslav Ryhel			};
735*118a745eSSvyatoslav Ryhel
736*118a745eSSvyatoslav Ryhel			pu2 {
737*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu2";
738*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd1";
739*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
740*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
741*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
742*118a745eSSvyatoslav Ryhel			};
743*118a745eSSvyatoslav Ryhel			pu3 {
744*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu3";
745*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
746*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
747*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
748*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
749*118a745eSSvyatoslav Ryhel			};
750*118a745eSSvyatoslav Ryhel			pcc1 {
751*118a745eSSvyatoslav Ryhel				nvidia,pins = "pcc1";
752*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
753*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
754*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
755*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
756*118a745eSSvyatoslav Ryhel			};
757*118a745eSSvyatoslav Ryhel			pv2 {
758*118a745eSSvyatoslav Ryhel				nvidia,pins = "pv2";
759*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
760*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
761*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
762*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763*118a745eSSvyatoslav Ryhel			};
764*118a745eSSvyatoslav Ryhel			pv3 {
765*118a745eSSvyatoslav Ryhel				nvidia,pins = "pv3";
766*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
767*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
768*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
769*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
770*118a745eSSvyatoslav Ryhel			};
771*118a745eSSvyatoslav Ryhel			vi-vsync-pd6 {
772*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_vsync_pd6",
773*118a745eSSvyatoslav Ryhel					      "vi_hsync_pd7";
774*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
775*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
776*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
777*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
778*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
779*118a745eSSvyatoslav Ryhel				nvidia,io-reset = <0>;
780*118a745eSSvyatoslav Ryhel			};
781*118a745eSSvyatoslav Ryhel			vi-d10-pt2 {
782*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d10_pt2",
783*118a745eSSvyatoslav Ryhel					      "vi_d0_pt4",
784*118a745eSSvyatoslav Ryhel					      "pbb0";
785*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd2";
786*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
787*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
788*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
789*118a745eSSvyatoslav Ryhel			};
790*118a745eSSvyatoslav Ryhel			kb-row0-pr0 {
791*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_row0_pr0";
792*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
793*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
794*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
795*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
796*118a745eSSvyatoslav Ryhel			};
797*118a745eSSvyatoslav Ryhel			gmi-ad0-pg0 {
798*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad0_pg0",
799*118a745eSSvyatoslav Ryhel					      "gmi_ad1_pg1",
800*118a745eSSvyatoslav Ryhel					      "gmi_ad2_pg2",
801*118a745eSSvyatoslav Ryhel					      "gmi_ad3_pg3",
802*118a745eSSvyatoslav Ryhel					      "gmi_ad6_pg6",
803*118a745eSSvyatoslav Ryhel					      "gmi_ad7_pg7",
804*118a745eSSvyatoslav Ryhel					      "gmi_wr_n_pi0",
805*118a745eSSvyatoslav Ryhel					      "gmi_oe_n_pi1",
806*118a745eSSvyatoslav Ryhel					      "gmi_dqs_pi2",
807*118a745eSSvyatoslav Ryhel					      "gmi_adv_n_pk0",
808*118a745eSSvyatoslav Ryhel					      "gmi_clk_pk1";
809*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
810*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
811*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
812*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
813*118a745eSSvyatoslav Ryhel			};
814*118a745eSSvyatoslav Ryhel			gmi-ad13-ph5 {
815*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad13_ph5";
816*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
817*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
818*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
819*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
820*118a745eSSvyatoslav Ryhel			};
821*118a745eSSvyatoslav Ryhel			gmi-ad10-ph2 {
822*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad10_ph2",
823*118a745eSSvyatoslav Ryhel					      "gmi_ad11_ph3",
824*118a745eSSvyatoslav Ryhel					      "gmi_ad14_ph6";
825*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
826*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
827*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
828*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
829*118a745eSSvyatoslav Ryhel			};
830*118a745eSSvyatoslav Ryhel			gmi-ad12-ph4 {
831*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad12_ph4",
832*118a745eSSvyatoslav Ryhel					      "gmi_rst_n_pi4";
833*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
834*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
835*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
836*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
837*118a745eSSvyatoslav Ryhel			};
838*118a745eSSvyatoslav Ryhel
839*118a745eSSvyatoslav Ryhel			/* USB2 VBUS control */
840*118a745eSSvyatoslav Ryhel			usb2-vbus-control {
841*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad15_ph7";
842*118a745eSSvyatoslav Ryhel				nvidia,function = "nand";
843*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
844*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
845*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
846*118a745eSSvyatoslav Ryhel			};
847*118a745eSSvyatoslav Ryhel
848*118a745eSSvyatoslav Ryhel			/* PWM pinmux */
849*118a745eSSvyatoslav Ryhel			pwm-0 {
850*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_ad8_ph0";
851*118a745eSSvyatoslav Ryhel				nvidia,function = "pwm0";
852*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
853*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
854*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
855*118a745eSSvyatoslav Ryhel			};
856*118a745eSSvyatoslav Ryhel			pwm-2 {
857*118a745eSSvyatoslav Ryhel				nvidia,pins = "pu5";
858*118a745eSSvyatoslav Ryhel				nvidia,function = "pwm2";
859*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
860*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
861*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
862*118a745eSSvyatoslav Ryhel			};
863*118a745eSSvyatoslav Ryhel
864*118a745eSSvyatoslav Ryhel			/* S/PDIF pinmux */
865*118a745eSSvyatoslav Ryhel			spdif-out {
866*118a745eSSvyatoslav Ryhel				nvidia,pins = "spdif_out_pk5";
867*118a745eSSvyatoslav Ryhel				nvidia,function = "spdif";
868*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
869*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
870*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
871*118a745eSSvyatoslav Ryhel			};
872*118a745eSSvyatoslav Ryhel			spdif-in {
873*118a745eSSvyatoslav Ryhel				nvidia,pins = "spdif_in_pk6";
874*118a745eSSvyatoslav Ryhel				nvidia,function = "spdif";
875*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
876*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
877*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
878*118a745eSSvyatoslav Ryhel			};
879*118a745eSSvyatoslav Ryhel			vi-d4-pl2 {
880*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d4_pl2";
881*118a745eSSvyatoslav Ryhel				nvidia,function = "vi";
882*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
883*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
884*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
885*118a745eSSvyatoslav Ryhel			};
886*118a745eSSvyatoslav Ryhel			vi-d6-pl4 {
887*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_d6_pl4";
888*118a745eSSvyatoslav Ryhel				nvidia,function = "vi";
889*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
890*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
891*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
892*118a745eSSvyatoslav Ryhel				nvidia,lock = <0>;
893*118a745eSSvyatoslav Ryhel				nvidia,io-reset = <0>;
894*118a745eSSvyatoslav Ryhel			};
895*118a745eSSvyatoslav Ryhel			vi-mclk-pt1 {
896*118a745eSSvyatoslav Ryhel				nvidia,pins = "vi_mclk_pt1";
897*118a745eSSvyatoslav Ryhel				nvidia,function = "vi";
898*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
899*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
900*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
901*118a745eSSvyatoslav Ryhel			};
902*118a745eSSvyatoslav Ryhel			jtag-rtck {
903*118a745eSSvyatoslav Ryhel				nvidia,pins = "jtag_rtck_pu7";
904*118a745eSSvyatoslav Ryhel				nvidia,function = "rtck";
905*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
906*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
907*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
908*118a745eSSvyatoslav Ryhel			};
909*118a745eSSvyatoslav Ryhel
910*118a745eSSvyatoslav Ryhel			crt-hsync-pv6 {
911*118a745eSSvyatoslav Ryhel				nvidia,pins = "crt_hsync_pv6",
912*118a745eSSvyatoslav Ryhel					      "crt_vsync_pv7";
913*118a745eSSvyatoslav Ryhel				nvidia,function = "crt";
914*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
915*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
916*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
917*118a745eSSvyatoslav Ryhel			};
918*118a745eSSvyatoslav Ryhel
919*118a745eSSvyatoslav Ryhel			clk1-out {
920*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk1_out_pw4";
921*118a745eSSvyatoslav Ryhel				nvidia,function = "extperiph1";
922*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
923*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
924*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
925*118a745eSSvyatoslav Ryhel			};
926*118a745eSSvyatoslav Ryhel			clk2-out {
927*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk2_out_pw5";
928*118a745eSSvyatoslav Ryhel				nvidia,function = "extperiph2";
929*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
930*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
931*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
932*118a745eSSvyatoslav Ryhel			};
933*118a745eSSvyatoslav Ryhel			clk3-out {
934*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk3_out_pee0";
935*118a745eSSvyatoslav Ryhel				nvidia,function = "extperiph3";
936*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
938*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939*118a745eSSvyatoslav Ryhel			};
940*118a745eSSvyatoslav Ryhel			sys-clk-req {
941*118a745eSSvyatoslav Ryhel				nvidia,pins = "sys_clk_req_pz5";
942*118a745eSSvyatoslav Ryhel				nvidia,function = "sysclk";
943*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
944*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
945*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
946*118a745eSSvyatoslav Ryhel			};
947*118a745eSSvyatoslav Ryhel			pbb4 {
948*118a745eSSvyatoslav Ryhel				nvidia,pins = "pbb4";
949*118a745eSSvyatoslav Ryhel				nvidia,function = "vgp4";
950*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
951*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
952*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
953*118a745eSSvyatoslav Ryhel			};
954*118a745eSSvyatoslav Ryhel			pbb5 {
955*118a745eSSvyatoslav Ryhel				nvidia,pins = "pbb5";
956*118a745eSSvyatoslav Ryhel				nvidia,function = "vgp5";
957*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
958*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
959*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
960*118a745eSSvyatoslav Ryhel			};
961*118a745eSSvyatoslav Ryhel			pbb6 {
962*118a745eSSvyatoslav Ryhel				nvidia,pins = "pbb6";
963*118a745eSSvyatoslav Ryhel				nvidia,function = "vgp6";
964*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
965*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
966*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
967*118a745eSSvyatoslav Ryhel			};
968*118a745eSSvyatoslav Ryhel			clk2-req-pcc5 {
969*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk2_req_pcc5",
970*118a745eSSvyatoslav Ryhel					      "clk1_req_pee2";
971*118a745eSSvyatoslav Ryhel				nvidia,function = "dap";
972*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
973*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
974*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
975*118a745eSSvyatoslav Ryhel			};
976*118a745eSSvyatoslav Ryhel			clk3-req-pee1 {
977*118a745eSSvyatoslav Ryhel				nvidia,pins = "clk3_req_pee1";
978*118a745eSSvyatoslav Ryhel				nvidia,function = "dev3";
979*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
981*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982*118a745eSSvyatoslav Ryhel			};
983*118a745eSSvyatoslav Ryhel			owr {
984*118a745eSSvyatoslav Ryhel				nvidia,pins = "owr";
985*118a745eSSvyatoslav Ryhel				nvidia,function = "owr";
986*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
987*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
988*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
989*118a745eSSvyatoslav Ryhel			};
990*118a745eSSvyatoslav Ryhel
991*118a745eSSvyatoslav Ryhel			/* P1801-T specific pinmux */
992*118a745eSSvyatoslav Ryhel			lcd-pwr2 {
993*118a745eSSvyatoslav Ryhel				nvidia,pins = "lcd_pwr2_pc6",
994*118a745eSSvyatoslav Ryhel					      "lcd_dc1_pd2";
995*118a745eSSvyatoslav Ryhel				nvidia,function = "displaya";
996*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
997*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
998*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
999*118a745eSSvyatoslav Ryhel			};
1000*118a745eSSvyatoslav Ryhel			lcd-m1 {
1001*118a745eSSvyatoslav Ryhel				nvidia,pins = "lcd_m1_pw1";
1002*118a745eSSvyatoslav Ryhel				nvidia,function = "displaya";
1003*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1004*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1005*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006*118a745eSSvyatoslav Ryhel			};
1007*118a745eSSvyatoslav Ryhel			key-mode {
1008*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_cs4_n_pk2";
1009*118a745eSSvyatoslav Ryhel				nvidia,function = "rsvd4";
1010*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1011*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1012*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1013*118a745eSSvyatoslav Ryhel			};
1014*118a745eSSvyatoslav Ryhel			splashtop {
1015*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_cs6_n_pi3";
1016*118a745eSSvyatoslav Ryhel				nvidia,function = "nand_alt";
1017*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1018*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1019*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1020*118a745eSSvyatoslav Ryhel			};
1021*118a745eSSvyatoslav Ryhel			w8-detect {
1022*118a745eSSvyatoslav Ryhel				nvidia,pins = "gmi_cs7_n_pi6";
1023*118a745eSSvyatoslav Ryhel				nvidia,function = "nand_alt";
1024*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1025*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1026*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1027*118a745eSSvyatoslav Ryhel			};
1028*118a745eSSvyatoslav Ryhel			pbb3 {
1029*118a745eSSvyatoslav Ryhel				nvidia,pins = "pbb3";
1030*118a745eSSvyatoslav Ryhel				nvidia,function = "vgp3";
1031*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1032*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1033*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1034*118a745eSSvyatoslav Ryhel			};
1035*118a745eSSvyatoslav Ryhel			pbb7 {
1036*118a745eSSvyatoslav Ryhel				nvidia,pins = "pbb7";
1037*118a745eSSvyatoslav Ryhel				nvidia,function = "i2s4";
1038*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1039*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1040*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1041*118a745eSSvyatoslav Ryhel			};
1042*118a745eSSvyatoslav Ryhel			spi2-mosi-px0 {
1043*118a745eSSvyatoslav Ryhel				nvidia,pins = "spi2_mosi_px0";
1044*118a745eSSvyatoslav Ryhel				nvidia,function = "spi6";
1045*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1046*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1047*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1048*118a745eSSvyatoslav Ryhel			};
1049*118a745eSSvyatoslav Ryhel			tp-vendor {
1050*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_row6_pr6",
1051*118a745eSSvyatoslav Ryhel					      "kb_row7_pr7";
1052*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
1053*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_UP>;
1054*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1055*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1056*118a745eSSvyatoslav Ryhel			};
1057*118a745eSSvyatoslav Ryhel			tp-power {
1058*118a745eSSvyatoslav Ryhel				nvidia,pins = "kb_row8_ps0";
1059*118a745eSSvyatoslav Ryhel				nvidia,function = "kbc";
1060*118a745eSSvyatoslav Ryhel				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1061*118a745eSSvyatoslav Ryhel				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1062*118a745eSSvyatoslav Ryhel				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1063*118a745eSSvyatoslav Ryhel			};
1064*118a745eSSvyatoslav Ryhel
1065*118a745eSSvyatoslav Ryhel			/* GPIO power/drive control */
1066*118a745eSSvyatoslav Ryhel			drive-dap1 {
1067*118a745eSSvyatoslav Ryhel				nvidia,pins = "drive_dap1",
1068*118a745eSSvyatoslav Ryhel					      "drive_dap2",
1069*118a745eSSvyatoslav Ryhel					      "drive_dbg",
1070*118a745eSSvyatoslav Ryhel					      "drive_at5",
1071*118a745eSSvyatoslav Ryhel					      "drive_gme",
1072*118a745eSSvyatoslav Ryhel					      "drive_ddc",
1073*118a745eSSvyatoslav Ryhel					      "drive_ao1",
1074*118a745eSSvyatoslav Ryhel					      "drive_uart3";
1075*118a745eSSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1076*118a745eSSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1077*118a745eSSvyatoslav Ryhel				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1078*118a745eSSvyatoslav Ryhel				nvidia,pull-down-strength = <31>;
1079*118a745eSSvyatoslav Ryhel				nvidia,pull-up-strength = <31>;
1080*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1081*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1082*118a745eSSvyatoslav Ryhel			};
1083*118a745eSSvyatoslav Ryhel			drive-sdio1 {
1084*118a745eSSvyatoslav Ryhel				nvidia,pins = "drive_sdio1",
1085*118a745eSSvyatoslav Ryhel					      "drive_sdio3";
1086*118a745eSSvyatoslav Ryhel				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1087*118a745eSSvyatoslav Ryhel				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1088*118a745eSSvyatoslav Ryhel				nvidia,pull-down-strength = <46>;
1089*118a745eSSvyatoslav Ryhel				nvidia,pull-up-strength = <42>;
1090*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1091*118a745eSSvyatoslav Ryhel				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1092*118a745eSSvyatoslav Ryhel			};
1093*118a745eSSvyatoslav Ryhel		};
1094*118a745eSSvyatoslav Ryhel	};
1095*118a745eSSvyatoslav Ryhel
1096*118a745eSSvyatoslav Ryhel	uartb: serial@70006040 {
1097*118a745eSSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
1098*118a745eSSvyatoslav Ryhel		reset-names = "serial";
1099*118a745eSSvyatoslav Ryhel		/delete-property/ reg-shift;
1100*118a745eSSvyatoslav Ryhel		status = "okay";
1101*118a745eSSvyatoslav Ryhel
1102*118a745eSSvyatoslav Ryhel		/* Broadcom GPS BCM47511 */
1103*118a745eSSvyatoslav Ryhel	};
1104*118a745eSSvyatoslav Ryhel
1105*118a745eSSvyatoslav Ryhel	uartc: serial@70006200 {
1106*118a745eSSvyatoslav Ryhel		compatible = "nvidia,tegra30-hsuart";
1107*118a745eSSvyatoslav Ryhel		reset-names = "serial";
1108*118a745eSSvyatoslav Ryhel		/delete-property/ reg-shift;
1109*118a745eSSvyatoslav Ryhel		status = "okay";
1110*118a745eSSvyatoslav Ryhel
1111*118a745eSSvyatoslav Ryhel		/* Azurewave AW-AH691 BCM43241B0 */
1112*118a745eSSvyatoslav Ryhel	};
1113*118a745eSSvyatoslav Ryhel
1114*118a745eSSvyatoslav Ryhel	pwm: pwm@7000a000 {
1115*118a745eSSvyatoslav Ryhel		status = "okay";
1116*118a745eSSvyatoslav Ryhel	};
1117*118a745eSSvyatoslav Ryhel
1118*118a745eSSvyatoslav Ryhel	i2c@7000c000 {
1119*118a745eSSvyatoslav Ryhel		status = "okay";
1120*118a745eSSvyatoslav Ryhel		clock-frequency = <280000>;
1121*118a745eSSvyatoslav Ryhel	};
1122*118a745eSSvyatoslav Ryhel
1123*118a745eSSvyatoslav Ryhel	i2c@7000c400 {
1124*118a745eSSvyatoslav Ryhel		status = "okay";
1125*118a745eSSvyatoslav Ryhel		clock-frequency = <400000>;
1126*118a745eSSvyatoslav Ryhel
1127*118a745eSSvyatoslav Ryhel		/* Nuvoton NPCE791LA0DX embedded controller */
1128*118a745eSSvyatoslav Ryhel	};
1129*118a745eSSvyatoslav Ryhel
1130*118a745eSSvyatoslav Ryhel	i2c@7000c500 {
1131*118a745eSSvyatoslav Ryhel		status = "okay";
1132*118a745eSSvyatoslav Ryhel		clock-frequency = <100000>;
1133*118a745eSSvyatoslav Ryhel
1134*118a745eSSvyatoslav Ryhel		accelerometer@f {
1135*118a745eSSvyatoslav Ryhel			compatible = "kionix,kxtf9";
1136*118a745eSSvyatoslav Ryhel			reg = <0x0f>;
1137*118a745eSSvyatoslav Ryhel
1138*118a745eSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1139*118a745eSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1140*118a745eSSvyatoslav Ryhel
1141*118a745eSSvyatoslav Ryhel			vdd-supply = <&vdd_1v8_vio>;
1142*118a745eSSvyatoslav Ryhel			vddio-supply = <&vdd_1v8_vio>;
1143*118a745eSSvyatoslav Ryhel
1144*118a745eSSvyatoslav Ryhel			mount-matrix = "0", "1", "0",
1145*118a745eSSvyatoslav Ryhel				       "1", "0", "0",
1146*118a745eSSvyatoslav Ryhel				       "0", "0", "1";
1147*118a745eSSvyatoslav Ryhel		};
1148*118a745eSSvyatoslav Ryhel	};
1149*118a745eSSvyatoslav Ryhel
1150*118a745eSSvyatoslav Ryhel	hdmi_ddc: i2c@7000c700 {
1151*118a745eSSvyatoslav Ryhel		status = "okay";
1152*118a745eSSvyatoslav Ryhel		clock-frequency = <33000>;
1153*118a745eSSvyatoslav Ryhel	};
1154*118a745eSSvyatoslav Ryhel
1155*118a745eSSvyatoslav Ryhel	i2c@7000d000 {
1156*118a745eSSvyatoslav Ryhel		status = "okay";
1157*118a745eSSvyatoslav Ryhel		clock-frequency = <400000>;
1158*118a745eSSvyatoslav Ryhel
1159*118a745eSSvyatoslav Ryhel		rt5640: audio-codec@1c {
1160*118a745eSSvyatoslav Ryhel			compatible = "realtek,rt5640";
1161*118a745eSSvyatoslav Ryhel			reg = <0x1c>;
1162*118a745eSSvyatoslav Ryhel
1163*118a745eSSvyatoslav Ryhel			realtek,dmic1-data-pin = <1>;
1164*118a745eSSvyatoslav Ryhel
1165*118a745eSSvyatoslav Ryhel			clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1166*118a745eSSvyatoslav Ryhel			clock-names = "mclk";
1167*118a745eSSvyatoslav Ryhel
1168*118a745eSSvyatoslav Ryhel			realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_HIGH>;
1169*118a745eSSvyatoslav Ryhel		};
1170*118a745eSSvyatoslav Ryhel
1171*118a745eSSvyatoslav Ryhel		/* Texas Instruments TPS659110 PMIC */
1172*118a745eSSvyatoslav Ryhel		pmic: pmic@2d {
1173*118a745eSSvyatoslav Ryhel			compatible = "ti,tps65911";
1174*118a745eSSvyatoslav Ryhel			reg = <0x2d>;
1175*118a745eSSvyatoslav Ryhel
1176*118a745eSSvyatoslav Ryhel			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1177*118a745eSSvyatoslav Ryhel			#interrupt-cells = <2>;
1178*118a745eSSvyatoslav Ryhel			interrupt-controller;
1179*118a745eSSvyatoslav Ryhel			wakeup-source;
1180*118a745eSSvyatoslav Ryhel
1181*118a745eSSvyatoslav Ryhel			ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1182*118a745eSSvyatoslav Ryhel			ti,system-power-controller;
1183*118a745eSSvyatoslav Ryhel			ti,sleep-keep-ck32k;
1184*118a745eSSvyatoslav Ryhel			ti,sleep-enable;
1185*118a745eSSvyatoslav Ryhel
1186*118a745eSSvyatoslav Ryhel			#gpio-cells = <2>;
1187*118a745eSSvyatoslav Ryhel			gpio-controller;
1188*118a745eSSvyatoslav Ryhel
1189*118a745eSSvyatoslav Ryhel			vcc1-supply = <&vdd_5v0_bat>;
1190*118a745eSSvyatoslav Ryhel			vcc2-supply = <&vdd_5v0_bat>;
1191*118a745eSSvyatoslav Ryhel			vcc3-supply = <&vdd_1v8_vio>;
1192*118a745eSSvyatoslav Ryhel			vcc4-supply = <&vdd_5v0_bat>;
1193*118a745eSSvyatoslav Ryhel			vcc5-supply = <&vdd_5v0_bat>;
1194*118a745eSSvyatoslav Ryhel			vcc6-supply = <&vddio_ddr>;
1195*118a745eSSvyatoslav Ryhel			vcc7-supply = <&vdd_5v0_bat>;
1196*118a745eSSvyatoslav Ryhel			vccio-supply = <&vdd_5v0_bat>;
1197*118a745eSSvyatoslav Ryhel
1198*118a745eSSvyatoslav Ryhel			pmic-sleep-hog {
1199*118a745eSSvyatoslav Ryhel				gpio-hog;
1200*118a745eSSvyatoslav Ryhel				gpios = <2 GPIO_ACTIVE_HIGH>;
1201*118a745eSSvyatoslav Ryhel				output-high;
1202*118a745eSSvyatoslav Ryhel			};
1203*118a745eSSvyatoslav Ryhel
1204*118a745eSSvyatoslav Ryhel			regulators {
1205*118a745eSSvyatoslav Ryhel				/* vdd1 is not used by Portable AiO */
1206*118a745eSSvyatoslav Ryhel
1207*118a745eSSvyatoslav Ryhel				vddio_ddr: vdd2 {
1208*118a745eSSvyatoslav Ryhel					regulator-name = "vddio_ddr";
1209*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1210*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1211*118a745eSSvyatoslav Ryhel					regulator-always-on;
1212*118a745eSSvyatoslav Ryhel					regulator-boot-on;
1213*118a745eSSvyatoslav Ryhel				};
1214*118a745eSSvyatoslav Ryhel
1215*118a745eSSvyatoslav Ryhel				vdd_cpu: vddctrl {
1216*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_cpu,vdd_sys";
1217*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <600000>;
1218*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1400000>;
1219*118a745eSSvyatoslav Ryhel					regulator-coupled-with = <&vdd_core>;
1220*118a745eSSvyatoslav Ryhel					regulator-coupled-max-spread = <300000>;
1221*118a745eSSvyatoslav Ryhel					regulator-max-step-microvolt = <100000>;
1222*118a745eSSvyatoslav Ryhel					regulator-always-on;
1223*118a745eSSvyatoslav Ryhel					regulator-boot-on;
1224*118a745eSSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <1>;
1225*118a745eSSvyatoslav Ryhel
1226*118a745eSSvyatoslav Ryhel					nvidia,tegra-cpu-regulator;
1227*118a745eSSvyatoslav Ryhel				};
1228*118a745eSSvyatoslav Ryhel
1229*118a745eSSvyatoslav Ryhel				vdd_1v8_vio: vio {
1230*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_1v8_gen";
1231*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1500000>;
1232*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <3300000>;
1233*118a745eSSvyatoslav Ryhel					regulator-always-on;
1234*118a745eSSvyatoslav Ryhel					regulator-boot-on;
1235*118a745eSSvyatoslav Ryhel				};
1236*118a745eSSvyatoslav Ryhel
1237*118a745eSSvyatoslav Ryhel				/* eMMC VDD */
1238*118a745eSSvyatoslav Ryhel				vcore_emmc: ldo1 {
1239*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_emmc_core";
1240*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1000000>;
1241*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <3300000>;
1242*118a745eSSvyatoslav Ryhel					regulator-always-on;
1243*118a745eSSvyatoslav Ryhel				};
1244*118a745eSSvyatoslav Ryhel
1245*118a745eSSvyatoslav Ryhel				/* uSD slot VDD */
1246*118a745eSSvyatoslav Ryhel				vdd_usd: ldo2 {
1247*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_usd";
1248*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <3100000>;
1249*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <3100000>;
1250*118a745eSSvyatoslav Ryhel					regulator-always-on;
1251*118a745eSSvyatoslav Ryhel				};
1252*118a745eSSvyatoslav Ryhel
1253*118a745eSSvyatoslav Ryhel				/* uSD slot VDDIO */
1254*118a745eSSvyatoslav Ryhel				vddio_usd: ldo3 {
1255*118a745eSSvyatoslav Ryhel					regulator-name = "vddio_usd";
1256*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1800000>;
1257*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <3100000>;
1258*118a745eSSvyatoslav Ryhel				};
1259*118a745eSSvyatoslav Ryhel
1260*118a745eSSvyatoslav Ryhel				ldo4 {
1261*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_rtc";
1262*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1263*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1264*118a745eSSvyatoslav Ryhel					regulator-always-on;
1265*118a745eSSvyatoslav Ryhel				};
1266*118a745eSSvyatoslav Ryhel
1267*118a745eSSvyatoslav Ryhel				/* ldo5 is not used by Portable AiO */
1268*118a745eSSvyatoslav Ryhel
1269*118a745eSSvyatoslav Ryhel				ldo6 {
1270*118a745eSSvyatoslav Ryhel					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1271*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1272*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1273*118a745eSSvyatoslav Ryhel				};
1274*118a745eSSvyatoslav Ryhel
1275*118a745eSSvyatoslav Ryhel				ldo7 {
1276*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_pllm,x,u,a_p_c_s";
1277*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1200000>;
1278*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1200000>;
1279*118a745eSSvyatoslav Ryhel					regulator-always-on;
1280*118a745eSSvyatoslav Ryhel					regulator-boot-on;
1281*118a745eSSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <8>;
1282*118a745eSSvyatoslav Ryhel				};
1283*118a745eSSvyatoslav Ryhel
1284*118a745eSSvyatoslav Ryhel				ldo8 {
1285*118a745eSSvyatoslav Ryhel					regulator-name = "vdd_ddr_hs";
1286*118a745eSSvyatoslav Ryhel					regulator-min-microvolt = <1000000>;
1287*118a745eSSvyatoslav Ryhel					regulator-max-microvolt = <1000000>;
1288*118a745eSSvyatoslav Ryhel					regulator-always-on;
1289*118a745eSSvyatoslav Ryhel					ti,regulator-ext-sleep-control = <8>;
1290*118a745eSSvyatoslav Ryhel				};
1291*118a745eSSvyatoslav Ryhel			};
1292*118a745eSSvyatoslav Ryhel		};
1293*118a745eSSvyatoslav Ryhel
1294*118a745eSSvyatoslav Ryhel		nct72: temperature-sensor@4c {
1295*118a745eSSvyatoslav Ryhel			compatible = "onnn,nct1008";
1296*118a745eSSvyatoslav Ryhel			reg = <0x4c>;
1297*118a745eSSvyatoslav Ryhel
1298*118a745eSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1299*118a745eSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1300*118a745eSSvyatoslav Ryhel
1301*118a745eSSvyatoslav Ryhel			vcc-supply = <&vdd_3v3_sys>;
1302*118a745eSSvyatoslav Ryhel			#thermal-sensor-cells = <1>;
1303*118a745eSSvyatoslav Ryhel		};
1304*118a745eSSvyatoslav Ryhel
1305*118a745eSSvyatoslav Ryhel		vdd_core: core-regulator@60 {
1306*118a745eSSvyatoslav Ryhel			compatible = "ti,tps62361";
1307*118a745eSSvyatoslav Ryhel			reg = <0x60>;
1308*118a745eSSvyatoslav Ryhel
1309*118a745eSSvyatoslav Ryhel			regulator-name = "tps62361-vout";
1310*118a745eSSvyatoslav Ryhel			regulator-min-microvolt = <500000>;
1311*118a745eSSvyatoslav Ryhel			regulator-max-microvolt = <1770000>;
1312*118a745eSSvyatoslav Ryhel			regulator-coupled-with = <&vdd_cpu>;
1313*118a745eSSvyatoslav Ryhel			regulator-coupled-max-spread = <300000>;
1314*118a745eSSvyatoslav Ryhel			regulator-max-step-microvolt = <100000>;
1315*118a745eSSvyatoslav Ryhel			regulator-boot-on;
1316*118a745eSSvyatoslav Ryhel			regulator-always-on;
1317*118a745eSSvyatoslav Ryhel			ti,enable-vout-discharge;
1318*118a745eSSvyatoslav Ryhel			ti,vsel0-state-high;
1319*118a745eSSvyatoslav Ryhel			ti,vsel1-state-high;
1320*118a745eSSvyatoslav Ryhel
1321*118a745eSSvyatoslav Ryhel			nvidia,tegra-core-regulator;
1322*118a745eSSvyatoslav Ryhel		};
1323*118a745eSSvyatoslav Ryhel	};
1324*118a745eSSvyatoslav Ryhel
1325*118a745eSSvyatoslav Ryhel	vdd_5v0_bat: regulator-bat {
1326*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1327*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_ac_bat";
1328*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1329*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1330*118a745eSSvyatoslav Ryhel		regulator-always-on;
1331*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1332*118a745eSSvyatoslav Ryhel	};
1333*118a745eSSvyatoslav Ryhel
1334*118a745eSSvyatoslav Ryhel	vdd_5v0_cp: regulator-sby {
1335*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1336*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_5v0_sby";
1337*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1338*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1339*118a745eSSvyatoslav Ryhel		regulator-always-on;
1340*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1341*118a745eSSvyatoslav Ryhel		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1342*118a745eSSvyatoslav Ryhel		enable-active-high;
1343*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
1344*118a745eSSvyatoslav Ryhel	};
1345*118a745eSSvyatoslav Ryhel
1346*118a745eSSvyatoslav Ryhel	vdd_5v0_sys: regulator-5v {
1347*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1348*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_5v0_sys";
1349*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1350*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1351*118a745eSSvyatoslav Ryhel		regulator-always-on;
1352*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1353*118a745eSSvyatoslav Ryhel		gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1354*118a745eSSvyatoslav Ryhel		enable-active-high;
1355*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
1356*118a745eSSvyatoslav Ryhel	};
1357*118a745eSSvyatoslav Ryhel
1358*118a745eSSvyatoslav Ryhel	vdd_1v5_ddr: regulator-ddr {
1359*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1360*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_ddr";
1361*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <1500000>;
1362*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <1500000>;
1363*118a745eSSvyatoslav Ryhel		regulator-always-on;
1364*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1365*118a745eSSvyatoslav Ryhel		gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1366*118a745eSSvyatoslav Ryhel		enable-active-high;
1367*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
1368*118a745eSSvyatoslav Ryhel	};
1369*118a745eSSvyatoslav Ryhel
1370*118a745eSSvyatoslav Ryhel	vdd_3v3_sys: regulator-3v {
1371*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1372*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_3v3_sys";
1373*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
1374*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
1375*118a745eSSvyatoslav Ryhel		regulator-always-on;
1376*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1377*118a745eSSvyatoslav Ryhel		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1378*118a745eSSvyatoslav Ryhel		enable-active-high;
1379*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_bat>;
1380*118a745eSSvyatoslav Ryhel	};
1381*118a745eSSvyatoslav Ryhel
1382*118a745eSSvyatoslav Ryhel	vdd_3v3_com: regulator-com {
1383*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1384*118a745eSSvyatoslav Ryhel		regulator-name = "vdd_3v3_com";
1385*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <3300000>;
1386*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <3300000>;
1387*118a745eSSvyatoslav Ryhel		regulator-always-on;
1388*118a745eSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1389*118a745eSSvyatoslav Ryhel		enable-active-high;
1390*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_3v3_sys>;
1391*118a745eSSvyatoslav Ryhel	};
1392*118a745eSSvyatoslav Ryhel
1393*118a745eSSvyatoslav Ryhel	usb2_vbus: regulator-usb2 {
1394*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1395*118a745eSSvyatoslav Ryhel		regulator-name = "usb2_vbus";
1396*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1397*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1398*118a745eSSvyatoslav Ryhel		enable-active-high;
1399*118a745eSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
1400*118a745eSSvyatoslav Ryhel		gpio-open-drain;
1401*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_sys>;
1402*118a745eSSvyatoslav Ryhel	};
1403*118a745eSSvyatoslav Ryhel
1404*118a745eSSvyatoslav Ryhel	hdmi_5v0_sys: regulator-hdmi {
1405*118a745eSSvyatoslav Ryhel		compatible = "regulator-fixed";
1406*118a745eSSvyatoslav Ryhel		regulator-name = "hdmi_5v0_sys";
1407*118a745eSSvyatoslav Ryhel		regulator-min-microvolt = <5000000>;
1408*118a745eSSvyatoslav Ryhel		regulator-max-microvolt = <5000000>;
1409*118a745eSSvyatoslav Ryhel		regulator-boot-on;
1410*118a745eSSvyatoslav Ryhel		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1411*118a745eSSvyatoslav Ryhel		enable-active-high;
1412*118a745eSSvyatoslav Ryhel		vin-supply = <&vdd_5v0_sys>;
1413*118a745eSSvyatoslav Ryhel	};
1414*118a745eSSvyatoslav Ryhel
1415*118a745eSSvyatoslav Ryhel	pmc@7000e400 {
1416*118a745eSSvyatoslav Ryhel		status = "okay";
1417*118a745eSSvyatoslav Ryhel		nvidia,invert-interrupt;
1418*118a745eSSvyatoslav Ryhel		nvidia,suspend-mode = <2>;
1419*118a745eSSvyatoslav Ryhel		nvidia,cpu-pwr-good-time = <2000>;
1420*118a745eSSvyatoslav Ryhel		nvidia,cpu-pwr-off-time = <200>;
1421*118a745eSSvyatoslav Ryhel		nvidia,core-pwr-good-time = <3845 3845>;
1422*118a745eSSvyatoslav Ryhel		nvidia,core-pwr-off-time = <0>;
1423*118a745eSSvyatoslav Ryhel		nvidia,core-power-req-active-high;
1424*118a745eSSvyatoslav Ryhel		nvidia,sys-clock-req-active-high;
1425*118a745eSSvyatoslav Ryhel		core-supply = <&vdd_core>;
1426*118a745eSSvyatoslav Ryhel
1427*118a745eSSvyatoslav Ryhel		i2c-thermtrip {
1428*118a745eSSvyatoslav Ryhel			nvidia,i2c-controller-id = <4>;
1429*118a745eSSvyatoslav Ryhel			nvidia,bus-addr = <0x2d>;
1430*118a745eSSvyatoslav Ryhel			nvidia,reg-addr = <0x3f>;
1431*118a745eSSvyatoslav Ryhel			nvidia,reg-data = <0x81>;
1432*118a745eSSvyatoslav Ryhel		};
1433*118a745eSSvyatoslav Ryhel	};
1434*118a745eSSvyatoslav Ryhel
1435*118a745eSSvyatoslav Ryhel	memory-controller@7000f000 {
1436*118a745eSSvyatoslav Ryhel		emc-timings-3 {
1437*118a745eSSvyatoslav Ryhel			/* Micron 2GB 800MHz */
1438*118a745eSSvyatoslav Ryhel			nvidia,ram-code = <3>;
1439*118a745eSSvyatoslav Ryhel
1440*118a745eSSvyatoslav Ryhel			timing-25500000 {
1441*118a745eSSvyatoslav Ryhel				clock-frequency = <25500000>;
1442*118a745eSSvyatoslav Ryhel
1443*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00030003 0xc0000020
1444*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1445*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1446*118a745eSSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1447*118a745eSSvyatoslav Ryhel					0x06020102 0x000a0502 0x75830303 0x001f0000 >;
1448*118a745eSSvyatoslav Ryhel			};
1449*118a745eSSvyatoslav Ryhel
1450*118a745eSSvyatoslav Ryhel			timing-51000000 {
1451*118a745eSSvyatoslav Ryhel				clock-frequency = <51000000>;
1452*118a745eSSvyatoslav Ryhel
1453*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00010003 0xc0000020
1454*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000002 0x00000000
1455*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1456*118a745eSSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1457*118a745eSSvyatoslav Ryhel					0x06020102 0x000a0502 0x74630303 0x001f0000 >;
1458*118a745eSSvyatoslav Ryhel			};
1459*118a745eSSvyatoslav Ryhel
1460*118a745eSSvyatoslav Ryhel			timing-102000000 {
1461*118a745eSSvyatoslav Ryhel				clock-frequency = <102000000>;
1462*118a745eSSvyatoslav Ryhel
1463*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000003 0xc0000030
1464*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000000
1465*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000003 0x00000008
1466*118a745eSSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1467*118a745eSSvyatoslav Ryhel					0x06020102 0x000a0503 0x73c30504 0x001f0000 >;
1468*118a745eSSvyatoslav Ryhel			};
1469*118a745eSSvyatoslav Ryhel
1470*118a745eSSvyatoslav Ryhel			timing-204000000 {
1471*118a745eSSvyatoslav Ryhel				clock-frequency = <204000000>;
1472*118a745eSSvyatoslav Ryhel
1473*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000006 0xc0000025
1474*118a745eSSvyatoslav Ryhel					0x00000001 0x00000001 0x00000005 0x00000002
1475*118a745eSSvyatoslav Ryhel					0x00000003 0x00000001 0x00000003 0x00000008
1476*118a745eSSvyatoslav Ryhel					0x00000002 0x00000001 0x00000002 0x00000006
1477*118a745eSSvyatoslav Ryhel					0x06020102 0x000a0505 0x73840a06 0x001f0000 >;
1478*118a745eSSvyatoslav Ryhel			};
1479*118a745eSSvyatoslav Ryhel
1480*118a745eSSvyatoslav Ryhel			timing-400000000 {
1481*118a745eSSvyatoslav Ryhel				clock-frequency = <400000000>;
1482*118a745eSSvyatoslav Ryhel
1483*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x0000000c 0xc0000048
1484*118a745eSSvyatoslav Ryhel					0x00000001 0x00000002 0x00000009 0x00000005
1485*118a745eSSvyatoslav Ryhel					0x00000005 0x00000001 0x00000002 0x00000008
1486*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000003 0x00000006
1487*118a745eSSvyatoslav Ryhel					0x06030202 0x000d0709 0x7086120a 0x001f0000 >;
1488*118a745eSSvyatoslav Ryhel			};
1489*118a745eSSvyatoslav Ryhel
1490*118a745eSSvyatoslav Ryhel			timing-800000000 {
1491*118a745eSSvyatoslav Ryhel				clock-frequency = <800000000>;
1492*118a745eSSvyatoslav Ryhel
1493*118a745eSSvyatoslav Ryhel				nvidia,emem-configuration = < 0x00000018 0xc0000090
1494*118a745eSSvyatoslav Ryhel					0x00000004 0x00000005 0x00000013 0x0000000c
1495*118a745eSSvyatoslav Ryhel					0x0000000b 0x00000002 0x00000003 0x0000000c
1496*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000004 0x00000008
1497*118a745eSSvyatoslav Ryhel					0x08040202 0x00160d13 0x712c2414 0x001f0000 >;
1498*118a745eSSvyatoslav Ryhel			};
1499*118a745eSSvyatoslav Ryhel		};
1500*118a745eSSvyatoslav Ryhel	};
1501*118a745eSSvyatoslav Ryhel
1502*118a745eSSvyatoslav Ryhel	memory-controller@7000f400 {
1503*118a745eSSvyatoslav Ryhel		emc-timings-3 {
1504*118a745eSSvyatoslav Ryhel			/* Micron 2GB 800MHz */
1505*118a745eSSvyatoslav Ryhel			nvidia,ram-code = <3>;
1506*118a745eSSvyatoslav Ryhel
1507*118a745eSSvyatoslav Ryhel			timing-25500000 {
1508*118a745eSSvyatoslav Ryhel				clock-frequency = <25500000>;
1509*118a745eSSvyatoslav Ryhel
1510*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1511*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1512*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200008>;
1513*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1514*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1515*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1516*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1517*118a745eSSvyatoslav Ryhel
1518*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000001
1519*118a745eSSvyatoslav Ryhel					0x00000006 0x00000000 0x00000000 0x00000002
1520*118a745eSSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1521*118a745eSSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1522*118a745eSSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x00000009
1523*118a745eSSvyatoslav Ryhel					0x0000000b 0x000000c0 0x00000000 0x00000030
1524*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1525*118a745eSSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000007 0x00000007
1526*118a745eSSvyatoslav Ryhel					0x00000004 0x00000001 0x00000000 0x00000004
1527*118a745eSSvyatoslav Ryhel					0x00000005 0x000000c7 0x00000006 0x00000006
1528*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1529*118a745eSSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1530*118a745eSSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1531*118a745eSSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1532*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1533*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1534*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1535*118a745eSSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1536*118a745eSSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1537*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1538*118a745eSSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1539*118a745eSSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1540*118a745eSSvyatoslav Ryhel					0x00000000 0x80000287 0xe8000000 0xff00ff00 >;
1541*118a745eSSvyatoslav Ryhel			};
1542*118a745eSSvyatoslav Ryhel
1543*118a745eSSvyatoslav Ryhel			timing-51000000 {
1544*118a745eSSvyatoslav Ryhel				clock-frequency = <51000000>;
1545*118a745eSSvyatoslav Ryhel
1546*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1547*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1548*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200008>;
1549*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1550*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1551*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1552*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1553*118a745eSSvyatoslav Ryhel
1554*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000002
1555*118a745eSSvyatoslav Ryhel					0x0000000d 0x00000001 0x00000000 0x00000002
1556*118a745eSSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000000
1557*118a745eSSvyatoslav Ryhel					0x00000000 0x00000003 0x00000001 0x00000000
1558*118a745eSSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x00000009
1559*118a745eSSvyatoslav Ryhel					0x0000000b 0x00000181 0x00000000 0x00000060
1560*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1561*118a745eSSvyatoslav Ryhel					0x00000007 0x0000000f 0x0000000e 0x0000000e
1562*118a745eSSvyatoslav Ryhel					0x00000004 0x00000002 0x00000000 0x00000004
1563*118a745eSSvyatoslav Ryhel					0x00000005 0x0000018e 0x00000006 0x00000006
1564*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1565*118a745eSSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1566*118a745eSSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1567*118a745eSSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1568*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1569*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1570*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1571*118a745eSSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1572*118a745eSSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1573*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1574*118a745eSSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1575*118a745eSSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1576*118a745eSSvyatoslav Ryhel					0x00000000 0x8000040b 0xe8000000 0xff00ff00 >;
1577*118a745eSSvyatoslav Ryhel			};
1578*118a745eSSvyatoslav Ryhel
1579*118a745eSSvyatoslav Ryhel			timing-102000000 {
1580*118a745eSSvyatoslav Ryhel				clock-frequency = <102000000>;
1581*118a745eSSvyatoslav Ryhel
1582*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1583*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1584*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200008>;
1585*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1586*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1587*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1588*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1589*118a745eSSvyatoslav Ryhel
1590*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000004
1591*118a745eSSvyatoslav Ryhel					0x0000001a 0x00000003 0x00000001 0x00000002
1592*118a745eSSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000001
1593*118a745eSSvyatoslav Ryhel					0x00000001 0x00000003 0x00000001 0x00000000
1594*118a745eSSvyatoslav Ryhel					0x00000005 0x00000005 0x00000004 0x00000009
1595*118a745eSSvyatoslav Ryhel					0x0000000b 0x00000303 0x00000000 0x000000c0
1596*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1597*118a745eSSvyatoslav Ryhel					0x00000007 0x0000000f 0x0000001c 0x0000001c
1598*118a745eSSvyatoslav Ryhel					0x00000004 0x00000004 0x00000000 0x00000004
1599*118a745eSSvyatoslav Ryhel					0x00000005 0x0000031c 0x00000006 0x00000006
1600*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x007800a4
1601*118a745eSSvyatoslav Ryhel					0x00008000 0x000fc000 0x000fc000 0x000fc000
1602*118a745eSSvyatoslav Ryhel					0x000fc000 0x000fc000 0x000fc000 0x000fc000
1603*118a745eSSvyatoslav Ryhel					0x000fc000 0x00000000 0x00000000 0x00000000
1604*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1605*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1606*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1607*118a745eSSvyatoslav Ryhel					0x00000000 0x000fc000 0x000fc000 0x000fc000
1608*118a745eSSvyatoslav Ryhel					0x000fc000 0x000002a0 0x0800211c 0x00000000
1609*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1610*118a745eSSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00000000
1611*118a745eSSvyatoslav Ryhel					0x00000040 0x000c000c 0xa0f10000 0x00000000
1612*118a745eSSvyatoslav Ryhel					0x00000000 0x80000713 0xe8000000 0xff00ff00 >;
1613*118a745eSSvyatoslav Ryhel			};
1614*118a745eSSvyatoslav Ryhel
1615*118a745eSSvyatoslav Ryhel			timing-204000000 {
1616*118a745eSSvyatoslav Ryhel				clock-frequency = <204000000>;
1617*118a745eSSvyatoslav Ryhel
1618*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1619*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100003>;
1620*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200008>;
1621*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80001221>;
1622*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1623*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-dyn-self-ref;
1624*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1625*118a745eSSvyatoslav Ryhel
1626*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000009
1627*118a745eSSvyatoslav Ryhel					0x00000035 0x00000007 0x00000002 0x00000002
1628*118a745eSSvyatoslav Ryhel					0x0000000a 0x00000005 0x0000000b 0x00000002
1629*118a745eSSvyatoslav Ryhel					0x00000002 0x00000003 0x00000001 0x00000000
1630*118a745eSSvyatoslav Ryhel					0x00000005 0x00000006 0x00000004 0x00000009
1631*118a745eSSvyatoslav Ryhel					0x0000000b 0x00000607 0x00000000 0x00000181
1632*118a745eSSvyatoslav Ryhel					0x00000002 0x00000002 0x00000001 0x00000000
1633*118a745eSSvyatoslav Ryhel					0x00000007 0x0000000f 0x00000038 0x00000038
1634*118a745eSSvyatoslav Ryhel					0x00000004 0x00000007 0x00000000 0x00000004
1635*118a745eSSvyatoslav Ryhel					0x00000005 0x00000638 0x00000007 0x00000004
1636*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00004288 0x004400a4
1637*118a745eSSvyatoslav Ryhel					0x00008000 0x00080000 0x00080000 0x00080000
1638*118a745eSSvyatoslav Ryhel					0x00080000 0x00080000 0x00080000 0x00080000
1639*118a745eSSvyatoslav Ryhel					0x00080000 0x00000000 0x00000000 0x00000000
1640*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1641*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1642*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1643*118a745eSSvyatoslav Ryhel					0x00000000 0x00080000 0x00080000 0x00080000
1644*118a745eSSvyatoslav Ryhel					0x00080000 0x000002a0 0x0800211c 0x00000000
1645*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f108 0x05057404 0x54000007
1646*118a745eSSvyatoslav Ryhel					0x08000168 0x08000000 0x00000802 0x00020000
1647*118a745eSSvyatoslav Ryhel					0x00000100 0x000c000c 0xa0f10000 0x00000000
1648*118a745eSSvyatoslav Ryhel					0x00000000 0x80000d22 0xe8000000 0xff00ff00 >;
1649*118a745eSSvyatoslav Ryhel			};
1650*118a745eSSvyatoslav Ryhel
1651*118a745eSSvyatoslav Ryhel			timing-400000000 {
1652*118a745eSSvyatoslav Ryhel				clock-frequency = <400000000>;
1653*118a745eSSvyatoslav Ryhel
1654*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1655*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1656*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200000>;
1657*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000521>;
1658*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1659*118a745eSSvyatoslav Ryhel
1660*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000012
1661*118a745eSSvyatoslav Ryhel					0x00000066 0x0000000c 0x00000004 0x00000003
1662*118a745eSSvyatoslav Ryhel					0x00000008 0x00000002 0x0000000a 0x00000004
1663*118a745eSSvyatoslav Ryhel					0x00000004 0x00000002 0x00000001 0x00000000
1664*118a745eSSvyatoslav Ryhel					0x00000004 0x00000006 0x00000004 0x0000000a
1665*118a745eSSvyatoslav Ryhel					0x0000000c 0x00000bf0 0x00000000 0x000002fc
1666*118a745eSSvyatoslav Ryhel					0x00000001 0x00000008 0x00000001 0x00000000
1667*118a745eSSvyatoslav Ryhel					0x00000008 0x0000000f 0x0000006c 0x00000200
1668*118a745eSSvyatoslav Ryhel					0x00000004 0x0000000c 0x00000000 0x00000004
1669*118a745eSSvyatoslav Ryhel					0x00000005 0x00000c30 0x00000000 0x00000004
1670*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00007088 0x001d0084
1671*118a745eSSvyatoslav Ryhel					0x00008000 0x00044000 0x00044000 0x00044000
1672*118a745eSSvyatoslav Ryhel					0x00044000 0x00044000 0x00044000 0x00044000
1673*118a745eSSvyatoslav Ryhel					0x00044000 0x00000000 0x00000000 0x00000000
1674*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1675*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1676*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1677*118a745eSSvyatoslav Ryhel					0x00000000 0x00048000 0x00048000 0x00048000
1678*118a745eSSvyatoslav Ryhel					0x00048000 0x000002a0 0x0800013d 0x00000000
1679*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f508 0x05057404 0x54000007
1680*118a745eSSvyatoslav Ryhel					0x080001e8 0x08000021 0x00000802 0x00020000
1681*118a745eSSvyatoslav Ryhel					0x00000100 0x0158000c 0xa0f10000 0x00000000
1682*118a745eSSvyatoslav Ryhel					0x00000000 0x800018c8 0xe8000000 0xff00ff89 >;
1683*118a745eSSvyatoslav Ryhel			};
1684*118a745eSSvyatoslav Ryhel
1685*118a745eSSvyatoslav Ryhel			timing-800000000 {
1686*118a745eSSvyatoslav Ryhel				clock-frequency = <800000000>;
1687*118a745eSSvyatoslav Ryhel
1688*118a745eSSvyatoslav Ryhel				nvidia,emc-auto-cal-interval = <0x001fffff>;
1689*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-1 = <0x80100002>;
1690*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-2 = <0x80200018>;
1691*118a745eSSvyatoslav Ryhel				nvidia,emc-mode-reset = <0x80000d71>;
1692*118a745eSSvyatoslav Ryhel				nvidia,emc-zcal-cnt-long = <0x00000040>;
1693*118a745eSSvyatoslav Ryhel				nvidia,emc-cfg-periodic-qrst;
1694*118a745eSSvyatoslav Ryhel
1695*118a745eSSvyatoslav Ryhel				nvidia,emc-configuration =  < 0x00000025
1696*118a745eSSvyatoslav Ryhel					0x000000ce 0x0000001a 0x00000009 0x00000005
1697*118a745eSSvyatoslav Ryhel					0x0000000d 0x00000004 0x00000013 0x00000009
1698*118a745eSSvyatoslav Ryhel					0x00000009 0x00000003 0x00000001 0x00000000
1699*118a745eSSvyatoslav Ryhel					0x00000007 0x0000000b 0x00000009 0x0000000b
1700*118a745eSSvyatoslav Ryhel					0x00000012 0x00001820 0x00000000 0x00000608
1701*118a745eSSvyatoslav Ryhel					0x00000003 0x00000012 0x00000001 0x00000000
1702*118a745eSSvyatoslav Ryhel					0x0000000f 0x00000018 0x000000d8 0x00000200
1703*118a745eSSvyatoslav Ryhel					0x00000005 0x00000018 0x00000000 0x00000007
1704*118a745eSSvyatoslav Ryhel					0x00000008 0x00001860 0x0000000c 0x00000004
1705*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00005088 0xf0070191
1706*118a745eSSvyatoslav Ryhel					0x00008000 0x0000c00a 0x0000000a 0x0000000a
1707*118a745eSSvyatoslav Ryhel					0x0000000a 0x0000000a 0x0000000a 0x0000000a
1708*118a745eSSvyatoslav Ryhel					0x0000000a 0x00018000 0x00018000 0x00018000
1709*118a745eSSvyatoslav Ryhel					0x00018000 0x00000000 0x00000000 0x00000000
1710*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1711*118a745eSSvyatoslav Ryhel					0x00000000 0x00000000 0x00000000 0x00000000
1712*118a745eSSvyatoslav Ryhel					0x00000000 0x0000000a 0x0000000a 0x0000000a
1713*118a745eSSvyatoslav Ryhel					0x0000000a 0x000002a0 0x0800013d 0x22220000
1714*118a745eSSvyatoslav Ryhel					0x77fff884 0x01f1f501 0x07077404 0x54000000
1715*118a745eSSvyatoslav Ryhel					0x080001e8 0x08000021 0x00000802 0x00020000
1716*118a745eSSvyatoslav Ryhel					0x00000100 0x00f0000c 0xa0f10202 0x00000000
1717*118a745eSSvyatoslav Ryhel					0x00000000 0x8000308c 0xe8000000 0xff00ff49 >;
1718*118a745eSSvyatoslav Ryhel			};
1719*118a745eSSvyatoslav Ryhel		};
1720*118a745eSSvyatoslav Ryhel	};
1721*118a745eSSvyatoslav Ryhel
1722*118a745eSSvyatoslav Ryhel	hda@70030000 {
1723*118a745eSSvyatoslav Ryhel		status = "okay";
1724*118a745eSSvyatoslav Ryhel	};
1725*118a745eSSvyatoslav Ryhel
1726*118a745eSSvyatoslav Ryhel	ahub@70080000 {
1727*118a745eSSvyatoslav Ryhel		i2s@70080400 { /* i2s1 */
1728*118a745eSSvyatoslav Ryhel			status = "okay";
1729*118a745eSSvyatoslav Ryhel		};
1730*118a745eSSvyatoslav Ryhel
1731*118a745eSSvyatoslav Ryhel		/* BT SCO */
1732*118a745eSSvyatoslav Ryhel		i2s@70080600 { /* i2s3 */
1733*118a745eSSvyatoslav Ryhel			status = "okay";
1734*118a745eSSvyatoslav Ryhel		};
1735*118a745eSSvyatoslav Ryhel	};
1736*118a745eSSvyatoslav Ryhel
1737*118a745eSSvyatoslav Ryhel	sdmmc1: mmc@78000000 {
1738*118a745eSSvyatoslav Ryhel		status = "okay";
1739*118a745eSSvyatoslav Ryhel
1740*118a745eSSvyatoslav Ryhel		/* SDR104 mode unsupported yet */
1741*118a745eSSvyatoslav Ryhel		max-frequency = <104000000>;
1742*118a745eSSvyatoslav Ryhel
1743*118a745eSSvyatoslav Ryhel		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1744*118a745eSSvyatoslav Ryhel		bus-width = <4>;
1745*118a745eSSvyatoslav Ryhel
1746*118a745eSSvyatoslav Ryhel		vmmc-supply = <&vdd_usd>;	/* ldo2 */
1747*118a745eSSvyatoslav Ryhel		vqmmc-supply = <&vddio_usd>;	/* ldo3 */
1748*118a745eSSvyatoslav Ryhel	};
1749*118a745eSSvyatoslav Ryhel
1750*118a745eSSvyatoslav Ryhel	sdmmc3: mmc@78000400 {
1751*118a745eSSvyatoslav Ryhel		status = "okay";
1752*118a745eSSvyatoslav Ryhel
1753*118a745eSSvyatoslav Ryhel		#address-cells = <1>;
1754*118a745eSSvyatoslav Ryhel		#size-cells = <0>;
1755*118a745eSSvyatoslav Ryhel
1756*118a745eSSvyatoslav Ryhel		keep-power-in-suspend;
1757*118a745eSSvyatoslav Ryhel		bus-width = <4>;
1758*118a745eSSvyatoslav Ryhel		non-removable;
1759*118a745eSSvyatoslav Ryhel
1760*118a745eSSvyatoslav Ryhel		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1761*118a745eSSvyatoslav Ryhel		vmmc-supply = <&vdd_3v3_com>;
1762*118a745eSSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
1763*118a745eSSvyatoslav Ryhel
1764*118a745eSSvyatoslav Ryhel		/* Azurewave AW-AH691 BCM43241B0 */
1765*118a745eSSvyatoslav Ryhel		wifi@1 {
1766*118a745eSSvyatoslav Ryhel			compatible = "brcm,bcm4329-fmac";
1767*118a745eSSvyatoslav Ryhel			reg = <1>;
1768*118a745eSSvyatoslav Ryhel
1769*118a745eSSvyatoslav Ryhel			interrupt-parent = <&gpio>;
1770*118a745eSSvyatoslav Ryhel			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1771*118a745eSSvyatoslav Ryhel			interrupt-names = "host-wake";
1772*118a745eSSvyatoslav Ryhel		};
1773*118a745eSSvyatoslav Ryhel	};
1774*118a745eSSvyatoslav Ryhel
1775*118a745eSSvyatoslav Ryhel	sdmmc4: mmc@78000600 {
1776*118a745eSSvyatoslav Ryhel		status = "okay";
1777*118a745eSSvyatoslav Ryhel		bus-width = <8>;
1778*118a745eSSvyatoslav Ryhel
1779*118a745eSSvyatoslav Ryhel		non-removable;
1780*118a745eSSvyatoslav Ryhel		mmc-ddr-3_3v;
1781*118a745eSSvyatoslav Ryhel
1782*118a745eSSvyatoslav Ryhel		vmmc-supply = <&vcore_emmc>;
1783*118a745eSSvyatoslav Ryhel		vqmmc-supply = <&vdd_1v8_vio>;
1784*118a745eSSvyatoslav Ryhel	};
1785*118a745eSSvyatoslav Ryhel
1786*118a745eSSvyatoslav Ryhel	/* USB via ASUS connector */
1787*118a745eSSvyatoslav Ryhel	usb@7d000000 {
1788*118a745eSSvyatoslav Ryhel		compatible = "nvidia,tegra30-udc";
1789*118a745eSSvyatoslav Ryhel		status = "okay";
1790*118a745eSSvyatoslav Ryhel		dr_mode = "peripheral";
1791*118a745eSSvyatoslav Ryhel	};
1792*118a745eSSvyatoslav Ryhel
1793*118a745eSSvyatoslav Ryhel	usb-phy@7d000000 {
1794*118a745eSSvyatoslav Ryhel		status = "okay";
1795*118a745eSSvyatoslav Ryhel		dr_mode = "peripheral";
1796*118a745eSSvyatoslav Ryhel		nvidia,hssync-start-delay = <0>;
1797*118a745eSSvyatoslav Ryhel		nvidia,xcvr-lsfslew = <2>;
1798*118a745eSSvyatoslav Ryhel		nvidia,xcvr-lsrslew = <2>;
1799*118a745eSSvyatoslav Ryhel		vbus-supply = <&vdd_5v0_sys>;
1800*118a745eSSvyatoslav Ryhel	};
1801*118a745eSSvyatoslav Ryhel
1802*118a745eSSvyatoslav Ryhel	/* mini-USB port */
1803*118a745eSSvyatoslav Ryhel	usb@7d004000 {
1804*118a745eSSvyatoslav Ryhel		status = "okay";
1805*118a745eSSvyatoslav Ryhel	};
1806*118a745eSSvyatoslav Ryhel
1807*118a745eSSvyatoslav Ryhel	usb-phy@7d004000 {
1808*118a745eSSvyatoslav Ryhel		status = "okay";
1809*118a745eSSvyatoslav Ryhel		vbus-supply = <&usb2_vbus>;
1810*118a745eSSvyatoslav Ryhel	};
1811*118a745eSSvyatoslav Ryhel
1812*118a745eSSvyatoslav Ryhel	/* Full size USB */
1813*118a745eSSvyatoslav Ryhel	usb@7d008000 {
1814*118a745eSSvyatoslav Ryhel		status = "okay";
1815*118a745eSSvyatoslav Ryhel	};
1816*118a745eSSvyatoslav Ryhel
1817*118a745eSSvyatoslav Ryhel	usb-phy@7d008000 {
1818*118a745eSSvyatoslav Ryhel		status = "okay";
1819*118a745eSSvyatoslav Ryhel		vbus-supply = <&vdd_5v0_bat>;
1820*118a745eSSvyatoslav Ryhel	};
1821*118a745eSSvyatoslav Ryhel
1822*118a745eSSvyatoslav Ryhel	pad_battery: battery-cell {
1823*118a745eSSvyatoslav Ryhel		compatible = "simple-battery";
1824*118a745eSSvyatoslav Ryhel		device-chemistry = "lithium-ion-polymer";
1825*118a745eSSvyatoslav Ryhel		charge-full-design-microamp-hours = <5136000>;
1826*118a745eSSvyatoslav Ryhel		energy-full-design-microwatt-hours = <38000000>;
1827*118a745eSSvyatoslav Ryhel		operating-range-celsius = <0 45>;
1828*118a745eSSvyatoslav Ryhel	};
1829*118a745eSSvyatoslav Ryhel
1830*118a745eSSvyatoslav Ryhel	/* Connected to a 18.4" LVDS panel */
1831*118a745eSSvyatoslav Ryhel	bridge {
1832*118a745eSSvyatoslav Ryhel		compatible = "mstar,tsumu88adt3-lf-1";
1833*118a745eSSvyatoslav Ryhel
1834*118a745eSSvyatoslav Ryhel		ports {
1835*118a745eSSvyatoslav Ryhel			#address-cells = <1>;
1836*118a745eSSvyatoslav Ryhel			#size-cells = <0>;
1837*118a745eSSvyatoslav Ryhel
1838*118a745eSSvyatoslav Ryhel			port@0 {
1839*118a745eSSvyatoslav Ryhel				reg = <0>;
1840*118a745eSSvyatoslav Ryhel
1841*118a745eSSvyatoslav Ryhel				bridge_in: endpoint {
1842*118a745eSSvyatoslav Ryhel					remote-endpoint = <&hdmi_out>;
1843*118a745eSSvyatoslav Ryhel				};
1844*118a745eSSvyatoslav Ryhel			};
1845*118a745eSSvyatoslav Ryhel
1846*118a745eSSvyatoslav Ryhel			port@1 {
1847*118a745eSSvyatoslav Ryhel				reg = <1>;
1848*118a745eSSvyatoslav Ryhel
1849*118a745eSSvyatoslav Ryhel				bridge_out: endpoint {
1850*118a745eSSvyatoslav Ryhel					remote-endpoint = <&hdmi_connector_in>;
1851*118a745eSSvyatoslav Ryhel				};
1852*118a745eSSvyatoslav Ryhel			};
1853*118a745eSSvyatoslav Ryhel		};
1854*118a745eSSvyatoslav Ryhel	};
1855*118a745eSSvyatoslav Ryhel
1856*118a745eSSvyatoslav Ryhel	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1857*118a745eSSvyatoslav Ryhel	clk32k_in: clock-32k {
1858*118a745eSSvyatoslav Ryhel		compatible = "fixed-clock";
1859*118a745eSSvyatoslav Ryhel		#clock-cells = <0>;
1860*118a745eSSvyatoslav Ryhel		clock-frequency = <32768>;
1861*118a745eSSvyatoslav Ryhel		clock-output-names = "pmic-oscillator";
1862*118a745eSSvyatoslav Ryhel	};
1863*118a745eSSvyatoslav Ryhel
1864*118a745eSSvyatoslav Ryhel	connector {
1865*118a745eSSvyatoslav Ryhel		compatible = "hdmi-connector";
1866*118a745eSSvyatoslav Ryhel		label = "HDMI";
1867*118a745eSSvyatoslav Ryhel		type = "a";
1868*118a745eSSvyatoslav Ryhel
1869*118a745eSSvyatoslav Ryhel		/* low: tablet, high: dock */
1870*118a745eSSvyatoslav Ryhel		hpd-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_LOW>;
1871*118a745eSSvyatoslav Ryhel		ddc-i2c-bus = <&hdmi_ddc>;
1872*118a745eSSvyatoslav Ryhel		ddc-en-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1873*118a745eSSvyatoslav Ryhel
1874*118a745eSSvyatoslav Ryhel		port {
1875*118a745eSSvyatoslav Ryhel			hdmi_connector_in: endpoint {
1876*118a745eSSvyatoslav Ryhel				remote-endpoint = <&bridge_out>;
1877*118a745eSSvyatoslav Ryhel			};
1878*118a745eSSvyatoslav Ryhel		};
1879*118a745eSSvyatoslav Ryhel	};
1880*118a745eSSvyatoslav Ryhel
1881*118a745eSSvyatoslav Ryhel	cpus {
1882*118a745eSSvyatoslav Ryhel		cpu0: cpu@0 {
1883*118a745eSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1884*118a745eSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1885*118a745eSSvyatoslav Ryhel			#cooling-cells = <2>;
1886*118a745eSSvyatoslav Ryhel		};
1887*118a745eSSvyatoslav Ryhel		cpu1: cpu@1 {
1888*118a745eSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1889*118a745eSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1890*118a745eSSvyatoslav Ryhel			#cooling-cells = <2>;
1891*118a745eSSvyatoslav Ryhel		};
1892*118a745eSSvyatoslav Ryhel		cpu2: cpu@2 {
1893*118a745eSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1894*118a745eSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1895*118a745eSSvyatoslav Ryhel			#cooling-cells = <2>;
1896*118a745eSSvyatoslav Ryhel		};
1897*118a745eSSvyatoslav Ryhel		cpu3: cpu@3 {
1898*118a745eSSvyatoslav Ryhel			cpu-supply = <&vdd_cpu>;
1899*118a745eSSvyatoslav Ryhel			operating-points-v2 = <&cpu0_opp_table>;
1900*118a745eSSvyatoslav Ryhel			#cooling-cells = <2>;
1901*118a745eSSvyatoslav Ryhel		};
1902*118a745eSSvyatoslav Ryhel	};
1903*118a745eSSvyatoslav Ryhel
1904*118a745eSSvyatoslav Ryhel	gpio-keys {
1905*118a745eSSvyatoslav Ryhel		compatible = "gpio-keys";
1906*118a745eSSvyatoslav Ryhel
1907*118a745eSSvyatoslav Ryhel		key-power {
1908*118a745eSSvyatoslav Ryhel			label = "Power";
1909*118a745eSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1910*118a745eSSvyatoslav Ryhel			linux,code = <KEY_POWER>;
1911*118a745eSSvyatoslav Ryhel			debounce-interval = <10>;
1912*118a745eSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1913*118a745eSSvyatoslav Ryhel			wakeup-source;
1914*118a745eSSvyatoslav Ryhel		};
1915*118a745eSSvyatoslav Ryhel
1916*118a745eSSvyatoslav Ryhel		key-volume-up {
1917*118a745eSSvyatoslav Ryhel			label = "Volume Up";
1918*118a745eSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1919*118a745eSSvyatoslav Ryhel			linux,code = <KEY_VOLUMEUP>;
1920*118a745eSSvyatoslav Ryhel			debounce-interval = <10>;
1921*118a745eSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1922*118a745eSSvyatoslav Ryhel			wakeup-source;
1923*118a745eSSvyatoslav Ryhel		};
1924*118a745eSSvyatoslav Ryhel
1925*118a745eSSvyatoslav Ryhel		key-volume-down {
1926*118a745eSSvyatoslav Ryhel			label = "Volume Down";
1927*118a745eSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1928*118a745eSSvyatoslav Ryhel			linux,code = <KEY_VOLUMEDOWN>;
1929*118a745eSSvyatoslav Ryhel			debounce-interval = <10>;
1930*118a745eSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1931*118a745eSSvyatoslav Ryhel			wakeup-source;
1932*118a745eSSvyatoslav Ryhel		};
1933*118a745eSSvyatoslav Ryhel
1934*118a745eSSvyatoslav Ryhel		switch-docking-station-mode {
1935*118a745eSSvyatoslav Ryhel			label = "Mode";
1936*118a745eSSvyatoslav Ryhel			gpios = <&gpio TEGRA_GPIO(K, 2) GPIO_ACTIVE_LOW>;
1937*118a745eSSvyatoslav Ryhel			linux,code = <KEY_MODE>;
1938*118a745eSSvyatoslav Ryhel			debounce-interval = <10>;
1939*118a745eSSvyatoslav Ryhel			wakeup-event-action = <EV_ACT_ASSERTED>;
1940*118a745eSSvyatoslav Ryhel			wakeup-source;
1941*118a745eSSvyatoslav Ryhel		};
1942*118a745eSSvyatoslav Ryhel	};
1943*118a745eSSvyatoslav Ryhel
1944*118a745eSSvyatoslav Ryhel	opp-table-actmon {
1945*118a745eSSvyatoslav Ryhel		opp-800000000 {
1946*118a745eSSvyatoslav Ryhel			opp-supported-hw = <0x0006>;
1947*118a745eSSvyatoslav Ryhel		};
1948*118a745eSSvyatoslav Ryhel
1949*118a745eSSvyatoslav Ryhel		/delete-node/ opp-900000000;
1950*118a745eSSvyatoslav Ryhel	};
1951*118a745eSSvyatoslav Ryhel
1952*118a745eSSvyatoslav Ryhel	opp-table-emc {
1953*118a745eSSvyatoslav Ryhel		opp-800000000-1300 {
1954*118a745eSSvyatoslav Ryhel			opp-supported-hw = <0x0006>;
1955*118a745eSSvyatoslav Ryhel		};
1956*118a745eSSvyatoslav Ryhel
1957*118a745eSSvyatoslav Ryhel		/delete-node/ opp-900000000-1350;
1958*118a745eSSvyatoslav Ryhel	};
1959*118a745eSSvyatoslav Ryhel
1960*118a745eSSvyatoslav Ryhel	brcm_wifi_pwrseq: pwrseq-wifi {
1961*118a745eSSvyatoslav Ryhel		compatible = "mmc-pwrseq-simple";
1962*118a745eSSvyatoslav Ryhel
1963*118a745eSSvyatoslav Ryhel		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1964*118a745eSSvyatoslav Ryhel		clock-names = "ext_clock";
1965*118a745eSSvyatoslav Ryhel
1966*118a745eSSvyatoslav Ryhel		reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1967*118a745eSSvyatoslav Ryhel		post-power-on-delay-ms = <300>;
1968*118a745eSSvyatoslav Ryhel		power-off-delay-us = <300>;
1969*118a745eSSvyatoslav Ryhel	};
1970*118a745eSSvyatoslav Ryhel
1971*118a745eSSvyatoslav Ryhel	sound {
1972*118a745eSSvyatoslav Ryhel		compatible = "asus,tegra-audio-rt5640-p1801-t",
1973*118a745eSSvyatoslav Ryhel			     "nvidia,tegra-audio-rt5640";
1974*118a745eSSvyatoslav Ryhel		nvidia,model = "Asus Portable AiO P1801-T RT5642";
1975*118a745eSSvyatoslav Ryhel
1976*118a745eSSvyatoslav Ryhel		nvidia,audio-routing =
1977*118a745eSSvyatoslav Ryhel			"Headphones", "HPOR",
1978*118a745eSSvyatoslav Ryhel			"Headphones", "HPOL",
1979*118a745eSSvyatoslav Ryhel			"Speakers", "SPORP",
1980*118a745eSSvyatoslav Ryhel			"Speakers", "SPORN",
1981*118a745eSSvyatoslav Ryhel			"Speakers", "SPOLP",
1982*118a745eSSvyatoslav Ryhel			"Speakers", "SPOLN",
1983*118a745eSSvyatoslav Ryhel			"DMIC1", "Mic Jack";
1984*118a745eSSvyatoslav Ryhel
1985*118a745eSSvyatoslav Ryhel		nvidia,i2s-controller = <&tegra_i2s1>;
1986*118a745eSSvyatoslav Ryhel		nvidia,audio-codec = <&rt5640>;
1987*118a745eSSvyatoslav Ryhel
1988*118a745eSSvyatoslav Ryhel		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1989*118a745eSSvyatoslav Ryhel
1990*118a745eSSvyatoslav Ryhel		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1991*118a745eSSvyatoslav Ryhel			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1992*118a745eSSvyatoslav Ryhel			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1993*118a745eSSvyatoslav Ryhel		clock-names = "pll_a", "pll_a_out0", "mclk";
1994*118a745eSSvyatoslav Ryhel
1995*118a745eSSvyatoslav Ryhel		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1996*118a745eSSvyatoslav Ryhel				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1997*118a745eSSvyatoslav Ryhel
1998*118a745eSSvyatoslav Ryhel		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1999*118a745eSSvyatoslav Ryhel					 <&tegra_car TEGRA30_CLK_EXTERN1>;
2000*118a745eSSvyatoslav Ryhel	};
2001*118a745eSSvyatoslav Ryhel
2002*118a745eSSvyatoslav Ryhel	thermal-zones {
2003*118a745eSSvyatoslav Ryhel		/*
2004*118a745eSSvyatoslav Ryhel		 * NCT72 has two sensors:
2005*118a745eSSvyatoslav Ryhel		 *
2006*118a745eSSvyatoslav Ryhel		 *	0: internal that monitors ambient/skin temperature
2007*118a745eSSvyatoslav Ryhel		 *	1: external that is connected to the CPU's diode
2008*118a745eSSvyatoslav Ryhel		 *
2009*118a745eSSvyatoslav Ryhel		 * Ideally we should use userspace thermal governor,
2010*118a745eSSvyatoslav Ryhel		 * but it's a much more complex solution. The "skin"
2011*118a745eSSvyatoslav Ryhel		 * zone exists as a simpler solution which prevents
2012*118a745eSSvyatoslav Ryhel		 * the Portable AiO from getting too hot from a user's
2013*118a745eSSvyatoslav Ryhel		 * tactile perspective. The CPU zone is intended to
2014*118a745eSSvyatoslav Ryhel		 * protect silicon from damage.
2015*118a745eSSvyatoslav Ryhel		 */
2016*118a745eSSvyatoslav Ryhel
2017*118a745eSSvyatoslav Ryhel		skin-thermal {
2018*118a745eSSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
2019*118a745eSSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
2020*118a745eSSvyatoslav Ryhel
2021*118a745eSSvyatoslav Ryhel			thermal-sensors = <&nct72 0>;
2022*118a745eSSvyatoslav Ryhel
2023*118a745eSSvyatoslav Ryhel			trips {
2024*118a745eSSvyatoslav Ryhel				trip0: skin-alert {
2025*118a745eSSvyatoslav Ryhel					/* throttle at 57C until temperature drops to 56.8C */
2026*118a745eSSvyatoslav Ryhel					temperature = <57000>;
2027*118a745eSSvyatoslav Ryhel					hysteresis = <200>;
2028*118a745eSSvyatoslav Ryhel					type = "passive";
2029*118a745eSSvyatoslav Ryhel				};
2030*118a745eSSvyatoslav Ryhel
2031*118a745eSSvyatoslav Ryhel				trip1: skin-crit {
2032*118a745eSSvyatoslav Ryhel					/* shut down at 65C */
2033*118a745eSSvyatoslav Ryhel					temperature = <65000>;
2034*118a745eSSvyatoslav Ryhel					hysteresis = <2000>;
2035*118a745eSSvyatoslav Ryhel					type = "critical";
2036*118a745eSSvyatoslav Ryhel				};
2037*118a745eSSvyatoslav Ryhel			};
2038*118a745eSSvyatoslav Ryhel
2039*118a745eSSvyatoslav Ryhel			cooling-maps {
2040*118a745eSSvyatoslav Ryhel				map0 {
2041*118a745eSSvyatoslav Ryhel					trip = <&trip0>;
2042*118a745eSSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2043*118a745eSSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2044*118a745eSSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2045*118a745eSSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2046*118a745eSSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
2047*118a745eSSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
2048*118a745eSSvyatoslav Ryhel				};
2049*118a745eSSvyatoslav Ryhel			};
2050*118a745eSSvyatoslav Ryhel		};
2051*118a745eSSvyatoslav Ryhel
2052*118a745eSSvyatoslav Ryhel		cpu-thermal {
2053*118a745eSSvyatoslav Ryhel			polling-delay-passive = <1000>; /* milliseconds */
2054*118a745eSSvyatoslav Ryhel			polling-delay = <5000>; /* milliseconds */
2055*118a745eSSvyatoslav Ryhel
2056*118a745eSSvyatoslav Ryhel			thermal-sensors = <&nct72 1>;
2057*118a745eSSvyatoslav Ryhel
2058*118a745eSSvyatoslav Ryhel			trips {
2059*118a745eSSvyatoslav Ryhel				trip2: cpu-alert {
2060*118a745eSSvyatoslav Ryhel					/* throttle at 75C until temperature drops to 74.8C */
2061*118a745eSSvyatoslav Ryhel					temperature = <75000>;
2062*118a745eSSvyatoslav Ryhel					hysteresis = <200>;
2063*118a745eSSvyatoslav Ryhel					type = "passive";
2064*118a745eSSvyatoslav Ryhel				};
2065*118a745eSSvyatoslav Ryhel
2066*118a745eSSvyatoslav Ryhel				trip3: cpu-crit {
2067*118a745eSSvyatoslav Ryhel					/* shut down at 90C */
2068*118a745eSSvyatoslav Ryhel					temperature = <90000>;
2069*118a745eSSvyatoslav Ryhel					hysteresis = <2000>;
2070*118a745eSSvyatoslav Ryhel					type = "critical";
2071*118a745eSSvyatoslav Ryhel				};
2072*118a745eSSvyatoslav Ryhel			};
2073*118a745eSSvyatoslav Ryhel
2074*118a745eSSvyatoslav Ryhel			cooling-maps {
2075*118a745eSSvyatoslav Ryhel				map1 {
2076*118a745eSSvyatoslav Ryhel					trip = <&trip2>;
2077*118a745eSSvyatoslav Ryhel					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2078*118a745eSSvyatoslav Ryhel							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2079*118a745eSSvyatoslav Ryhel							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2080*118a745eSSvyatoslav Ryhel							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2081*118a745eSSvyatoslav Ryhel							 <&actmon THERMAL_NO_LIMIT
2082*118a745eSSvyatoslav Ryhel								  THERMAL_NO_LIMIT>;
2083*118a745eSSvyatoslav Ryhel				};
2084*118a745eSSvyatoslav Ryhel			};
2085*118a745eSSvyatoslav Ryhel		};
2086*118a745eSSvyatoslav Ryhel	};
2087*118a745eSSvyatoslav Ryhel};
2088