1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring 3*724ba675SRob Herring#include "tegra30-asus-nexus7-grouper-common.dtsi" 4*724ba675SRob Herring#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" 5*724ba675SRob Herring 6*724ba675SRob Herring/ { 7*724ba675SRob Herring compatible = "asus,grouper", "nvidia,tegra30"; 8*724ba675SRob Herring 9*724ba675SRob Herring pinmux@70000868 { 10*724ba675SRob Herring state_default: pinmux { 11*724ba675SRob Herring lcd_dc1_pd2 { 12*724ba675SRob Herring nvidia,pins = "lcd_dc1_pd2"; 13*724ba675SRob Herring nvidia,function = "displaya"; 14*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 15*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 16*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 17*724ba675SRob Herring }; 18*724ba675SRob Herring lcd_pwr2_pc6 { 19*724ba675SRob Herring nvidia,pins = "lcd_pwr2_pc6"; 20*724ba675SRob Herring nvidia,function = "displaya"; 21*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 22*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 23*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring spi2_cs2_n_pw3 { 26*724ba675SRob Herring nvidia,pins = "spi2_cs2_n_pw3"; 27*724ba675SRob Herring nvidia,function = "spi2"; 28*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 29*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 30*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring spi1_sck_px5 { 33*724ba675SRob Herring nvidia,pins = "spi1_sck_px5"; 34*724ba675SRob Herring nvidia,function = "spi1"; 35*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 36*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 37*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring pu5 { 40*724ba675SRob Herring nvidia,pins = "pu5"; 41*724ba675SRob Herring nvidia,function = "pwm2"; 42*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 43*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 44*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring spi1_miso_px7 { 47*724ba675SRob Herring nvidia,pins = "spi1_miso_px7"; 48*724ba675SRob Herring nvidia,function = "spi1"; 49*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 50*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 51*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring spi2_mosi_px0 { 54*724ba675SRob Herring nvidia,pins = "spi2_mosi_px0"; 55*724ba675SRob Herring nvidia,function = "spi2"; 56*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 57*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 58*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring kb_row7_pr7 { 61*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 62*724ba675SRob Herring nvidia,function = "kbc"; 63*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 64*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 65*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 66*724ba675SRob Herring }; 67*724ba675SRob Herring pu3 { 68*724ba675SRob Herring nvidia,pins = "pu3"; 69*724ba675SRob Herring nvidia,function = "rsvd4"; 70*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 71*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 72*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 73*724ba675SRob Herring }; 74*724ba675SRob Herring pu4 { 75*724ba675SRob Herring nvidia,pins = "pu4"; 76*724ba675SRob Herring nvidia,function = "pwm1"; 77*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 78*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 79*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring kb_row15_ps7 { 82*724ba675SRob Herring nvidia,pins = "kb_row15_ps7"; 83*724ba675SRob Herring nvidia,function = "kbc"; 84*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 85*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 86*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring kb_row3_pr3 { 89*724ba675SRob Herring nvidia,pins = "kb_row3_pr3"; 90*724ba675SRob Herring nvidia,function = "kbc"; 91*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 92*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 93*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring kb_row13_ps5 { 96*724ba675SRob Herring nvidia,pins = "kb_row13_ps5"; 97*724ba675SRob Herring nvidia,function = "kbc"; 98*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 99*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 100*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring gmi_wp_n_pc7 { 103*724ba675SRob Herring nvidia,pins = "gmi_wp_n_pc7", 104*724ba675SRob Herring "gmi_wait_pi7", 105*724ba675SRob Herring "gmi_cs4_n_pk2", 106*724ba675SRob Herring "gmi_cs3_n_pk4"; 107*724ba675SRob Herring nvidia,function = "rsvd1"; 108*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 109*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 110*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring gmi_cs6_n_pi3 { 113*724ba675SRob Herring nvidia,pins = "gmi_cs6_n_pi3"; 114*724ba675SRob Herring nvidia,function = "gmi"; 115*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 116*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 117*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 118*724ba675SRob Herring }; 119*724ba675SRob Herring }; 120*724ba675SRob Herring }; 121*724ba675SRob Herring 122*724ba675SRob Herring i2c@7000c500 { 123*724ba675SRob Herring nfc@28 { 124*724ba675SRob Herring compatible = "nxp,pn544-i2c"; 125*724ba675SRob Herring reg = <0x28>; 126*724ba675SRob Herring 127*724ba675SRob Herring interrupt-parent = <&gpio>; 128*724ba675SRob Herring interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>; 129*724ba675SRob Herring 130*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; 131*724ba675SRob Herring firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring }; 134*724ba675SRob Herring 135*724ba675SRob Herring display-panel { 136*724ba675SRob Herring panel-timing { 137*724ba675SRob Herring clock-frequency = <68000000>; 138*724ba675SRob Herring hactive = <800>; 139*724ba675SRob Herring vactive = <1280>; 140*724ba675SRob Herring hfront-porch = <24>; 141*724ba675SRob Herring hback-porch = <32>; 142*724ba675SRob Herring hsync-len = <24>; 143*724ba675SRob Herring vsync-len = <1>; 144*724ba675SRob Herring vfront-porch = <5>; 145*724ba675SRob Herring vback-porch = <32>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring }; 148*724ba675SRob Herring}; 149