1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring 3*724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h> 4*724ba675SRob Herring#include <dt-bindings/input/input.h> 5*724ba675SRob Herring#include <dt-bindings/power/summit,smb347-charger.h> 6*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 7*724ba675SRob Herring 8*724ba675SRob Herring#include "tegra30.dtsi" 9*724ba675SRob Herring#include "tegra30-cpu-opp.dtsi" 10*724ba675SRob Herring#include "tegra30-cpu-opp-microvolt.dtsi" 11*724ba675SRob Herring#include "tegra30-asus-lvds-display.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring aliases { 15*724ba675SRob Herring mmc0 = &sdmmc4; /* eMMC */ 16*724ba675SRob Herring mmc1 = &sdmmc3; /* WiFi */ 17*724ba675SRob Herring 18*724ba675SRob Herring rtc0 = &pmic; 19*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 20*724ba675SRob Herring 21*724ba675SRob Herring serial1 = &uartc; /* Bluetooth */ 22*724ba675SRob Herring serial2 = &uartb; /* GPS */ 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring /* 26*724ba675SRob Herring * The decompressor and also some bootloaders rely on a 27*724ba675SRob Herring * pre-existing /chosen node to be available to insert the 28*724ba675SRob Herring * command line and merge other ATAGS info. 29*724ba675SRob Herring */ 30*724ba675SRob Herring chosen {}; 31*724ba675SRob Herring 32*724ba675SRob Herring firmware { 33*724ba675SRob Herring trusted-foundations { 34*724ba675SRob Herring compatible = "tlm,trusted-foundations"; 35*724ba675SRob Herring tlm,version-major = <0x0>; 36*724ba675SRob Herring tlm,version-minor = <0x0>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring memory@80000000 { 41*724ba675SRob Herring reg = <0x80000000 0x40000000>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring reserved-memory { 45*724ba675SRob Herring #address-cells = <1>; 46*724ba675SRob Herring #size-cells = <1>; 47*724ba675SRob Herring ranges; 48*724ba675SRob Herring 49*724ba675SRob Herring linux,cma@80000000 { 50*724ba675SRob Herring compatible = "shared-dma-pool"; 51*724ba675SRob Herring alloc-ranges = <0x80000000 0x30000000>; 52*724ba675SRob Herring size = <0x10000000>; /* 256MiB */ 53*724ba675SRob Herring linux,cma-default; 54*724ba675SRob Herring reusable; 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring ramoops@bfdf0000 { 58*724ba675SRob Herring compatible = "ramoops"; 59*724ba675SRob Herring reg = <0xbfdf0000 0x10000>; /* 64kB */ 60*724ba675SRob Herring console-size = <0x8000>; /* 32kB */ 61*724ba675SRob Herring record-size = <0x400>; /* 1kB */ 62*724ba675SRob Herring ecc-size = <16>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring trustzone@bfe00000 { 66*724ba675SRob Herring reg = <0xbfe00000 0x200000>; 67*724ba675SRob Herring no-map; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring gpio@6000d000 { 72*724ba675SRob Herring init-low-power-mode-hog { 73*724ba675SRob Herring gpio-hog; 74*724ba675SRob Herring gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 75*724ba675SRob Herring input; 76*724ba675SRob Herring }; 77*724ba675SRob Herring 78*724ba675SRob Herring init-mode-hog { 79*724ba675SRob Herring gpio-hog; 80*724ba675SRob Herring gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, 81*724ba675SRob Herring <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, 82*724ba675SRob Herring <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 83*724ba675SRob Herring output-low; 84*724ba675SRob Herring }; 85*724ba675SRob Herring }; 86*724ba675SRob Herring 87*724ba675SRob Herring pinmux@70000868 { 88*724ba675SRob Herring pinctrl-names = "default"; 89*724ba675SRob Herring pinctrl-0 = <&state_default>; 90*724ba675SRob Herring 91*724ba675SRob Herring state_default: pinmux { 92*724ba675SRob Herring clk_32k_out_pa0 { 93*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 94*724ba675SRob Herring nvidia,function = "blink"; 95*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 96*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 97*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring uart3_cts_n_pa1 { 100*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1", 101*724ba675SRob Herring "uart3_rxd_pw7"; 102*724ba675SRob Herring nvidia,function = "uartc"; 103*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 104*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 105*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring dap2_fs_pa2 { 108*724ba675SRob Herring nvidia,pins = "dap2_fs_pa2", 109*724ba675SRob Herring "dap2_sclk_pa3", 110*724ba675SRob Herring "dap2_din_pa4", 111*724ba675SRob Herring "dap2_dout_pa5"; 112*724ba675SRob Herring nvidia,function = "i2s1"; 113*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 114*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 115*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring sdmmc3_clk_pa6 { 118*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 119*724ba675SRob Herring nvidia,function = "sdmmc3"; 120*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 121*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 122*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 123*724ba675SRob Herring }; 124*724ba675SRob Herring sdmmc3_cmd_pa7 { 125*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7", 126*724ba675SRob Herring "sdmmc3_dat3_pb4", 127*724ba675SRob Herring "sdmmc3_dat2_pb5", 128*724ba675SRob Herring "sdmmc3_dat1_pb6", 129*724ba675SRob Herring "sdmmc3_dat0_pb7", 130*724ba675SRob Herring "sdmmc3_dat4_pd1", 131*724ba675SRob Herring "sdmmc3_dat6_pd3", 132*724ba675SRob Herring "sdmmc3_dat7_pd4"; 133*724ba675SRob Herring nvidia,function = "sdmmc3"; 134*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 135*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 136*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 137*724ba675SRob Herring }; 138*724ba675SRob Herring gmi_a17_pb0 { 139*724ba675SRob Herring nvidia,pins = "gmi_a17_pb0", 140*724ba675SRob Herring "gmi_a18_pb1"; 141*724ba675SRob Herring nvidia,function = "uartd"; 142*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 143*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 144*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 145*724ba675SRob Herring }; 146*724ba675SRob Herring lcd_pwr0_pb2 { 147*724ba675SRob Herring nvidia,pins = "lcd_pwr0_pb2", 148*724ba675SRob Herring "lcd_pwr1_pc1", 149*724ba675SRob Herring "lcd_m1_pw1"; 150*724ba675SRob Herring nvidia,function = "displaya"; 151*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 152*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 153*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 154*724ba675SRob Herring }; 155*724ba675SRob Herring lcd_pclk_pb3 { 156*724ba675SRob Herring nvidia,pins = "lcd_pclk_pb3", 157*724ba675SRob Herring "lcd_d0_pe0", 158*724ba675SRob Herring "lcd_d1_pe1", 159*724ba675SRob Herring "lcd_d2_pe2", 160*724ba675SRob Herring "lcd_d3_pe3", 161*724ba675SRob Herring "lcd_d4_pe4", 162*724ba675SRob Herring "lcd_d5_pe5", 163*724ba675SRob Herring "lcd_d6_pe6", 164*724ba675SRob Herring "lcd_d7_pe7", 165*724ba675SRob Herring "lcd_d8_pf0", 166*724ba675SRob Herring "lcd_d9_pf1", 167*724ba675SRob Herring "lcd_d10_pf2", 168*724ba675SRob Herring "lcd_d11_pf3", 169*724ba675SRob Herring "lcd_d12_pf4", 170*724ba675SRob Herring "lcd_d13_pf5", 171*724ba675SRob Herring "lcd_d14_pf6", 172*724ba675SRob Herring "lcd_d15_pf7", 173*724ba675SRob Herring "lcd_de_pj1", 174*724ba675SRob Herring "lcd_hsync_pj3", 175*724ba675SRob Herring "lcd_vsync_pj4", 176*724ba675SRob Herring "lcd_d16_pm0", 177*724ba675SRob Herring "lcd_d17_pm1", 178*724ba675SRob Herring "lcd_d18_pm2", 179*724ba675SRob Herring "lcd_d19_pm3", 180*724ba675SRob Herring "lcd_d20_pm4", 181*724ba675SRob Herring "lcd_d21_pm5", 182*724ba675SRob Herring "lcd_d22_pm6", 183*724ba675SRob Herring "lcd_d23_pm7", 184*724ba675SRob Herring "lcd_cs0_n_pn4", 185*724ba675SRob Herring "lcd_sdout_pn5", 186*724ba675SRob Herring "lcd_dc0_pn6", 187*724ba675SRob Herring "lcd_cs1_n_pw0", 188*724ba675SRob Herring "lcd_sdin_pz2", 189*724ba675SRob Herring "lcd_sck_pz4"; 190*724ba675SRob Herring nvidia,function = "displaya"; 191*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 192*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 193*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring uart3_rts_n_pc0 { 196*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0", 197*724ba675SRob Herring "uart3_txd_pw6"; 198*724ba675SRob Herring nvidia,function = "uartc"; 199*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 200*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 201*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 202*724ba675SRob Herring }; 203*724ba675SRob Herring uart2_txd_pc2 { 204*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2", 205*724ba675SRob Herring "uart2_rts_n_pj6"; 206*724ba675SRob Herring nvidia,function = "uartb"; 207*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 209*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 210*724ba675SRob Herring }; 211*724ba675SRob Herring uart2_rxd_pc3 { 212*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3", 213*724ba675SRob Herring "uart2_cts_n_pj5"; 214*724ba675SRob Herring nvidia,function = "uartb"; 215*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 217*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring gen1_i2c_scl_pc4 { 220*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4", 221*724ba675SRob Herring "gen1_i2c_sda_pc5"; 222*724ba675SRob Herring nvidia,function = "i2c1"; 223*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 224*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 225*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 226*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring gmi_wp_n_pc7 { 229*724ba675SRob Herring nvidia,pins = "gmi_wp_n_pc7", 230*724ba675SRob Herring "gmi_wait_pi7", 231*724ba675SRob Herring "gmi_cs4_n_pk2", 232*724ba675SRob Herring "gmi_cs3_n_pk4"; 233*724ba675SRob Herring nvidia,function = "rsvd1"; 234*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 235*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 236*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 237*724ba675SRob Herring }; 238*724ba675SRob Herring gmi_ad12_ph4 { 239*724ba675SRob Herring nvidia,pins = "gmi_ad12_ph4", 240*724ba675SRob Herring "gmi_cs0_n_pj0", 241*724ba675SRob Herring "gmi_cs1_n_pj2", 242*724ba675SRob Herring "gmi_cs2_n_pk3"; 243*724ba675SRob Herring nvidia,function = "rsvd1"; 244*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 245*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 246*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 247*724ba675SRob Herring }; 248*724ba675SRob Herring sdmmc3_dat5_pd0 { 249*724ba675SRob Herring nvidia,pins = "sdmmc3_dat5_pd0"; 250*724ba675SRob Herring nvidia,function = "sdmmc3"; 251*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 252*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 253*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 254*724ba675SRob Herring }; 255*724ba675SRob Herring gmi_ad0_pg0 { 256*724ba675SRob Herring nvidia,pins = "gmi_ad0_pg0", 257*724ba675SRob Herring "gmi_ad1_pg1", 258*724ba675SRob Herring "gmi_ad14_ph6", 259*724ba675SRob Herring "pu1"; 260*724ba675SRob Herring nvidia,function = "rsvd1"; 261*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 262*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 263*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 264*724ba675SRob Herring }; 265*724ba675SRob Herring gmi_ad2_pg2 { 266*724ba675SRob Herring nvidia,pins = "gmi_ad2_pg2", 267*724ba675SRob Herring "gmi_ad3_pg3", 268*724ba675SRob Herring "gmi_ad6_pg6", 269*724ba675SRob Herring "gmi_ad7_pg7"; 270*724ba675SRob Herring nvidia,function = "rsvd1"; 271*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 272*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 273*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 274*724ba675SRob Herring }; 275*724ba675SRob Herring gmi_ad4_pg4 { 276*724ba675SRob Herring nvidia,pins = "gmi_ad4_pg4", 277*724ba675SRob Herring "gmi_ad5_pg5"; 278*724ba675SRob Herring nvidia,function = "nand"; 279*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 280*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 281*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 282*724ba675SRob Herring }; 283*724ba675SRob Herring gmi_ad8_ph0 { 284*724ba675SRob Herring nvidia,pins = "gmi_ad8_ph0"; 285*724ba675SRob Herring nvidia,function = "pwm0"; 286*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 287*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 288*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 289*724ba675SRob Herring }; 290*724ba675SRob Herring gmi_ad9_ph1 { 291*724ba675SRob Herring nvidia,pins = "gmi_ad9_ph1"; 292*724ba675SRob Herring nvidia,function = "rsvd4"; 293*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 294*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 295*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 296*724ba675SRob Herring }; 297*724ba675SRob Herring gmi_ad10_ph2 { 298*724ba675SRob Herring nvidia,pins = "gmi_ad10_ph2"; 299*724ba675SRob Herring nvidia,function = "pwm2"; 300*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 301*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 302*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring gmi_ad11_ph3 { 305*724ba675SRob Herring nvidia,pins = "gmi_ad11_ph3"; 306*724ba675SRob Herring nvidia,function = "pwm3"; 307*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 308*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 309*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 310*724ba675SRob Herring }; 311*724ba675SRob Herring gmi_ad13_ph5 { 312*724ba675SRob Herring nvidia,pins = "gmi_ad13_ph5", 313*724ba675SRob Herring "gmi_wr_n_pi0", 314*724ba675SRob Herring "gmi_oe_n_pi1", 315*724ba675SRob Herring "gmi_adv_n_pk0"; 316*724ba675SRob Herring nvidia,function = "rsvd1"; 317*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 318*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 319*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 320*724ba675SRob Herring }; 321*724ba675SRob Herring gmi_ad15_ph7 { 322*724ba675SRob Herring nvidia,pins = "gmi_ad15_ph7"; 323*724ba675SRob Herring nvidia,function = "rsvd1"; 324*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 325*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 326*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring gmi_dqs_pi2 { 329*724ba675SRob Herring nvidia,pins = "gmi_dqs_pi2", 330*724ba675SRob Herring "pu2", 331*724ba675SRob Herring "pv1"; 332*724ba675SRob Herring nvidia,function = "rsvd1"; 333*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 334*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 335*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 336*724ba675SRob Herring }; 337*724ba675SRob Herring gmi_rst_n_pi4 { 338*724ba675SRob Herring nvidia,pins = "gmi_rst_n_pi4"; 339*724ba675SRob Herring nvidia,function = "nand"; 340*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 341*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 342*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 343*724ba675SRob Herring }; 344*724ba675SRob Herring gmi_iordy_pi5 { 345*724ba675SRob Herring nvidia,pins = "gmi_iordy_pi5"; 346*724ba675SRob Herring nvidia,function = "rsvd1"; 347*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 348*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 349*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 350*724ba675SRob Herring }; 351*724ba675SRob Herring gmi_cs7_n_pi6 { 352*724ba675SRob Herring nvidia,pins = "gmi_cs7_n_pi6", 353*724ba675SRob Herring "gmi_clk_pk1"; 354*724ba675SRob Herring nvidia,function = "nand"; 355*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 356*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 357*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 358*724ba675SRob Herring }; 359*724ba675SRob Herring gmi_a16_pj7 { 360*724ba675SRob Herring nvidia,pins = "gmi_a16_pj7", 361*724ba675SRob Herring "gmi_a19_pk7"; 362*724ba675SRob Herring nvidia,function = "uartd"; 363*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 364*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 365*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 366*724ba675SRob Herring }; 367*724ba675SRob Herring spdif_out_pk5 { 368*724ba675SRob Herring nvidia,pins = "spdif_out_pk5"; 369*724ba675SRob Herring nvidia,function = "spdif"; 370*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 371*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 372*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 373*724ba675SRob Herring }; 374*724ba675SRob Herring spdif_in_pk6 { 375*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 376*724ba675SRob Herring nvidia,function = "spdif"; 377*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 378*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 379*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring dap1_fs_pn0 { 382*724ba675SRob Herring nvidia,pins = "dap1_fs_pn0", 383*724ba675SRob Herring "dap1_din_pn1", 384*724ba675SRob Herring "dap1_dout_pn2", 385*724ba675SRob Herring "dap1_sclk_pn3"; 386*724ba675SRob Herring nvidia,function = "i2s0"; 387*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 388*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 389*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 390*724ba675SRob Herring }; 391*724ba675SRob Herring hdmi_int_pn7 { 392*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 393*724ba675SRob Herring nvidia,function = "hdmi"; 394*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 395*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 396*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 397*724ba675SRob Herring }; 398*724ba675SRob Herring ulpi_data7_po0 { 399*724ba675SRob Herring nvidia,pins = "ulpi_data7_po0"; 400*724ba675SRob Herring nvidia,function = "uarta"; 401*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 402*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 403*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 404*724ba675SRob Herring }; 405*724ba675SRob Herring ulpi_data3_po4 { 406*724ba675SRob Herring nvidia,pins = "ulpi_data3_po4"; 407*724ba675SRob Herring nvidia,function = "ulpi"; 408*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 409*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 410*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring dap3_fs_pp0 { 413*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0"; 414*724ba675SRob Herring nvidia,function = "i2s2"; 415*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 416*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 417*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 418*724ba675SRob Herring }; 419*724ba675SRob Herring dap4_fs_pp4 { 420*724ba675SRob Herring nvidia,pins = "dap4_fs_pp4", 421*724ba675SRob Herring "dap4_din_pp5", 422*724ba675SRob Herring "dap4_dout_pp6", 423*724ba675SRob Herring "dap4_sclk_pp7"; 424*724ba675SRob Herring nvidia,function = "i2s3"; 425*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 426*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 427*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 428*724ba675SRob Herring }; 429*724ba675SRob Herring kb_col0_pq0 { 430*724ba675SRob Herring nvidia,pins = "kb_col0_pq0", 431*724ba675SRob Herring "kb_col1_pq1", 432*724ba675SRob Herring "kb_row1_pr1"; 433*724ba675SRob Herring nvidia,function = "kbc"; 434*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 436*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring kb_col2_pq2 { 439*724ba675SRob Herring nvidia,pins = "kb_col2_pq2", 440*724ba675SRob Herring "kb_col3_pq3"; 441*724ba675SRob Herring nvidia,function = "rsvd4"; 442*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 443*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 444*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 445*724ba675SRob Herring }; 446*724ba675SRob Herring kb_col4_pq4 { 447*724ba675SRob Herring nvidia,pins = "kb_col4_pq4", 448*724ba675SRob Herring "kb_col5_pq5", 449*724ba675SRob Herring "kb_col7_pq7", 450*724ba675SRob Herring "kb_row2_pr2", 451*724ba675SRob Herring "kb_row4_pr4", 452*724ba675SRob Herring "kb_row5_pr5", 453*724ba675SRob Herring "kb_row14_ps6"; 454*724ba675SRob Herring nvidia,function = "kbc"; 455*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 456*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 457*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 458*724ba675SRob Herring }; 459*724ba675SRob Herring kb_row0_pr0 { 460*724ba675SRob Herring nvidia,pins = "kb_row0_pr0"; 461*724ba675SRob Herring nvidia,function = "rsvd4"; 462*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 463*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 464*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 465*724ba675SRob Herring }; 466*724ba675SRob Herring kb_row6_pr6 { 467*724ba675SRob Herring nvidia,pins = "kb_row6_pr6", 468*724ba675SRob Herring "kb_row8_ps0", 469*724ba675SRob Herring "kb_row9_ps1", 470*724ba675SRob Herring "kb_row10_ps2"; 471*724ba675SRob Herring nvidia,function = "kbc"; 472*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 473*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 474*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 475*724ba675SRob Herring }; 476*724ba675SRob Herring kb_row11_ps3 { 477*724ba675SRob Herring nvidia,pins = "kb_row11_ps3", 478*724ba675SRob Herring "kb_row12_ps4"; 479*724ba675SRob Herring nvidia,function = "kbc"; 480*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 481*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 482*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 483*724ba675SRob Herring }; 484*724ba675SRob Herring gen2_i2c_scl_pt5 { 485*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5", 486*724ba675SRob Herring "gen2_i2c_sda_pt6"; 487*724ba675SRob Herring nvidia,function = "i2c2"; 488*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 489*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 490*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 491*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 492*724ba675SRob Herring }; 493*724ba675SRob Herring sdmmc4_cmd_pt7 { 494*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7", 495*724ba675SRob Herring "sdmmc4_dat0_paa0", 496*724ba675SRob Herring "sdmmc4_dat1_paa1", 497*724ba675SRob Herring "sdmmc4_dat2_paa2", 498*724ba675SRob Herring "sdmmc4_dat3_paa3", 499*724ba675SRob Herring "sdmmc4_dat4_paa4", 500*724ba675SRob Herring "sdmmc4_dat5_paa5", 501*724ba675SRob Herring "sdmmc4_dat6_paa6", 502*724ba675SRob Herring "sdmmc4_dat7_paa7"; 503*724ba675SRob Herring nvidia,function = "sdmmc4"; 504*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 505*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 506*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 507*724ba675SRob Herring }; 508*724ba675SRob Herring pu0 { 509*724ba675SRob Herring nvidia,pins = "pu0", 510*724ba675SRob Herring "pu6"; 511*724ba675SRob Herring nvidia,function = "rsvd4"; 512*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 513*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 514*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515*724ba675SRob Herring }; 516*724ba675SRob Herring jtag_rtck_pu7 { 517*724ba675SRob Herring nvidia,pins = "jtag_rtck_pu7"; 518*724ba675SRob Herring nvidia,function = "rtck"; 519*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 520*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 521*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 522*724ba675SRob Herring }; 523*724ba675SRob Herring pv0 { 524*724ba675SRob Herring nvidia,pins = "pv0"; 525*724ba675SRob Herring nvidia,function = "rsvd1"; 526*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 527*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 528*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 529*724ba675SRob Herring }; 530*724ba675SRob Herring ddc_scl_pv4 { 531*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4", 532*724ba675SRob Herring "ddc_sda_pv5"; 533*724ba675SRob Herring nvidia,function = "i2c4"; 534*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 535*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 536*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 537*724ba675SRob Herring }; 538*724ba675SRob Herring crt_hsync_pv6 { 539*724ba675SRob Herring nvidia,pins = "crt_hsync_pv6", 540*724ba675SRob Herring "crt_vsync_pv7"; 541*724ba675SRob Herring nvidia,function = "crt"; 542*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 544*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 545*724ba675SRob Herring }; 546*724ba675SRob Herring spi2_cs1_n_pw2 { 547*724ba675SRob Herring nvidia,pins = "spi2_cs1_n_pw2", 548*724ba675SRob Herring "spi2_miso_px1", 549*724ba675SRob Herring "spi2_sck_px2"; 550*724ba675SRob Herring nvidia,function = "spi2"; 551*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 552*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 553*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 554*724ba675SRob Herring }; 555*724ba675SRob Herring clk1_out_pw4 { 556*724ba675SRob Herring nvidia,pins = "clk1_out_pw4"; 557*724ba675SRob Herring nvidia,function = "extperiph1"; 558*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 559*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 560*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 561*724ba675SRob Herring }; 562*724ba675SRob Herring clk2_out_pw5 { 563*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 564*724ba675SRob Herring nvidia,function = "extperiph2"; 565*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 566*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 567*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 568*724ba675SRob Herring }; 569*724ba675SRob Herring spi2_cs0_n_px3 { 570*724ba675SRob Herring nvidia,pins = "spi2_cs0_n_px3"; 571*724ba675SRob Herring nvidia,function = "spi6"; 572*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 573*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 574*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 575*724ba675SRob Herring }; 576*724ba675SRob Herring spi1_mosi_px4 { 577*724ba675SRob Herring nvidia,pins = "spi1_mosi_px4", 578*724ba675SRob Herring "spi1_cs0_n_px6"; 579*724ba675SRob Herring nvidia,function = "spi1"; 580*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 581*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 582*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 583*724ba675SRob Herring }; 584*724ba675SRob Herring ulpi_clk_py0 { 585*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0", 586*724ba675SRob Herring "ulpi_dir_py1"; 587*724ba675SRob Herring nvidia,function = "ulpi"; 588*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 589*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 590*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 591*724ba675SRob Herring }; 592*724ba675SRob Herring sdmmc1_dat3_py4 { 593*724ba675SRob Herring nvidia,pins = "sdmmc1_dat3_py4", 594*724ba675SRob Herring "sdmmc1_dat2_py5", 595*724ba675SRob Herring "sdmmc1_dat1_py6", 596*724ba675SRob Herring "sdmmc1_dat0_py7", 597*724ba675SRob Herring "sdmmc1_cmd_pz1"; 598*724ba675SRob Herring nvidia,function = "sdmmc1"; 599*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 600*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 601*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 602*724ba675SRob Herring }; 603*724ba675SRob Herring sdmmc1_clk_pz0 { 604*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 605*724ba675SRob Herring nvidia,function = "sdmmc1"; 606*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 607*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 608*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 609*724ba675SRob Herring }; 610*724ba675SRob Herring lcd_wr_n_pz3 { 611*724ba675SRob Herring nvidia,pins = "lcd_wr_n_pz3"; 612*724ba675SRob Herring nvidia,function = "displaya"; 613*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 614*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 615*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 616*724ba675SRob Herring }; 617*724ba675SRob Herring sys_clk_req_pz5 { 618*724ba675SRob Herring nvidia,pins = "sys_clk_req_pz5"; 619*724ba675SRob Herring nvidia,function = "sysclk"; 620*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 621*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 622*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 623*724ba675SRob Herring }; 624*724ba675SRob Herring pwr_i2c_scl_pz6 { 625*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6", 626*724ba675SRob Herring "pwr_i2c_sda_pz7"; 627*724ba675SRob Herring nvidia,function = "i2cpwr"; 628*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 629*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 630*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 631*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 632*724ba675SRob Herring }; 633*724ba675SRob Herring pbb0 { 634*724ba675SRob Herring nvidia,pins = "pbb0", 635*724ba675SRob Herring "pcc1"; 636*724ba675SRob Herring nvidia,function = "rsvd2"; 637*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 639*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 640*724ba675SRob Herring }; 641*724ba675SRob Herring cam_i2c_scl_pbb1 { 642*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1", 643*724ba675SRob Herring "cam_i2c_sda_pbb2"; 644*724ba675SRob Herring nvidia,function = "i2c3"; 645*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 647*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 649*724ba675SRob Herring }; 650*724ba675SRob Herring pbb3 { 651*724ba675SRob Herring nvidia,pins = "pbb3"; 652*724ba675SRob Herring nvidia,function = "vgp3"; 653*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 655*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 656*724ba675SRob Herring }; 657*724ba675SRob Herring pbb4 { 658*724ba675SRob Herring nvidia,pins = "pbb4"; 659*724ba675SRob Herring nvidia,function = "vgp4"; 660*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 661*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 662*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 663*724ba675SRob Herring }; 664*724ba675SRob Herring pbb5 { 665*724ba675SRob Herring nvidia,pins = "pbb5"; 666*724ba675SRob Herring nvidia,function = "vgp5"; 667*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 668*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 669*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 670*724ba675SRob Herring }; 671*724ba675SRob Herring pbb6 { 672*724ba675SRob Herring nvidia,pins = "pbb6"; 673*724ba675SRob Herring nvidia,function = "vgp6"; 674*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 675*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 676*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 677*724ba675SRob Herring }; 678*724ba675SRob Herring pbb7 { 679*724ba675SRob Herring nvidia,pins = "pbb7", 680*724ba675SRob Herring "pcc2"; 681*724ba675SRob Herring nvidia,function = "i2s4"; 682*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 683*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 684*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 685*724ba675SRob Herring }; 686*724ba675SRob Herring cam_mclk_pcc0 { 687*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0"; 688*724ba675SRob Herring nvidia,function = "vi_alt3"; 689*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 690*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 691*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 692*724ba675SRob Herring }; 693*724ba675SRob Herring sdmmc4_rst_n_pcc3 { 694*724ba675SRob Herring nvidia,pins = "sdmmc4_rst_n_pcc3"; 695*724ba675SRob Herring nvidia,function = "rsvd2"; 696*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 697*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 698*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 699*724ba675SRob Herring }; 700*724ba675SRob Herring sdmmc4_clk_pcc4 { 701*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 702*724ba675SRob Herring nvidia,function = "sdmmc4"; 703*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 704*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 705*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 706*724ba675SRob Herring }; 707*724ba675SRob Herring clk2_req_pcc5 { 708*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 709*724ba675SRob Herring nvidia,function = "dap"; 710*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 712*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 713*724ba675SRob Herring }; 714*724ba675SRob Herring pex_l2_rst_n_pcc6 { 715*724ba675SRob Herring nvidia,pins = "pex_l2_rst_n_pcc6", 716*724ba675SRob Herring "pex_l2_clkreq_n_pcc7"; 717*724ba675SRob Herring nvidia,function = "pcie"; 718*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 719*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 720*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 721*724ba675SRob Herring }; 722*724ba675SRob Herring pex_wake_n_pdd3 { 723*724ba675SRob Herring nvidia,pins = "pex_wake_n_pdd3", 724*724ba675SRob Herring "pex_l2_prsnt_n_pdd7"; 725*724ba675SRob Herring nvidia,function = "pcie"; 726*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 727*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 728*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 729*724ba675SRob Herring }; 730*724ba675SRob Herring clk3_out_pee0 { 731*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 732*724ba675SRob Herring nvidia,function = "extperiph3"; 733*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 734*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 735*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 736*724ba675SRob Herring }; 737*724ba675SRob Herring clk1_req_pee2 { 738*724ba675SRob Herring nvidia,pins = "clk1_req_pee2"; 739*724ba675SRob Herring nvidia,function = "dap"; 740*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 741*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 742*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 743*724ba675SRob Herring }; 744*724ba675SRob Herring hdmi_cec_pee3 { 745*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 746*724ba675SRob Herring nvidia,function = "cec"; 747*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 748*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 749*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 750*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 751*724ba675SRob Herring }; 752*724ba675SRob Herring owr { 753*724ba675SRob Herring nvidia,pins = "owr"; 754*724ba675SRob Herring nvidia,function = "owr"; 755*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 756*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 757*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 758*724ba675SRob Herring }; 759*724ba675SRob Herring drive_dap1 { 760*724ba675SRob Herring nvidia,pins = "drive_dap1", 761*724ba675SRob Herring "drive_dap2", 762*724ba675SRob Herring "drive_dbg", 763*724ba675SRob Herring "drive_at5", 764*724ba675SRob Herring "drive_gme", 765*724ba675SRob Herring "drive_ddc", 766*724ba675SRob Herring "drive_ao1", 767*724ba675SRob Herring "drive_uart3"; 768*724ba675SRob Herring nvidia,high-speed-mode = <0>; 769*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_ENABLE>; 770*724ba675SRob Herring nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 771*724ba675SRob Herring nvidia,pull-down-strength = <31>; 772*724ba675SRob Herring nvidia,pull-up-strength = <31>; 773*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 774*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 775*724ba675SRob Herring }; 776*724ba675SRob Herring drive_sdio1 { 777*724ba675SRob Herring nvidia,pins = "drive_sdio1", 778*724ba675SRob Herring "drive_sdio3"; 779*724ba675SRob Herring nvidia,high-speed-mode = <0>; 780*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 781*724ba675SRob Herring nvidia,pull-down-strength = <46>; 782*724ba675SRob Herring nvidia,pull-up-strength = <42>; 783*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 784*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 785*724ba675SRob Herring }; 786*724ba675SRob Herring drive_gma { 787*724ba675SRob Herring nvidia,pins = "drive_gma", 788*724ba675SRob Herring "drive_gmb", 789*724ba675SRob Herring "drive_gmc", 790*724ba675SRob Herring "drive_gmd"; 791*724ba675SRob Herring nvidia,pull-down-strength = <9>; 792*724ba675SRob Herring nvidia,pull-up-strength = <9>; 793*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 794*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 795*724ba675SRob Herring }; 796*724ba675SRob Herring }; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring uartb: serial@70006040 { 800*724ba675SRob Herring compatible = "nvidia,tegra30-hsuart"; 801*724ba675SRob Herring /delete-property/ reg-shift; 802*724ba675SRob Herring /* GPS BCM4751 */ 803*724ba675SRob Herring }; 804*724ba675SRob Herring 805*724ba675SRob Herring uartc: serial@70006200 { 806*724ba675SRob Herring compatible = "nvidia,tegra30-hsuart"; 807*724ba675SRob Herring /delete-property/ reg-shift; 808*724ba675SRob Herring status = "okay"; 809*724ba675SRob Herring 810*724ba675SRob Herring nvidia,adjust-baud-rates = <0 9600 100>, 811*724ba675SRob Herring <9600 115200 200>, 812*724ba675SRob Herring <1000000 4000000 136>; 813*724ba675SRob Herring 814*724ba675SRob Herring /* Azurewave AW-NH665 BCM4330B1 */ 815*724ba675SRob Herring bluetooth { 816*724ba675SRob Herring compatible = "brcm,bcm4330-bt"; 817*724ba675SRob Herring 818*724ba675SRob Herring interrupt-parent = <&gpio>; 819*724ba675SRob Herring interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 820*724ba675SRob Herring interrupt-names = "host-wakeup"; 821*724ba675SRob Herring 822*724ba675SRob Herring max-speed = <4000000>; 823*724ba675SRob Herring 824*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 825*724ba675SRob Herring clock-names = "txco"; 826*724ba675SRob Herring 827*724ba675SRob Herring vbat-supply = <&vdd_3v3_sys>; 828*724ba675SRob Herring vddio-supply = <&vdd_1v8>; 829*724ba675SRob Herring 830*724ba675SRob Herring device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 831*724ba675SRob Herring shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 832*724ba675SRob Herring }; 833*724ba675SRob Herring }; 834*724ba675SRob Herring 835*724ba675SRob Herring pwm: pwm@7000a000 { 836*724ba675SRob Herring status = "okay"; 837*724ba675SRob Herring }; 838*724ba675SRob Herring 839*724ba675SRob Herring i2c@7000c400 { 840*724ba675SRob Herring clock-frequency = <400000>; 841*724ba675SRob Herring status = "okay"; 842*724ba675SRob Herring 843*724ba675SRob Herring touchscreen@10 { 844*724ba675SRob Herring compatible = "elan,ektf3624"; 845*724ba675SRob Herring reg = <0x10>; 846*724ba675SRob Herring 847*724ba675SRob Herring interrupt-parent = <&gpio>; 848*724ba675SRob Herring interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; 849*724ba675SRob Herring 850*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 851*724ba675SRob Herring 852*724ba675SRob Herring vcc33-supply = <&vcc_3v3_ts>; 853*724ba675SRob Herring vccio-supply = <&vcc_3v3_ts>; 854*724ba675SRob Herring 855*724ba675SRob Herring touchscreen-size-x = <2112>; 856*724ba675SRob Herring touchscreen-size-y = <1280>; 857*724ba675SRob Herring touchscreen-swapped-x-y; 858*724ba675SRob Herring touchscreen-inverted-x; 859*724ba675SRob Herring }; 860*724ba675SRob Herring }; 861*724ba675SRob Herring 862*724ba675SRob Herring i2c@7000c500 { 863*724ba675SRob Herring clock-frequency = <100000>; 864*724ba675SRob Herring status = "okay"; 865*724ba675SRob Herring 866*724ba675SRob Herring compass@e { 867*724ba675SRob Herring compatible = "asahi-kasei,ak8974"; 868*724ba675SRob Herring reg = <0x0e>; 869*724ba675SRob Herring 870*724ba675SRob Herring interrupt-parent = <&gpio>; 871*724ba675SRob Herring interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; 872*724ba675SRob Herring 873*724ba675SRob Herring avdd-supply = <&vdd_3v3_sys>; 874*724ba675SRob Herring dvdd-supply = <&vdd_1v8>; 875*724ba675SRob Herring 876*724ba675SRob Herring mount-matrix = "0", "-1", "0", 877*724ba675SRob Herring "-1", "0", "0", 878*724ba675SRob Herring "0", "0", "-1"; 879*724ba675SRob Herring }; 880*724ba675SRob Herring 881*724ba675SRob Herring light-sensor@1c { 882*724ba675SRob Herring compatible = "dynaimage,al3010"; 883*724ba675SRob Herring reg = <0x1c>; 884*724ba675SRob Herring 885*724ba675SRob Herring interrupt-parent = <&gpio>; 886*724ba675SRob Herring interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 887*724ba675SRob Herring 888*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 889*724ba675SRob Herring }; 890*724ba675SRob Herring 891*724ba675SRob Herring accelerometer@68 { 892*724ba675SRob Herring compatible = "invensense,mpu6050"; 893*724ba675SRob Herring reg = <0x68>; 894*724ba675SRob Herring 895*724ba675SRob Herring interrupt-parent = <&gpio>; 896*724ba675SRob Herring interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 897*724ba675SRob Herring 898*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 899*724ba675SRob Herring vddio-supply = <&vdd_1v8>; 900*724ba675SRob Herring 901*724ba675SRob Herring mount-matrix = "0", "-1", "0", 902*724ba675SRob Herring "-1", "0", "0", 903*724ba675SRob Herring "0", "0", "-1"; 904*724ba675SRob Herring }; 905*724ba675SRob Herring }; 906*724ba675SRob Herring 907*724ba675SRob Herring i2c@7000d000 { 908*724ba675SRob Herring clock-frequency = <100000>; 909*724ba675SRob Herring status = "okay"; 910*724ba675SRob Herring 911*724ba675SRob Herring rt5640: audio-codec@1c { 912*724ba675SRob Herring compatible = "realtek,rt5640"; 913*724ba675SRob Herring reg = <0x1c>; 914*724ba675SRob Herring 915*724ba675SRob Herring realtek,dmic1-data-pin = <1>; 916*724ba675SRob Herring }; 917*724ba675SRob Herring 918*724ba675SRob Herring nct72: temperature-sensor@4c { 919*724ba675SRob Herring compatible = "onnn,nct1008"; 920*724ba675SRob Herring reg = <0x4c>; 921*724ba675SRob Herring vcc-supply = <&vdd_3v3_sys>; 922*724ba675SRob Herring 923*724ba675SRob Herring interrupt-parent = <&gpio>; 924*724ba675SRob Herring interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>; 925*724ba675SRob Herring 926*724ba675SRob Herring #thermal-sensor-cells = <1>; 927*724ba675SRob Herring }; 928*724ba675SRob Herring 929*724ba675SRob Herring fuel-gauge@55 { 930*724ba675SRob Herring compatible = "ti,bq27541"; 931*724ba675SRob Herring reg = <0x55>; 932*724ba675SRob Herring power-supplies = <&power_supply>; 933*724ba675SRob Herring }; 934*724ba675SRob Herring 935*724ba675SRob Herring power_supply: charger@6a { 936*724ba675SRob Herring compatible = "summit,smb347"; 937*724ba675SRob Herring reg = <0x6a>; 938*724ba675SRob Herring 939*724ba675SRob Herring interrupt-parent = <&gpio>; 940*724ba675SRob Herring interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; 941*724ba675SRob Herring 942*724ba675SRob Herring summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; 943*724ba675SRob Herring summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; 944*724ba675SRob Herring summit,enable-usb-charging; 945*724ba675SRob Herring 946*724ba675SRob Herring monitored-battery = <&battery_cell>; 947*724ba675SRob Herring 948*724ba675SRob Herring usb_vbus: usb-vbus { 949*724ba675SRob Herring regulator-name = "usb_vbus"; 950*724ba675SRob Herring regulator-min-microvolt = <5000000>; 951*724ba675SRob Herring regulator-max-microvolt = <5000000>; 952*724ba675SRob Herring regulator-min-microamp = <750000>; 953*724ba675SRob Herring regulator-max-microamp = <750000>; 954*724ba675SRob Herring 955*724ba675SRob Herring /* 956*724ba675SRob Herring * SMB347 INOK input pin is connected to PMIC's 957*724ba675SRob Herring * ACOK output, which is fixed to ACTIVE_LOW as 958*724ba675SRob Herring * long as battery voltage is in a good range. 959*724ba675SRob Herring * 960*724ba675SRob Herring * Active INOK disables SMB347 output, so polarity 961*724ba675SRob Herring * needs to be toggled when we want to get the 962*724ba675SRob Herring * output. 963*724ba675SRob Herring */ 964*724ba675SRob Herring summit,needs-inok-toggle; 965*724ba675SRob Herring }; 966*724ba675SRob Herring }; 967*724ba675SRob Herring }; 968*724ba675SRob Herring 969*724ba675SRob Herring pmc@7000e400 { 970*724ba675SRob Herring status = "okay"; 971*724ba675SRob Herring nvidia,invert-interrupt; 972*724ba675SRob Herring nvidia,suspend-mode = <1>; 973*724ba675SRob Herring nvidia,cpu-pwr-good-time = <2000>; 974*724ba675SRob Herring nvidia,cpu-pwr-off-time = <200>; 975*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 976*724ba675SRob Herring nvidia,core-pwr-off-time = <0>; 977*724ba675SRob Herring nvidia,core-power-req-active-high; 978*724ba675SRob Herring nvidia,sys-clock-req-active-high; 979*724ba675SRob Herring core-supply = <&vdd_core>; 980*724ba675SRob Herring }; 981*724ba675SRob Herring 982*724ba675SRob Herring ahub@70080000 { 983*724ba675SRob Herring i2s@70080400 { 984*724ba675SRob Herring status = "okay"; 985*724ba675SRob Herring }; 986*724ba675SRob Herring }; 987*724ba675SRob Herring 988*724ba675SRob Herring sdmmc3: mmc@78000400 { 989*724ba675SRob Herring status = "okay"; 990*724ba675SRob Herring 991*724ba675SRob Herring #address-cells = <1>; 992*724ba675SRob Herring #size-cells = <0>; 993*724ba675SRob Herring 994*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 995*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 996*724ba675SRob Herring assigned-clock-rates = <50000000>; 997*724ba675SRob Herring 998*724ba675SRob Herring max-frequency = <50000000>; 999*724ba675SRob Herring keep-power-in-suspend; 1000*724ba675SRob Herring bus-width = <4>; 1001*724ba675SRob Herring non-removable; 1002*724ba675SRob Herring 1003*724ba675SRob Herring mmc-pwrseq = <&brcm_wifi_pwrseq>; 1004*724ba675SRob Herring vmmc-supply = <&vdd_3v3_sys>; 1005*724ba675SRob Herring vqmmc-supply = <&vdd_1v8>; 1006*724ba675SRob Herring 1007*724ba675SRob Herring /* Azurewave AW-NH665 BCM4330 */ 1008*724ba675SRob Herring wifi@1 { 1009*724ba675SRob Herring reg = <1>; 1010*724ba675SRob Herring compatible = "brcm,bcm4329-fmac"; 1011*724ba675SRob Herring interrupt-parent = <&gpio>; 1012*724ba675SRob Herring interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 1013*724ba675SRob Herring interrupt-names = "host-wake"; 1014*724ba675SRob Herring }; 1015*724ba675SRob Herring }; 1016*724ba675SRob Herring 1017*724ba675SRob Herring sdmmc4: mmc@78000600 { 1018*724ba675SRob Herring status = "okay"; 1019*724ba675SRob Herring bus-width = <8>; 1020*724ba675SRob Herring vmmc-supply = <&vcore_emmc>; 1021*724ba675SRob Herring vqmmc-supply = <&vdd_1v8>; 1022*724ba675SRob Herring non-removable; 1023*724ba675SRob Herring }; 1024*724ba675SRob Herring 1025*724ba675SRob Herring usb@7d000000 { 1026*724ba675SRob Herring compatible = "nvidia,tegra30-udc"; 1027*724ba675SRob Herring status = "okay"; 1028*724ba675SRob Herring dr_mode = "otg"; 1029*724ba675SRob Herring vbus-supply = <&usb_vbus>; 1030*724ba675SRob Herring }; 1031*724ba675SRob Herring 1032*724ba675SRob Herring usb-phy@7d000000 { 1033*724ba675SRob Herring status = "okay"; 1034*724ba675SRob Herring dr_mode = "otg"; 1035*724ba675SRob Herring nvidia,hssync-start-delay = <0>; 1036*724ba675SRob Herring nvidia,xcvr-lsfslew = <2>; 1037*724ba675SRob Herring nvidia,xcvr-lsrslew = <2>; 1038*724ba675SRob Herring }; 1039*724ba675SRob Herring 1040*724ba675SRob Herring backlight: backlight { 1041*724ba675SRob Herring compatible = "pwm-backlight"; 1042*724ba675SRob Herring 1043*724ba675SRob Herring power-supply = <&vdd_5v0_sys>; 1044*724ba675SRob Herring pwms = <&pwm 0 50000>; 1045*724ba675SRob Herring 1046*724ba675SRob Herring brightness-levels = <1 255>; 1047*724ba675SRob Herring num-interpolated-steps = <254>; 1048*724ba675SRob Herring default-brightness-level = <15>; 1049*724ba675SRob Herring }; 1050*724ba675SRob Herring 1051*724ba675SRob Herring battery_cell: battery-cell { 1052*724ba675SRob Herring compatible = "simple-battery"; 1053*724ba675SRob Herring constant-charge-current-max-microamp = <1800000>; 1054*724ba675SRob Herring operating-range-celsius = <0 45>; 1055*724ba675SRob Herring }; 1056*724ba675SRob Herring 1057*724ba675SRob Herring /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1058*724ba675SRob Herring clk32k_in: clock-32k { 1059*724ba675SRob Herring compatible = "fixed-clock"; 1060*724ba675SRob Herring #clock-cells = <0>; 1061*724ba675SRob Herring clock-frequency = <32768>; 1062*724ba675SRob Herring clock-output-names = "pmic-oscillator"; 1063*724ba675SRob Herring }; 1064*724ba675SRob Herring 1065*724ba675SRob Herring cpus { 1066*724ba675SRob Herring cpu0: cpu@0 { 1067*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1068*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1069*724ba675SRob Herring #cooling-cells = <2>; 1070*724ba675SRob Herring }; 1071*724ba675SRob Herring 1072*724ba675SRob Herring cpu1: cpu@1 { 1073*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1074*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1075*724ba675SRob Herring #cooling-cells = <2>; 1076*724ba675SRob Herring }; 1077*724ba675SRob Herring 1078*724ba675SRob Herring cpu2: cpu@2 { 1079*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1080*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1081*724ba675SRob Herring #cooling-cells = <2>; 1082*724ba675SRob Herring }; 1083*724ba675SRob Herring 1084*724ba675SRob Herring cpu3: cpu@3 { 1085*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1086*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1087*724ba675SRob Herring #cooling-cells = <2>; 1088*724ba675SRob Herring }; 1089*724ba675SRob Herring }; 1090*724ba675SRob Herring 1091*724ba675SRob Herring display-panel { 1092*724ba675SRob Herring /* 1093*724ba675SRob Herring * Nexus 7 supports two compatible panel models: 1094*724ba675SRob Herring * 1095*724ba675SRob Herring * 1. hydis,hv070wx2-1e0 1096*724ba675SRob Herring * 2. chunghwa,claa070wp03xg 1097*724ba675SRob Herring * 1098*724ba675SRob Herring * We want to use timing which is optimized for Nexus 7, 1099*724ba675SRob Herring * hence we need to customize the timing. 1100*724ba675SRob Herring */ 1101*724ba675SRob Herring compatible = "panel-lvds"; 1102*724ba675SRob Herring 1103*724ba675SRob Herring width-mm = <94>; 1104*724ba675SRob Herring height-mm = <150>; 1105*724ba675SRob Herring rotation = <180>; 1106*724ba675SRob Herring 1107*724ba675SRob Herring data-mapping = "jeida-24"; 1108*724ba675SRob Herring 1109*724ba675SRob Herring /* DDC unconnected on Nexus 7 */ 1110*724ba675SRob Herring /delete-property/ ddc-i2c-bus; 1111*724ba675SRob Herring }; 1112*724ba675SRob Herring 1113*724ba675SRob Herring gpio-keys { 1114*724ba675SRob Herring compatible = "gpio-keys"; 1115*724ba675SRob Herring 1116*724ba675SRob Herring key-power { 1117*724ba675SRob Herring label = "Power"; 1118*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1119*724ba675SRob Herring linux,code = <KEY_POWER>; 1120*724ba675SRob Herring debounce-interval = <10>; 1121*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1122*724ba675SRob Herring wakeup-source; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring 1125*724ba675SRob Herring key-volume-down { 1126*724ba675SRob Herring label = "Volume Down"; 1127*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; 1128*724ba675SRob Herring linux,code = <KEY_VOLUMEDOWN>; 1129*724ba675SRob Herring debounce-interval = <10>; 1130*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1131*724ba675SRob Herring wakeup-source; 1132*724ba675SRob Herring }; 1133*724ba675SRob Herring 1134*724ba675SRob Herring key-volume-up { 1135*724ba675SRob Herring label = "Volume Up"; 1136*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 1137*724ba675SRob Herring linux,code = <KEY_VOLUMEUP>; 1138*724ba675SRob Herring debounce-interval = <10>; 1139*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1140*724ba675SRob Herring wakeup-source; 1141*724ba675SRob Herring }; 1142*724ba675SRob Herring 1143*724ba675SRob Herring switch-hall-sensor { 1144*724ba675SRob Herring label = "Lid"; 1145*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; 1146*724ba675SRob Herring linux,input-type = <EV_SW>; 1147*724ba675SRob Herring linux,code = <SW_LID>; 1148*724ba675SRob Herring debounce-interval = <500>; 1149*724ba675SRob Herring wakeup-event-action = <EV_ACT_DEASSERTED>; 1150*724ba675SRob Herring wakeup-source; 1151*724ba675SRob Herring }; 1152*724ba675SRob Herring }; 1153*724ba675SRob Herring 1154*724ba675SRob Herring brcm_wifi_pwrseq: pwrseq-wifi { 1155*724ba675SRob Herring compatible = "mmc-pwrseq-simple"; 1156*724ba675SRob Herring 1157*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1158*724ba675SRob Herring clock-names = "ext_clock"; 1159*724ba675SRob Herring 1160*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; 1161*724ba675SRob Herring post-power-on-delay-ms = <300>; 1162*724ba675SRob Herring power-off-delay-us = <300>; 1163*724ba675SRob Herring }; 1164*724ba675SRob Herring 1165*724ba675SRob Herring vdd_5v0_sys: regulator-5v0 { 1166*724ba675SRob Herring compatible = "regulator-fixed"; 1167*724ba675SRob Herring regulator-name = "vdd_5v0"; 1168*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1169*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1170*724ba675SRob Herring regulator-always-on; 1171*724ba675SRob Herring regulator-boot-on; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring 1174*724ba675SRob Herring vdd_3v3_sys: regulator-3v3 { 1175*724ba675SRob Herring compatible = "regulator-fixed"; 1176*724ba675SRob Herring regulator-name = "vdd_3v3"; 1177*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1178*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1179*724ba675SRob Herring regulator-always-on; 1180*724ba675SRob Herring regulator-boot-on; 1181*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1182*724ba675SRob Herring }; 1183*724ba675SRob Herring 1184*724ba675SRob Herring vdd_pnl: regulator-panel { 1185*724ba675SRob Herring compatible = "regulator-fixed"; 1186*724ba675SRob Herring regulator-name = "vdd_panel"; 1187*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1188*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1189*724ba675SRob Herring regulator-enable-ramp-delay = <300000>; 1190*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1191*724ba675SRob Herring enable-active-high; 1192*724ba675SRob Herring vin-supply = <&vdd_3v3_sys>; 1193*724ba675SRob Herring }; 1194*724ba675SRob Herring 1195*724ba675SRob Herring vcc_3v3_ts: regulator-ts { 1196*724ba675SRob Herring compatible = "regulator-fixed"; 1197*724ba675SRob Herring regulator-name = "ldo_s-1167_3v3"; 1198*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1199*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1200*724ba675SRob Herring regulator-always-on; 1201*724ba675SRob Herring regulator-boot-on; 1202*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1203*724ba675SRob Herring }; 1204*724ba675SRob Herring 1205*724ba675SRob Herring sound { 1206*724ba675SRob Herring compatible = "nvidia,tegra-audio-rt5640-grouper", 1207*724ba675SRob Herring "nvidia,tegra-audio-rt5640"; 1208*724ba675SRob Herring nvidia,model = "ASUS Google Nexus 7 ALC5642"; 1209*724ba675SRob Herring 1210*724ba675SRob Herring nvidia,audio-routing = 1211*724ba675SRob Herring "Headphones", "HPOR", 1212*724ba675SRob Herring "Headphones", "HPOL", 1213*724ba675SRob Herring "Speakers", "SPORP", 1214*724ba675SRob Herring "Speakers", "SPORN", 1215*724ba675SRob Herring "Speakers", "SPOLP", 1216*724ba675SRob Herring "Speakers", "SPOLN", 1217*724ba675SRob Herring "DMIC1", "Mic Jack"; 1218*724ba675SRob Herring 1219*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 1220*724ba675SRob Herring nvidia,audio-codec = <&rt5640>; 1221*724ba675SRob Herring 1222*724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1223*724ba675SRob Herring 1224*724ba675SRob Herring clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1225*724ba675SRob Herring <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1226*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1227*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 1228*724ba675SRob Herring 1229*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1230*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1231*724ba675SRob Herring 1232*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1233*724ba675SRob Herring <&tegra_car TEGRA30_CLK_EXTERN1>; 1234*724ba675SRob Herring }; 1235*724ba675SRob Herring 1236*724ba675SRob Herring thermal-zones { 1237*724ba675SRob Herring /* 1238*724ba675SRob Herring * NCT72 has two sensors: 1239*724ba675SRob Herring * 1240*724ba675SRob Herring * 0: internal that monitors ambient/skin temperature 1241*724ba675SRob Herring * 1: external that is connected to the CPU's diode 1242*724ba675SRob Herring * 1243*724ba675SRob Herring * Ideally we should use userspace thermal governor, 1244*724ba675SRob Herring * but it's a much more complex solution. The "skin" 1245*724ba675SRob Herring * zone is a simpler solution which prevents Nexus 7 1246*724ba675SRob Herring * from getting too hot from a user's tactile perspective. 1247*724ba675SRob Herring * The CPU zone is intended to protect silicon from damage. 1248*724ba675SRob Herring */ 1249*724ba675SRob Herring 1250*724ba675SRob Herring skin-thermal { 1251*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 1252*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 1253*724ba675SRob Herring 1254*724ba675SRob Herring thermal-sensors = <&nct72 0>; 1255*724ba675SRob Herring 1256*724ba675SRob Herring trips { 1257*724ba675SRob Herring trip0: skin-alert { 1258*724ba675SRob Herring /* throttle at 57C until temperature drops to 56.8C */ 1259*724ba675SRob Herring temperature = <57000>; 1260*724ba675SRob Herring hysteresis = <200>; 1261*724ba675SRob Herring type = "passive"; 1262*724ba675SRob Herring }; 1263*724ba675SRob Herring 1264*724ba675SRob Herring trip1: skin-crit { 1265*724ba675SRob Herring /* shut down at 65C */ 1266*724ba675SRob Herring temperature = <65000>; 1267*724ba675SRob Herring hysteresis = <2000>; 1268*724ba675SRob Herring type = "critical"; 1269*724ba675SRob Herring }; 1270*724ba675SRob Herring }; 1271*724ba675SRob Herring 1272*724ba675SRob Herring cooling-maps { 1273*724ba675SRob Herring map0 { 1274*724ba675SRob Herring trip = <&trip0>; 1275*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1276*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1277*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1278*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1279*724ba675SRob Herring <&actmon THERMAL_NO_LIMIT 1280*724ba675SRob Herring THERMAL_NO_LIMIT>; 1281*724ba675SRob Herring }; 1282*724ba675SRob Herring }; 1283*724ba675SRob Herring }; 1284*724ba675SRob Herring 1285*724ba675SRob Herring cpu-thermal { 1286*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 1287*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 1288*724ba675SRob Herring 1289*724ba675SRob Herring thermal-sensors = <&nct72 1>; 1290*724ba675SRob Herring 1291*724ba675SRob Herring trips { 1292*724ba675SRob Herring trip2: cpu-alert { 1293*724ba675SRob Herring /* throttle at 85C until temperature drops to 84.8C */ 1294*724ba675SRob Herring temperature = <85000>; 1295*724ba675SRob Herring hysteresis = <200>; 1296*724ba675SRob Herring type = "passive"; 1297*724ba675SRob Herring }; 1298*724ba675SRob Herring 1299*724ba675SRob Herring trip3: cpu-crit { 1300*724ba675SRob Herring /* shut down at 90C */ 1301*724ba675SRob Herring temperature = <90000>; 1302*724ba675SRob Herring hysteresis = <2000>; 1303*724ba675SRob Herring type = "critical"; 1304*724ba675SRob Herring }; 1305*724ba675SRob Herring }; 1306*724ba675SRob Herring 1307*724ba675SRob Herring cooling-maps { 1308*724ba675SRob Herring map1 { 1309*724ba675SRob Herring trip = <&trip2>; 1310*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1311*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1312*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1313*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1314*724ba675SRob Herring <&actmon THERMAL_NO_LIMIT 1315*724ba675SRob Herring THERMAL_NO_LIMIT>; 1316*724ba675SRob Herring }; 1317*724ba675SRob Herring }; 1318*724ba675SRob Herring }; 1319*724ba675SRob Herring }; 1320*724ba675SRob Herring}; 1321