1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring#include <dt-bindings/clock/tegra20-car.h> 3*724ba675SRob Herring#include <dt-bindings/gpio/tegra-gpio.h> 4*724ba675SRob Herring#include <dt-bindings/memory/tegra20-mc.h> 5*724ba675SRob Herring#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 7*724ba675SRob Herring#include <dt-bindings/soc/tegra-pmc.h> 8*724ba675SRob Herring 9*724ba675SRob Herring#include "tegra20-peripherals-opp.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring compatible = "nvidia,tegra20"; 13*724ba675SRob Herring interrupt-parent = <&lic>; 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <1>; 16*724ba675SRob Herring 17*724ba675SRob Herring memory@0 { 18*724ba675SRob Herring device_type = "memory"; 19*724ba675SRob Herring reg = <0 0>; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring sram@40000000 { 23*724ba675SRob Herring compatible = "mmio-sram"; 24*724ba675SRob Herring reg = <0x40000000 0x40000>; 25*724ba675SRob Herring #address-cells = <1>; 26*724ba675SRob Herring #size-cells = <1>; 27*724ba675SRob Herring ranges = <0 0x40000000 0x40000>; 28*724ba675SRob Herring 29*724ba675SRob Herring vde_pool: sram@400 { 30*724ba675SRob Herring reg = <0x400 0x3fc00>; 31*724ba675SRob Herring pool; 32*724ba675SRob Herring }; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring host1x@50000000 { 36*724ba675SRob Herring compatible = "nvidia,tegra20-host1x"; 37*724ba675SRob Herring reg = <0x50000000 0x00024000>; 38*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 39*724ba675SRob Herring <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 40*724ba675SRob Herring interrupt-names = "syncpt", "host1x"; 41*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 42*724ba675SRob Herring clock-names = "host1x"; 43*724ba675SRob Herring resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 44*724ba675SRob Herring reset-names = "host1x", "mc"; 45*724ba675SRob Herring power-domains = <&pd_core>; 46*724ba675SRob Herring operating-points-v2 = <&host1x_dvfs_opp_table>; 47*724ba675SRob Herring 48*724ba675SRob Herring #address-cells = <1>; 49*724ba675SRob Herring #size-cells = <1>; 50*724ba675SRob Herring 51*724ba675SRob Herring ranges = <0x54000000 0x54000000 0x04000000>; 52*724ba675SRob Herring 53*724ba675SRob Herring mpe@54040000 { 54*724ba675SRob Herring compatible = "nvidia,tegra20-mpe"; 55*724ba675SRob Herring reg = <0x54040000 0x00040000>; 56*724ba675SRob Herring interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 57*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_MPE>; 58*724ba675SRob Herring resets = <&tegra_car 60>; 59*724ba675SRob Herring reset-names = "mpe"; 60*724ba675SRob Herring power-domains = <&pd_mpe>; 61*724ba675SRob Herring operating-points-v2 = <&mpe_dvfs_opp_table>; 62*724ba675SRob Herring status = "disabled"; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring vi@54080000 { 66*724ba675SRob Herring compatible = "nvidia,tegra20-vi"; 67*724ba675SRob Herring reg = <0x54080000 0x00040000>; 68*724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 69*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_VI>; 70*724ba675SRob Herring resets = <&tegra_car 20>; 71*724ba675SRob Herring reset-names = "vi"; 72*724ba675SRob Herring power-domains = <&pd_venc>; 73*724ba675SRob Herring operating-points-v2 = <&vi_dvfs_opp_table>; 74*724ba675SRob Herring status = "disabled"; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring epp@540c0000 { 78*724ba675SRob Herring compatible = "nvidia,tegra20-epp"; 79*724ba675SRob Herring reg = <0x540c0000 0x00040000>; 80*724ba675SRob Herring interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 81*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_EPP>; 82*724ba675SRob Herring resets = <&tegra_car 19>; 83*724ba675SRob Herring reset-names = "epp"; 84*724ba675SRob Herring power-domains = <&pd_core>; 85*724ba675SRob Herring operating-points-v2 = <&epp_dvfs_opp_table>; 86*724ba675SRob Herring status = "disabled"; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring isp@54100000 { 90*724ba675SRob Herring compatible = "nvidia,tegra20-isp"; 91*724ba675SRob Herring reg = <0x54100000 0x00040000>; 92*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 93*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_ISP>; 94*724ba675SRob Herring resets = <&tegra_car 23>; 95*724ba675SRob Herring reset-names = "isp"; 96*724ba675SRob Herring power-domains = <&pd_venc>; 97*724ba675SRob Herring status = "disabled"; 98*724ba675SRob Herring }; 99*724ba675SRob Herring 100*724ba675SRob Herring gr2d@54140000 { 101*724ba675SRob Herring compatible = "nvidia,tegra20-gr2d"; 102*724ba675SRob Herring reg = <0x54140000 0x00040000>; 103*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 104*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_GR2D>; 105*724ba675SRob Herring resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 106*724ba675SRob Herring reset-names = "2d", "mc"; 107*724ba675SRob Herring power-domains = <&pd_core>; 108*724ba675SRob Herring operating-points-v2 = <&gr2d_dvfs_opp_table>; 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring gr3d@54180000 { 112*724ba675SRob Herring compatible = "nvidia,tegra20-gr3d"; 113*724ba675SRob Herring reg = <0x54180000 0x00040000>; 114*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_GR3D>; 115*724ba675SRob Herring resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 116*724ba675SRob Herring reset-names = "3d", "mc"; 117*724ba675SRob Herring power-domains = <&pd_3d>; 118*724ba675SRob Herring operating-points-v2 = <&gr3d_dvfs_opp_table>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring dc@54200000 { 122*724ba675SRob Herring compatible = "nvidia,tegra20-dc"; 123*724ba675SRob Herring reg = <0x54200000 0x00040000>; 124*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 125*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_DISP1>, 126*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P>; 127*724ba675SRob Herring clock-names = "dc", "parent"; 128*724ba675SRob Herring resets = <&tegra_car 27>; 129*724ba675SRob Herring reset-names = "dc"; 130*724ba675SRob Herring power-domains = <&pd_core>; 131*724ba675SRob Herring operating-points-v2 = <&disp1_dvfs_opp_table>; 132*724ba675SRob Herring 133*724ba675SRob Herring nvidia,head = <0>; 134*724ba675SRob Herring 135*724ba675SRob Herring interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 136*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY0B &emc>, 137*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY1B &emc>, 138*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY0C &emc>, 139*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAYHC &emc>; 140*724ba675SRob Herring interconnect-names = "wina", 141*724ba675SRob Herring "winb", 142*724ba675SRob Herring "winb-vfilter", 143*724ba675SRob Herring "winc", 144*724ba675SRob Herring "cursor"; 145*724ba675SRob Herring 146*724ba675SRob Herring rgb { 147*724ba675SRob Herring status = "disabled"; 148*724ba675SRob Herring }; 149*724ba675SRob Herring }; 150*724ba675SRob Herring 151*724ba675SRob Herring dc@54240000 { 152*724ba675SRob Herring compatible = "nvidia,tegra20-dc"; 153*724ba675SRob Herring reg = <0x54240000 0x00040000>; 154*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 155*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_DISP2>, 156*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P>; 157*724ba675SRob Herring clock-names = "dc", "parent"; 158*724ba675SRob Herring resets = <&tegra_car 26>; 159*724ba675SRob Herring reset-names = "dc"; 160*724ba675SRob Herring power-domains = <&pd_core>; 161*724ba675SRob Herring operating-points-v2 = <&disp2_dvfs_opp_table>; 162*724ba675SRob Herring 163*724ba675SRob Herring nvidia,head = <1>; 164*724ba675SRob Herring 165*724ba675SRob Herring interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 166*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY0BB &emc>, 167*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY1BB &emc>, 168*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAY0CB &emc>, 169*724ba675SRob Herring <&mc TEGRA20_MC_DISPLAYHCB &emc>; 170*724ba675SRob Herring interconnect-names = "wina", 171*724ba675SRob Herring "winb", 172*724ba675SRob Herring "winb-vfilter", 173*724ba675SRob Herring "winc", 174*724ba675SRob Herring "cursor"; 175*724ba675SRob Herring 176*724ba675SRob Herring rgb { 177*724ba675SRob Herring status = "disabled"; 178*724ba675SRob Herring }; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring tegra_hdmi: hdmi@54280000 { 182*724ba675SRob Herring compatible = "nvidia,tegra20-hdmi"; 183*724ba675SRob Herring reg = <0x54280000 0x00040000>; 184*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 185*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_HDMI>, 186*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 187*724ba675SRob Herring clock-names = "hdmi", "parent"; 188*724ba675SRob Herring resets = <&tegra_car 51>; 189*724ba675SRob Herring reset-names = "hdmi"; 190*724ba675SRob Herring power-domains = <&pd_core>; 191*724ba675SRob Herring operating-points-v2 = <&hdmi_dvfs_opp_table>; 192*724ba675SRob Herring #sound-dai-cells = <0>; 193*724ba675SRob Herring status = "disabled"; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring tvo@542c0000 { 197*724ba675SRob Herring compatible = "nvidia,tegra20-tvo"; 198*724ba675SRob Herring reg = <0x542c0000 0x00040000>; 199*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 200*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_TVO>; 201*724ba675SRob Herring power-domains = <&pd_core>; 202*724ba675SRob Herring operating-points-v2 = <&tvo_dvfs_opp_table>; 203*724ba675SRob Herring status = "disabled"; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring dsi@54300000 { 207*724ba675SRob Herring compatible = "nvidia,tegra20-dsi"; 208*724ba675SRob Herring reg = <0x54300000 0x00040000>; 209*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_DSI>, 210*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 211*724ba675SRob Herring clock-names = "dsi", "parent"; 212*724ba675SRob Herring resets = <&tegra_car 48>; 213*724ba675SRob Herring reset-names = "dsi"; 214*724ba675SRob Herring power-domains = <&pd_core>; 215*724ba675SRob Herring operating-points-v2 = <&dsi_dvfs_opp_table>; 216*724ba675SRob Herring status = "disabled"; 217*724ba675SRob Herring }; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring timer@50040600 { 221*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 222*724ba675SRob Herring interrupt-parent = <&intc>; 223*724ba675SRob Herring reg = <0x50040600 0x20>; 224*724ba675SRob Herring interrupts = <GIC_PPI 13 225*724ba675SRob Herring (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 226*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_TWD>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring 229*724ba675SRob Herring intc: interrupt-controller@50041000 { 230*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 231*724ba675SRob Herring reg = <0x50041000 0x1000>, 232*724ba675SRob Herring <0x50040100 0x0100>; 233*724ba675SRob Herring interrupt-controller; 234*724ba675SRob Herring #interrupt-cells = <3>; 235*724ba675SRob Herring interrupt-parent = <&intc>; 236*724ba675SRob Herring }; 237*724ba675SRob Herring 238*724ba675SRob Herring cache-controller@50043000 { 239*724ba675SRob Herring compatible = "arm,pl310-cache"; 240*724ba675SRob Herring reg = <0x50043000 0x1000>; 241*724ba675SRob Herring arm,data-latency = <5 5 2>; 242*724ba675SRob Herring arm,tag-latency = <4 4 2>; 243*724ba675SRob Herring cache-unified; 244*724ba675SRob Herring cache-level = <2>; 245*724ba675SRob Herring }; 246*724ba675SRob Herring 247*724ba675SRob Herring lic: interrupt-controller@60004000 { 248*724ba675SRob Herring compatible = "nvidia,tegra20-ictlr"; 249*724ba675SRob Herring reg = <0x60004000 0x100>, 250*724ba675SRob Herring <0x60004100 0x50>, 251*724ba675SRob Herring <0x60004200 0x50>, 252*724ba675SRob Herring <0x60004300 0x50>; 253*724ba675SRob Herring interrupt-controller; 254*724ba675SRob Herring #interrupt-cells = <3>; 255*724ba675SRob Herring interrupt-parent = <&intc>; 256*724ba675SRob Herring }; 257*724ba675SRob Herring 258*724ba675SRob Herring timer@60005000 { 259*724ba675SRob Herring compatible = "nvidia,tegra20-timer"; 260*724ba675SRob Herring reg = <0x60005000 0x60>; 261*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 262*724ba675SRob Herring <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 263*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 264*724ba675SRob Herring <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 265*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_TIMER>; 266*724ba675SRob Herring }; 267*724ba675SRob Herring 268*724ba675SRob Herring tegra_car: clock@60006000 { 269*724ba675SRob Herring compatible = "nvidia,tegra20-car"; 270*724ba675SRob Herring reg = <0x60006000 0x1000>; 271*724ba675SRob Herring #clock-cells = <1>; 272*724ba675SRob Herring #reset-cells = <1>; 273*724ba675SRob Herring 274*724ba675SRob Herring sclk { 275*724ba675SRob Herring compatible = "nvidia,tegra20-sclk"; 276*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SCLK>; 277*724ba675SRob Herring power-domains = <&pd_core>; 278*724ba675SRob Herring operating-points-v2 = <&sclk_dvfs_opp_table>; 279*724ba675SRob Herring }; 280*724ba675SRob Herring }; 281*724ba675SRob Herring 282*724ba675SRob Herring flow-controller@60007000 { 283*724ba675SRob Herring compatible = "nvidia,tegra20-flowctrl"; 284*724ba675SRob Herring reg = <0x60007000 0x1000>; 285*724ba675SRob Herring }; 286*724ba675SRob Herring 287*724ba675SRob Herring apbdma: dma@6000a000 { 288*724ba675SRob Herring compatible = "nvidia,tegra20-apbdma"; 289*724ba675SRob Herring reg = <0x6000a000 0x1200>; 290*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 291*724ba675SRob Herring <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 292*724ba675SRob Herring <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 293*724ba675SRob Herring <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 294*724ba675SRob Herring <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 295*724ba675SRob Herring <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 296*724ba675SRob Herring <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 297*724ba675SRob Herring <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 298*724ba675SRob Herring <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 299*724ba675SRob Herring <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 300*724ba675SRob Herring <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 301*724ba675SRob Herring <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 302*724ba675SRob Herring <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 303*724ba675SRob Herring <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 304*724ba675SRob Herring <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 305*724ba675SRob Herring <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 306*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 307*724ba675SRob Herring resets = <&tegra_car 34>; 308*724ba675SRob Herring reset-names = "dma"; 309*724ba675SRob Herring #dma-cells = <1>; 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring ahb@6000c000 { 313*724ba675SRob Herring compatible = "nvidia,tegra20-ahb"; 314*724ba675SRob Herring reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 315*724ba675SRob Herring }; 316*724ba675SRob Herring 317*724ba675SRob Herring gpio: gpio@6000d000 { 318*724ba675SRob Herring compatible = "nvidia,tegra20-gpio"; 319*724ba675SRob Herring reg = <0x6000d000 0x1000>; 320*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 321*724ba675SRob Herring <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 322*724ba675SRob Herring <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 323*724ba675SRob Herring <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 324*724ba675SRob Herring <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 325*724ba675SRob Herring <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 326*724ba675SRob Herring <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 327*724ba675SRob Herring #gpio-cells = <2>; 328*724ba675SRob Herring gpio-controller; 329*724ba675SRob Herring #interrupt-cells = <2>; 330*724ba675SRob Herring interrupt-controller; 331*724ba675SRob Herring gpio-ranges = <&pinmux 0 0 224>; 332*724ba675SRob Herring }; 333*724ba675SRob Herring 334*724ba675SRob Herring vde@6001a000 { 335*724ba675SRob Herring compatible = "nvidia,tegra20-vde"; 336*724ba675SRob Herring reg = <0x6001a000 0x1000>, /* Syntax Engine */ 337*724ba675SRob Herring <0x6001b000 0x1000>, /* Video Bitstream Engine */ 338*724ba675SRob Herring <0x6001c000 0x100>, /* Macroblock Engine */ 339*724ba675SRob Herring <0x6001c200 0x100>, /* Post-processing Engine */ 340*724ba675SRob Herring <0x6001c400 0x100>, /* Motion Compensation Engine */ 341*724ba675SRob Herring <0x6001c600 0x100>, /* Transform Engine */ 342*724ba675SRob Herring <0x6001c800 0x100>, /* Pixel prediction block */ 343*724ba675SRob Herring <0x6001ca00 0x100>, /* Video DMA */ 344*724ba675SRob Herring <0x6001d800 0x300>; /* Video frame controls */ 345*724ba675SRob Herring reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 346*724ba675SRob Herring "tfe", "ppb", "vdma", "frameid"; 347*724ba675SRob Herring iram = <&vde_pool>; /* IRAM region */ 348*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 349*724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 350*724ba675SRob Herring <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 351*724ba675SRob Herring interrupt-names = "sync-token", "bsev", "sxe"; 352*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_VDE>; 353*724ba675SRob Herring reset-names = "vde", "mc"; 354*724ba675SRob Herring resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 355*724ba675SRob Herring power-domains = <&pd_vde>; 356*724ba675SRob Herring operating-points-v2 = <&vde_dvfs_opp_table>; 357*724ba675SRob Herring }; 358*724ba675SRob Herring 359*724ba675SRob Herring pinmux: pinmux@70000014 { 360*724ba675SRob Herring compatible = "nvidia,tegra20-pinmux"; 361*724ba675SRob Herring reg = <0x70000014 0x10>, /* Tri-state registers */ 362*724ba675SRob Herring <0x70000080 0x20>, /* Mux registers */ 363*724ba675SRob Herring <0x700000a0 0x14>, /* Pull-up/down registers */ 364*724ba675SRob Herring <0x70000868 0xa8>; /* Pad control registers */ 365*724ba675SRob Herring }; 366*724ba675SRob Herring 367*724ba675SRob Herring apbmisc@70000800 { 368*724ba675SRob Herring compatible = "nvidia,tegra20-apbmisc"; 369*724ba675SRob Herring reg = <0x70000800 0x64>, /* Chip revision */ 370*724ba675SRob Herring <0x70000008 0x04>; /* Strapping options */ 371*724ba675SRob Herring }; 372*724ba675SRob Herring 373*724ba675SRob Herring das@70000c00 { 374*724ba675SRob Herring compatible = "nvidia,tegra20-das"; 375*724ba675SRob Herring reg = <0x70000c00 0x80>; 376*724ba675SRob Herring }; 377*724ba675SRob Herring 378*724ba675SRob Herring tegra_ac97: ac97@70002000 { 379*724ba675SRob Herring compatible = "nvidia,tegra20-ac97"; 380*724ba675SRob Herring reg = <0x70002000 0x200>; 381*724ba675SRob Herring interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 382*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_AC97>; 383*724ba675SRob Herring resets = <&tegra_car 3>; 384*724ba675SRob Herring reset-names = "ac97"; 385*724ba675SRob Herring dmas = <&apbdma 12>, <&apbdma 12>; 386*724ba675SRob Herring dma-names = "rx", "tx"; 387*724ba675SRob Herring status = "disabled"; 388*724ba675SRob Herring }; 389*724ba675SRob Herring 390*724ba675SRob Herring tegra_spdif: spdif@70002400 { 391*724ba675SRob Herring compatible = "nvidia,tegra20-spdif"; 392*724ba675SRob Herring reg = <0x70002400 0x200>; 393*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 394*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, 395*724ba675SRob Herring <&tegra_car TEGRA20_CLK_SPDIF_IN>; 396*724ba675SRob Herring clock-names = "out", "in"; 397*724ba675SRob Herring resets = <&tegra_car 10>; 398*724ba675SRob Herring dmas = <&apbdma 3>, <&apbdma 3>; 399*724ba675SRob Herring dma-names = "rx", "tx"; 400*724ba675SRob Herring #sound-dai-cells = <0>; 401*724ba675SRob Herring status = "disabled"; 402*724ba675SRob Herring 403*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; 404*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring tegra_i2s1: i2s@70002800 { 408*724ba675SRob Herring compatible = "nvidia,tegra20-i2s"; 409*724ba675SRob Herring reg = <0x70002800 0x200>; 410*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 411*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_I2S1>; 412*724ba675SRob Herring resets = <&tegra_car 11>; 413*724ba675SRob Herring reset-names = "i2s"; 414*724ba675SRob Herring dmas = <&apbdma 2>, <&apbdma 2>; 415*724ba675SRob Herring dma-names = "rx", "tx"; 416*724ba675SRob Herring status = "disabled"; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring tegra_i2s2: i2s@70002a00 { 420*724ba675SRob Herring compatible = "nvidia,tegra20-i2s"; 421*724ba675SRob Herring reg = <0x70002a00 0x200>; 422*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 423*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_I2S2>; 424*724ba675SRob Herring resets = <&tegra_car 18>; 425*724ba675SRob Herring reset-names = "i2s"; 426*724ba675SRob Herring dmas = <&apbdma 1>, <&apbdma 1>; 427*724ba675SRob Herring dma-names = "rx", "tx"; 428*724ba675SRob Herring status = "disabled"; 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring /* 432*724ba675SRob Herring * There are two serial driver i.e. 8250 based simple serial 433*724ba675SRob Herring * driver and APB DMA based serial driver for higher baudrate 434*724ba675SRob Herring * and performace. To enable the 8250 based driver, the compatible 435*724ba675SRob Herring * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 436*724ba675SRob Herring * driver, the compatible is "nvidia,tegra20-hsuart". 437*724ba675SRob Herring */ 438*724ba675SRob Herring uarta: serial@70006000 { 439*724ba675SRob Herring compatible = "nvidia,tegra20-uart"; 440*724ba675SRob Herring reg = <0x70006000 0x40>; 441*724ba675SRob Herring reg-shift = <2>; 442*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 443*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_UARTA>; 444*724ba675SRob Herring resets = <&tegra_car 6>; 445*724ba675SRob Herring reset-names = "serial"; 446*724ba675SRob Herring dmas = <&apbdma 8>, <&apbdma 8>; 447*724ba675SRob Herring dma-names = "rx", "tx"; 448*724ba675SRob Herring status = "disabled"; 449*724ba675SRob Herring }; 450*724ba675SRob Herring 451*724ba675SRob Herring uartb: serial@70006040 { 452*724ba675SRob Herring compatible = "nvidia,tegra20-uart"; 453*724ba675SRob Herring reg = <0x70006040 0x40>; 454*724ba675SRob Herring reg-shift = <2>; 455*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 456*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_UARTB>; 457*724ba675SRob Herring resets = <&tegra_car 7>; 458*724ba675SRob Herring reset-names = "serial"; 459*724ba675SRob Herring dmas = <&apbdma 9>, <&apbdma 9>; 460*724ba675SRob Herring dma-names = "rx", "tx"; 461*724ba675SRob Herring status = "disabled"; 462*724ba675SRob Herring }; 463*724ba675SRob Herring 464*724ba675SRob Herring uartc: serial@70006200 { 465*724ba675SRob Herring compatible = "nvidia,tegra20-uart"; 466*724ba675SRob Herring reg = <0x70006200 0x100>; 467*724ba675SRob Herring reg-shift = <2>; 468*724ba675SRob Herring interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 469*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_UARTC>; 470*724ba675SRob Herring resets = <&tegra_car 55>; 471*724ba675SRob Herring reset-names = "serial"; 472*724ba675SRob Herring dmas = <&apbdma 10>, <&apbdma 10>; 473*724ba675SRob Herring dma-names = "rx", "tx"; 474*724ba675SRob Herring status = "disabled"; 475*724ba675SRob Herring }; 476*724ba675SRob Herring 477*724ba675SRob Herring uartd: serial@70006300 { 478*724ba675SRob Herring compatible = "nvidia,tegra20-uart"; 479*724ba675SRob Herring reg = <0x70006300 0x100>; 480*724ba675SRob Herring reg-shift = <2>; 481*724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 482*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_UARTD>; 483*724ba675SRob Herring resets = <&tegra_car 65>; 484*724ba675SRob Herring reset-names = "serial"; 485*724ba675SRob Herring dmas = <&apbdma 19>, <&apbdma 19>; 486*724ba675SRob Herring dma-names = "rx", "tx"; 487*724ba675SRob Herring status = "disabled"; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring uarte: serial@70006400 { 491*724ba675SRob Herring compatible = "nvidia,tegra20-uart"; 492*724ba675SRob Herring reg = <0x70006400 0x100>; 493*724ba675SRob Herring reg-shift = <2>; 494*724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 495*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_UARTE>; 496*724ba675SRob Herring resets = <&tegra_car 66>; 497*724ba675SRob Herring reset-names = "serial"; 498*724ba675SRob Herring dmas = <&apbdma 20>, <&apbdma 20>; 499*724ba675SRob Herring dma-names = "rx", "tx"; 500*724ba675SRob Herring status = "disabled"; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring nand-controller@70008000 { 504*724ba675SRob Herring compatible = "nvidia,tegra20-nand"; 505*724ba675SRob Herring reg = <0x70008000 0x100>; 506*724ba675SRob Herring #address-cells = <1>; 507*724ba675SRob Herring #size-cells = <0>; 508*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 509*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 510*724ba675SRob Herring clock-names = "nand"; 511*724ba675SRob Herring resets = <&tegra_car 13>; 512*724ba675SRob Herring reset-names = "nand"; 513*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 514*724ba675SRob Herring assigned-clock-rates = <150000000>; 515*724ba675SRob Herring power-domains = <&pd_core>; 516*724ba675SRob Herring operating-points-v2 = <&ndflash_dvfs_opp_table>; 517*724ba675SRob Herring status = "disabled"; 518*724ba675SRob Herring }; 519*724ba675SRob Herring 520*724ba675SRob Herring gmi@70009000 { 521*724ba675SRob Herring compatible = "nvidia,tegra20-gmi"; 522*724ba675SRob Herring reg = <0x70009000 0x1000>; 523*724ba675SRob Herring #address-cells = <2>; 524*724ba675SRob Herring #size-cells = <1>; 525*724ba675SRob Herring ranges = <0 0 0xd0000000 0xfffffff>; 526*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_NOR>; 527*724ba675SRob Herring clock-names = "gmi"; 528*724ba675SRob Herring resets = <&tegra_car 42>; 529*724ba675SRob Herring reset-names = "gmi"; 530*724ba675SRob Herring power-domains = <&pd_core>; 531*724ba675SRob Herring operating-points-v2 = <&nor_dvfs_opp_table>; 532*724ba675SRob Herring status = "disabled"; 533*724ba675SRob Herring }; 534*724ba675SRob Herring 535*724ba675SRob Herring pwm: pwm@7000a000 { 536*724ba675SRob Herring compatible = "nvidia,tegra20-pwm"; 537*724ba675SRob Herring reg = <0x7000a000 0x100>; 538*724ba675SRob Herring #pwm-cells = <2>; 539*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_PWM>; 540*724ba675SRob Herring resets = <&tegra_car 17>; 541*724ba675SRob Herring reset-names = "pwm"; 542*724ba675SRob Herring status = "disabled"; 543*724ba675SRob Herring }; 544*724ba675SRob Herring 545*724ba675SRob Herring i2c@7000c000 { 546*724ba675SRob Herring compatible = "nvidia,tegra20-i2c"; 547*724ba675SRob Herring reg = <0x7000c000 0x100>; 548*724ba675SRob Herring interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 549*724ba675SRob Herring #address-cells = <1>; 550*724ba675SRob Herring #size-cells = <0>; 551*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_I2C1>, 552*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 553*724ba675SRob Herring clock-names = "div-clk", "fast-clk"; 554*724ba675SRob Herring resets = <&tegra_car 12>; 555*724ba675SRob Herring reset-names = "i2c"; 556*724ba675SRob Herring dmas = <&apbdma 21>, <&apbdma 21>; 557*724ba675SRob Herring dma-names = "rx", "tx"; 558*724ba675SRob Herring status = "disabled"; 559*724ba675SRob Herring }; 560*724ba675SRob Herring 561*724ba675SRob Herring spi@7000c380 { 562*724ba675SRob Herring compatible = "nvidia,tegra20-sflash"; 563*724ba675SRob Herring reg = <0x7000c380 0x80>; 564*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 565*724ba675SRob Herring #address-cells = <1>; 566*724ba675SRob Herring #size-cells = <0>; 567*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SPI>; 568*724ba675SRob Herring resets = <&tegra_car 43>; 569*724ba675SRob Herring reset-names = "spi"; 570*724ba675SRob Herring dmas = <&apbdma 11>, <&apbdma 11>; 571*724ba675SRob Herring dma-names = "rx", "tx"; 572*724ba675SRob Herring status = "disabled"; 573*724ba675SRob Herring }; 574*724ba675SRob Herring 575*724ba675SRob Herring i2c2: i2c@7000c400 { 576*724ba675SRob Herring compatible = "nvidia,tegra20-i2c"; 577*724ba675SRob Herring reg = <0x7000c400 0x100>; 578*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 579*724ba675SRob Herring #address-cells = <1>; 580*724ba675SRob Herring #size-cells = <0>; 581*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_I2C2>, 582*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 583*724ba675SRob Herring clock-names = "div-clk", "fast-clk"; 584*724ba675SRob Herring resets = <&tegra_car 54>; 585*724ba675SRob Herring reset-names = "i2c"; 586*724ba675SRob Herring dmas = <&apbdma 22>, <&apbdma 22>; 587*724ba675SRob Herring dma-names = "rx", "tx"; 588*724ba675SRob Herring status = "disabled"; 589*724ba675SRob Herring }; 590*724ba675SRob Herring 591*724ba675SRob Herring i2c@7000c500 { 592*724ba675SRob Herring compatible = "nvidia,tegra20-i2c"; 593*724ba675SRob Herring reg = <0x7000c500 0x100>; 594*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 595*724ba675SRob Herring #address-cells = <1>; 596*724ba675SRob Herring #size-cells = <0>; 597*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_I2C3>, 598*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 599*724ba675SRob Herring clock-names = "div-clk", "fast-clk"; 600*724ba675SRob Herring resets = <&tegra_car 67>; 601*724ba675SRob Herring reset-names = "i2c"; 602*724ba675SRob Herring dmas = <&apbdma 23>, <&apbdma 23>; 603*724ba675SRob Herring dma-names = "rx", "tx"; 604*724ba675SRob Herring status = "disabled"; 605*724ba675SRob Herring }; 606*724ba675SRob Herring 607*724ba675SRob Herring i2c@7000d000 { 608*724ba675SRob Herring compatible = "nvidia,tegra20-i2c-dvc"; 609*724ba675SRob Herring reg = <0x7000d000 0x200>; 610*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 611*724ba675SRob Herring #address-cells = <1>; 612*724ba675SRob Herring #size-cells = <0>; 613*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_DVC>, 614*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 615*724ba675SRob Herring clock-names = "div-clk", "fast-clk"; 616*724ba675SRob Herring resets = <&tegra_car 47>; 617*724ba675SRob Herring reset-names = "i2c"; 618*724ba675SRob Herring dmas = <&apbdma 24>, <&apbdma 24>; 619*724ba675SRob Herring dma-names = "rx", "tx"; 620*724ba675SRob Herring status = "disabled"; 621*724ba675SRob Herring }; 622*724ba675SRob Herring 623*724ba675SRob Herring spi@7000d400 { 624*724ba675SRob Herring compatible = "nvidia,tegra20-slink"; 625*724ba675SRob Herring reg = <0x7000d400 0x200>; 626*724ba675SRob Herring interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 627*724ba675SRob Herring #address-cells = <1>; 628*724ba675SRob Herring #size-cells = <0>; 629*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SBC1>; 630*724ba675SRob Herring resets = <&tegra_car 41>; 631*724ba675SRob Herring reset-names = "spi"; 632*724ba675SRob Herring dmas = <&apbdma 15>, <&apbdma 15>; 633*724ba675SRob Herring dma-names = "rx", "tx"; 634*724ba675SRob Herring status = "disabled"; 635*724ba675SRob Herring }; 636*724ba675SRob Herring 637*724ba675SRob Herring spi@7000d600 { 638*724ba675SRob Herring compatible = "nvidia,tegra20-slink"; 639*724ba675SRob Herring reg = <0x7000d600 0x200>; 640*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 641*724ba675SRob Herring #address-cells = <1>; 642*724ba675SRob Herring #size-cells = <0>; 643*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SBC2>; 644*724ba675SRob Herring resets = <&tegra_car 44>; 645*724ba675SRob Herring reset-names = "spi"; 646*724ba675SRob Herring dmas = <&apbdma 16>, <&apbdma 16>; 647*724ba675SRob Herring dma-names = "rx", "tx"; 648*724ba675SRob Herring status = "disabled"; 649*724ba675SRob Herring }; 650*724ba675SRob Herring 651*724ba675SRob Herring spi@7000d800 { 652*724ba675SRob Herring compatible = "nvidia,tegra20-slink"; 653*724ba675SRob Herring reg = <0x7000d800 0x200>; 654*724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 655*724ba675SRob Herring #address-cells = <1>; 656*724ba675SRob Herring #size-cells = <0>; 657*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SBC3>; 658*724ba675SRob Herring resets = <&tegra_car 46>; 659*724ba675SRob Herring reset-names = "spi"; 660*724ba675SRob Herring dmas = <&apbdma 17>, <&apbdma 17>; 661*724ba675SRob Herring dma-names = "rx", "tx"; 662*724ba675SRob Herring status = "disabled"; 663*724ba675SRob Herring }; 664*724ba675SRob Herring 665*724ba675SRob Herring spi@7000da00 { 666*724ba675SRob Herring compatible = "nvidia,tegra20-slink"; 667*724ba675SRob Herring reg = <0x7000da00 0x200>; 668*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 669*724ba675SRob Herring #address-cells = <1>; 670*724ba675SRob Herring #size-cells = <0>; 671*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SBC4>; 672*724ba675SRob Herring resets = <&tegra_car 68>; 673*724ba675SRob Herring reset-names = "spi"; 674*724ba675SRob Herring dmas = <&apbdma 18>, <&apbdma 18>; 675*724ba675SRob Herring dma-names = "rx", "tx"; 676*724ba675SRob Herring status = "disabled"; 677*724ba675SRob Herring }; 678*724ba675SRob Herring 679*724ba675SRob Herring rtc@7000e000 { 680*724ba675SRob Herring compatible = "nvidia,tegra20-rtc"; 681*724ba675SRob Herring reg = <0x7000e000 0x100>; 682*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 683*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_RTC>; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring kbc@7000e200 { 687*724ba675SRob Herring compatible = "nvidia,tegra20-kbc"; 688*724ba675SRob Herring reg = <0x7000e200 0x100>; 689*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 690*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_KBC>; 691*724ba675SRob Herring resets = <&tegra_car 36>; 692*724ba675SRob Herring reset-names = "kbc"; 693*724ba675SRob Herring status = "disabled"; 694*724ba675SRob Herring }; 695*724ba675SRob Herring 696*724ba675SRob Herring tegra_pmc: pmc@7000e400 { 697*724ba675SRob Herring compatible = "nvidia,tegra20-pmc"; 698*724ba675SRob Herring reg = <0x7000e400 0x400>; 699*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 700*724ba675SRob Herring clock-names = "pclk", "clk32k_in"; 701*724ba675SRob Herring #clock-cells = <1>; 702*724ba675SRob Herring 703*724ba675SRob Herring pd_core: core-domain { 704*724ba675SRob Herring #power-domain-cells = <0>; 705*724ba675SRob Herring operating-points-v2 = <&core_opp_table>; 706*724ba675SRob Herring }; 707*724ba675SRob Herring 708*724ba675SRob Herring powergates { 709*724ba675SRob Herring pd_mpe: mpe { 710*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_MPE>; 711*724ba675SRob Herring resets = <&mc TEGRA20_MC_RESET_MPEA>, 712*724ba675SRob Herring <&mc TEGRA20_MC_RESET_MPEB>, 713*724ba675SRob Herring <&mc TEGRA20_MC_RESET_MPEC>, 714*724ba675SRob Herring <&tegra_car TEGRA20_CLK_MPE>; 715*724ba675SRob Herring power-domains = <&pd_core>; 716*724ba675SRob Herring #power-domain-cells = <0>; 717*724ba675SRob Herring }; 718*724ba675SRob Herring 719*724ba675SRob Herring pd_3d: td { 720*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_GR3D>; 721*724ba675SRob Herring resets = <&mc TEGRA20_MC_RESET_3D>, 722*724ba675SRob Herring <&tegra_car TEGRA20_CLK_GR3D>; 723*724ba675SRob Herring power-domains = <&pd_core>; 724*724ba675SRob Herring #power-domain-cells = <0>; 725*724ba675SRob Herring }; 726*724ba675SRob Herring 727*724ba675SRob Herring pd_vde: vdec { 728*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_VDE>; 729*724ba675SRob Herring resets = <&mc TEGRA20_MC_RESET_VDE>, 730*724ba675SRob Herring <&tegra_car TEGRA20_CLK_VDE>; 731*724ba675SRob Herring power-domains = <&pd_core>; 732*724ba675SRob Herring #power-domain-cells = <0>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring pd_venc: venc { 736*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_ISP>, 737*724ba675SRob Herring <&tegra_car TEGRA20_CLK_VI>, 738*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CSI>; 739*724ba675SRob Herring resets = <&mc TEGRA20_MC_RESET_ISP>, 740*724ba675SRob Herring <&mc TEGRA20_MC_RESET_VI>, 741*724ba675SRob Herring <&tegra_car TEGRA20_CLK_ISP>, 742*724ba675SRob Herring <&tegra_car 20 /* VI */>, 743*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CSI>; 744*724ba675SRob Herring power-domains = <&pd_core>; 745*724ba675SRob Herring #power-domain-cells = <0>; 746*724ba675SRob Herring }; 747*724ba675SRob Herring }; 748*724ba675SRob Herring }; 749*724ba675SRob Herring 750*724ba675SRob Herring mc: memory-controller@7000f000 { 751*724ba675SRob Herring compatible = "nvidia,tegra20-mc-gart"; 752*724ba675SRob Herring reg = <0x7000f000 0x00000400>, /* controller registers */ 753*724ba675SRob Herring <0x58000000 0x02000000>; /* GART aperture */ 754*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_MC>; 755*724ba675SRob Herring clock-names = "mc"; 756*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 757*724ba675SRob Herring #reset-cells = <1>; 758*724ba675SRob Herring #iommu-cells = <0>; 759*724ba675SRob Herring #interconnect-cells = <1>; 760*724ba675SRob Herring }; 761*724ba675SRob Herring 762*724ba675SRob Herring emc: memory-controller@7000f400 { 763*724ba675SRob Herring compatible = "nvidia,tegra20-emc"; 764*724ba675SRob Herring reg = <0x7000f400 0x400>; 765*724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 766*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_EMC>; 767*724ba675SRob Herring power-domains = <&pd_core>; 768*724ba675SRob Herring #address-cells = <1>; 769*724ba675SRob Herring #size-cells = <0>; 770*724ba675SRob Herring #interconnect-cells = <0>; 771*724ba675SRob Herring 772*724ba675SRob Herring nvidia,memory-controller = <&mc>; 773*724ba675SRob Herring operating-points-v2 = <&emc_icc_dvfs_opp_table>; 774*724ba675SRob Herring }; 775*724ba675SRob Herring 776*724ba675SRob Herring fuse@7000f800 { 777*724ba675SRob Herring compatible = "nvidia,tegra20-efuse"; 778*724ba675SRob Herring reg = <0x7000f800 0x400>; 779*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_FUSE>; 780*724ba675SRob Herring clock-names = "fuse"; 781*724ba675SRob Herring resets = <&tegra_car 39>; 782*724ba675SRob Herring reset-names = "fuse"; 783*724ba675SRob Herring }; 784*724ba675SRob Herring 785*724ba675SRob Herring pcie@80003000 { 786*724ba675SRob Herring compatible = "nvidia,tegra20-pcie"; 787*724ba675SRob Herring device_type = "pci"; 788*724ba675SRob Herring reg = <0x80003000 0x00000800>, /* PADS registers */ 789*724ba675SRob Herring <0x80003800 0x00000200>, /* AFI registers */ 790*724ba675SRob Herring <0x90000000 0x10000000>; /* configuration space */ 791*724ba675SRob Herring reg-names = "pads", "afi", "cs"; 792*724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 793*724ba675SRob Herring <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 794*724ba675SRob Herring interrupt-names = "intr", "msi"; 795*724ba675SRob Herring 796*724ba675SRob Herring #interrupt-cells = <1>; 797*724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 798*724ba675SRob Herring interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 799*724ba675SRob Herring 800*724ba675SRob Herring bus-range = <0x00 0xff>; 801*724ba675SRob Herring #address-cells = <3>; 802*724ba675SRob Herring #size-cells = <2>; 803*724ba675SRob Herring 804*724ba675SRob Herring ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ 805*724ba675SRob Herring <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ 806*724ba675SRob Herring <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ 807*724ba675SRob Herring <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ 808*724ba675SRob Herring <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 809*724ba675SRob Herring 810*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_PEX>, 811*724ba675SRob Herring <&tegra_car TEGRA20_CLK_AFI>, 812*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_E>; 813*724ba675SRob Herring clock-names = "pex", "afi", "pll_e"; 814*724ba675SRob Herring resets = <&tegra_car 70>, 815*724ba675SRob Herring <&tegra_car 72>, 816*724ba675SRob Herring <&tegra_car 74>; 817*724ba675SRob Herring reset-names = "pex", "afi", "pcie_x"; 818*724ba675SRob Herring power-domains = <&pd_core>; 819*724ba675SRob Herring operating-points-v2 = <&pcie_dvfs_opp_table>; 820*724ba675SRob Herring 821*724ba675SRob Herring status = "disabled"; 822*724ba675SRob Herring 823*724ba675SRob Herring pci@1,0 { 824*724ba675SRob Herring device_type = "pci"; 825*724ba675SRob Herring assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 826*724ba675SRob Herring reg = <0x000800 0 0 0 0>; 827*724ba675SRob Herring bus-range = <0x00 0xff>; 828*724ba675SRob Herring status = "disabled"; 829*724ba675SRob Herring 830*724ba675SRob Herring #address-cells = <3>; 831*724ba675SRob Herring #size-cells = <2>; 832*724ba675SRob Herring ranges; 833*724ba675SRob Herring 834*724ba675SRob Herring nvidia,num-lanes = <2>; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring pci@2,0 { 838*724ba675SRob Herring device_type = "pci"; 839*724ba675SRob Herring assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 840*724ba675SRob Herring reg = <0x001000 0 0 0 0>; 841*724ba675SRob Herring bus-range = <0x00 0xff>; 842*724ba675SRob Herring status = "disabled"; 843*724ba675SRob Herring 844*724ba675SRob Herring #address-cells = <3>; 845*724ba675SRob Herring #size-cells = <2>; 846*724ba675SRob Herring ranges; 847*724ba675SRob Herring 848*724ba675SRob Herring nvidia,num-lanes = <2>; 849*724ba675SRob Herring }; 850*724ba675SRob Herring }; 851*724ba675SRob Herring 852*724ba675SRob Herring usb@c5000000 { 853*724ba675SRob Herring compatible = "nvidia,tegra20-ehci"; 854*724ba675SRob Herring reg = <0xc5000000 0x4000>; 855*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 856*724ba675SRob Herring phy_type = "utmi"; 857*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USBD>; 858*724ba675SRob Herring resets = <&tegra_car 22>; 859*724ba675SRob Herring reset-names = "usb"; 860*724ba675SRob Herring nvidia,needs-double-reset; 861*724ba675SRob Herring nvidia,phy = <&phy1>; 862*724ba675SRob Herring power-domains = <&pd_core>; 863*724ba675SRob Herring operating-points-v2 = <&usbd_dvfs_opp_table>; 864*724ba675SRob Herring status = "disabled"; 865*724ba675SRob Herring }; 866*724ba675SRob Herring 867*724ba675SRob Herring phy1: usb-phy@c5000000 { 868*724ba675SRob Herring compatible = "nvidia,tegra20-usb-phy"; 869*724ba675SRob Herring reg = <0xc5000000 0x4000>, 870*724ba675SRob Herring <0xc5000000 0x4000>; 871*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 872*724ba675SRob Herring phy_type = "utmi"; 873*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USBD>, 874*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_U>, 875*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CLK_M>, 876*724ba675SRob Herring <&tegra_car TEGRA20_CLK_USBD>; 877*724ba675SRob Herring clock-names = "reg", "pll_u", "timer", "utmi-pads"; 878*724ba675SRob Herring resets = <&tegra_car 22>, <&tegra_car 22>; 879*724ba675SRob Herring reset-names = "usb", "utmi-pads"; 880*724ba675SRob Herring #phy-cells = <0>; 881*724ba675SRob Herring nvidia,has-legacy-mode; 882*724ba675SRob Herring nvidia,hssync-start-delay = <9>; 883*724ba675SRob Herring nvidia,idle-wait-delay = <17>; 884*724ba675SRob Herring nvidia,elastic-limit = <16>; 885*724ba675SRob Herring nvidia,term-range-adj = <6>; 886*724ba675SRob Herring nvidia,xcvr-setup = <9>; 887*724ba675SRob Herring nvidia,xcvr-lsfslew = <1>; 888*724ba675SRob Herring nvidia,xcvr-lsrslew = <1>; 889*724ba675SRob Herring nvidia,has-utmi-pad-registers; 890*724ba675SRob Herring nvidia,pmc = <&tegra_pmc 0>; 891*724ba675SRob Herring status = "disabled"; 892*724ba675SRob Herring }; 893*724ba675SRob Herring 894*724ba675SRob Herring usb@c5004000 { 895*724ba675SRob Herring compatible = "nvidia,tegra20-ehci"; 896*724ba675SRob Herring reg = <0xc5004000 0x4000>; 897*724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 898*724ba675SRob Herring phy_type = "ulpi"; 899*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USB2>; 900*724ba675SRob Herring resets = <&tegra_car 58>; 901*724ba675SRob Herring reset-names = "usb"; 902*724ba675SRob Herring nvidia,phy = <&phy2>; 903*724ba675SRob Herring power-domains = <&pd_core>; 904*724ba675SRob Herring operating-points-v2 = <&usb2_dvfs_opp_table>; 905*724ba675SRob Herring status = "disabled"; 906*724ba675SRob Herring }; 907*724ba675SRob Herring 908*724ba675SRob Herring phy2: usb-phy@c5004000 { 909*724ba675SRob Herring compatible = "nvidia,tegra20-usb-phy"; 910*724ba675SRob Herring reg = <0xc5004000 0x4000>; 911*724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 912*724ba675SRob Herring phy_type = "ulpi"; 913*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USB2>, 914*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_U>, 915*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CDEV2>; 916*724ba675SRob Herring clock-names = "reg", "pll_u", "ulpi-link"; 917*724ba675SRob Herring resets = <&tegra_car 58>, <&tegra_car 22>; 918*724ba675SRob Herring reset-names = "usb", "utmi-pads"; 919*724ba675SRob Herring #phy-cells = <0>; 920*724ba675SRob Herring nvidia,pmc = <&tegra_pmc 1>; 921*724ba675SRob Herring status = "disabled"; 922*724ba675SRob Herring }; 923*724ba675SRob Herring 924*724ba675SRob Herring usb@c5008000 { 925*724ba675SRob Herring compatible = "nvidia,tegra20-ehci"; 926*724ba675SRob Herring reg = <0xc5008000 0x4000>; 927*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 928*724ba675SRob Herring phy_type = "utmi"; 929*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USB3>; 930*724ba675SRob Herring resets = <&tegra_car 59>; 931*724ba675SRob Herring reset-names = "usb"; 932*724ba675SRob Herring nvidia,phy = <&phy3>; 933*724ba675SRob Herring power-domains = <&pd_core>; 934*724ba675SRob Herring operating-points-v2 = <&usb3_dvfs_opp_table>; 935*724ba675SRob Herring status = "disabled"; 936*724ba675SRob Herring }; 937*724ba675SRob Herring 938*724ba675SRob Herring phy3: usb-phy@c5008000 { 939*724ba675SRob Herring compatible = "nvidia,tegra20-usb-phy"; 940*724ba675SRob Herring reg = <0xc5008000 0x4000>, 941*724ba675SRob Herring <0xc5000000 0x4000>; 942*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 943*724ba675SRob Herring phy_type = "utmi"; 944*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_USB3>, 945*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_U>, 946*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CLK_M>, 947*724ba675SRob Herring <&tegra_car TEGRA20_CLK_USBD>; 948*724ba675SRob Herring clock-names = "reg", "pll_u", "timer", "utmi-pads"; 949*724ba675SRob Herring resets = <&tegra_car 59>, <&tegra_car 22>; 950*724ba675SRob Herring reset-names = "usb", "utmi-pads"; 951*724ba675SRob Herring #phy-cells = <0>; 952*724ba675SRob Herring nvidia,hssync-start-delay = <9>; 953*724ba675SRob Herring nvidia,idle-wait-delay = <17>; 954*724ba675SRob Herring nvidia,elastic-limit = <16>; 955*724ba675SRob Herring nvidia,term-range-adj = <6>; 956*724ba675SRob Herring nvidia,xcvr-setup = <9>; 957*724ba675SRob Herring nvidia,xcvr-lsfslew = <2>; 958*724ba675SRob Herring nvidia,xcvr-lsrslew = <2>; 959*724ba675SRob Herring nvidia,pmc = <&tegra_pmc 2>; 960*724ba675SRob Herring status = "disabled"; 961*724ba675SRob Herring }; 962*724ba675SRob Herring 963*724ba675SRob Herring mmc@c8000000 { 964*724ba675SRob Herring compatible = "nvidia,tegra20-sdhci"; 965*724ba675SRob Herring reg = <0xc8000000 0x200>; 966*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 967*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 968*724ba675SRob Herring clock-names = "sdhci"; 969*724ba675SRob Herring resets = <&tegra_car 14>; 970*724ba675SRob Herring reset-names = "sdhci"; 971*724ba675SRob Herring power-domains = <&pd_core>; 972*724ba675SRob Herring operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 973*724ba675SRob Herring status = "disabled"; 974*724ba675SRob Herring }; 975*724ba675SRob Herring 976*724ba675SRob Herring mmc@c8000200 { 977*724ba675SRob Herring compatible = "nvidia,tegra20-sdhci"; 978*724ba675SRob Herring reg = <0xc8000200 0x200>; 979*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 980*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 981*724ba675SRob Herring clock-names = "sdhci"; 982*724ba675SRob Herring resets = <&tegra_car 9>; 983*724ba675SRob Herring reset-names = "sdhci"; 984*724ba675SRob Herring power-domains = <&pd_core>; 985*724ba675SRob Herring operating-points-v2 = <&sdmmc2_dvfs_opp_table>; 986*724ba675SRob Herring status = "disabled"; 987*724ba675SRob Herring }; 988*724ba675SRob Herring 989*724ba675SRob Herring mmc@c8000400 { 990*724ba675SRob Herring compatible = "nvidia,tegra20-sdhci"; 991*724ba675SRob Herring reg = <0xc8000400 0x200>; 992*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 993*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 994*724ba675SRob Herring clock-names = "sdhci"; 995*724ba675SRob Herring resets = <&tegra_car 69>; 996*724ba675SRob Herring reset-names = "sdhci"; 997*724ba675SRob Herring power-domains = <&pd_core>; 998*724ba675SRob Herring operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 999*724ba675SRob Herring status = "disabled"; 1000*724ba675SRob Herring }; 1001*724ba675SRob Herring 1002*724ba675SRob Herring mmc@c8000600 { 1003*724ba675SRob Herring compatible = "nvidia,tegra20-sdhci"; 1004*724ba675SRob Herring reg = <0xc8000600 0x200>; 1005*724ba675SRob Herring interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1006*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 1007*724ba675SRob Herring clock-names = "sdhci"; 1008*724ba675SRob Herring resets = <&tegra_car 15>; 1009*724ba675SRob Herring reset-names = "sdhci"; 1010*724ba675SRob Herring power-domains = <&pd_core>; 1011*724ba675SRob Herring operating-points-v2 = <&sdmmc4_dvfs_opp_table>; 1012*724ba675SRob Herring status = "disabled"; 1013*724ba675SRob Herring }; 1014*724ba675SRob Herring 1015*724ba675SRob Herring cpus { 1016*724ba675SRob Herring #address-cells = <1>; 1017*724ba675SRob Herring #size-cells = <0>; 1018*724ba675SRob Herring 1019*724ba675SRob Herring cpu@0 { 1020*724ba675SRob Herring device_type = "cpu"; 1021*724ba675SRob Herring compatible = "arm,cortex-a9"; 1022*724ba675SRob Herring reg = <0>; 1023*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1024*724ba675SRob Herring }; 1025*724ba675SRob Herring 1026*724ba675SRob Herring cpu@1 { 1027*724ba675SRob Herring device_type = "cpu"; 1028*724ba675SRob Herring compatible = "arm,cortex-a9"; 1029*724ba675SRob Herring reg = <1>; 1030*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1031*724ba675SRob Herring }; 1032*724ba675SRob Herring }; 1033*724ba675SRob Herring 1034*724ba675SRob Herring pmu { 1035*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 1036*724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1037*724ba675SRob Herring <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1038*724ba675SRob Herring interrupt-affinity = <&{/cpus/cpu@0}>, 1039*724ba675SRob Herring <&{/cpus/cpu@1}>; 1040*724ba675SRob Herring }; 1041*724ba675SRob Herring 1042*724ba675SRob Herring sound-hdmi { 1043*724ba675SRob Herring compatible = "simple-audio-card"; 1044*724ba675SRob Herring simple-audio-card,name = "NVIDIA Tegra20 HDMI"; 1045*724ba675SRob Herring 1046*724ba675SRob Herring #address-cells = <1>; 1047*724ba675SRob Herring #size-cells = <0>; 1048*724ba675SRob Herring 1049*724ba675SRob Herring simple-audio-card,dai-link@0 { 1050*724ba675SRob Herring reg = <0>; 1051*724ba675SRob Herring 1052*724ba675SRob Herring codec { 1053*724ba675SRob Herring sound-dai = <&tegra_hdmi>; 1054*724ba675SRob Herring }; 1055*724ba675SRob Herring 1056*724ba675SRob Herring cpu { 1057*724ba675SRob Herring sound-dai = <&tegra_spdif>; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring }; 1060*724ba675SRob Herring }; 1061*724ba675SRob Herring}; 1062