xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra20-ventana.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/dts-v1/;
3*724ba675SRob Herring
4*724ba675SRob Herring#include <dt-bindings/input/input.h>
5*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h>
6*724ba675SRob Herring#include "tegra20.dtsi"
7*724ba675SRob Herring#include "tegra20-cpu-opp.dtsi"
8*724ba675SRob Herring#include "tegra20-cpu-opp-microvolt.dtsi"
9*724ba675SRob Herring
10*724ba675SRob Herring/ {
11*724ba675SRob Herring	model = "NVIDIA Tegra20 Ventana evaluation board";
12*724ba675SRob Herring	compatible = "nvidia,ventana", "nvidia,tegra20";
13*724ba675SRob Herring
14*724ba675SRob Herring	aliases {
15*724ba675SRob Herring		rtc0 = "/i2c@7000d000/tps6586x@34";
16*724ba675SRob Herring		rtc1 = "/rtc@7000e000";
17*724ba675SRob Herring		serial0 = &uartd;
18*724ba675SRob Herring	};
19*724ba675SRob Herring
20*724ba675SRob Herring	chosen {
21*724ba675SRob Herring		stdout-path = "serial0:115200n8";
22*724ba675SRob Herring	};
23*724ba675SRob Herring
24*724ba675SRob Herring	memory@0 {
25*724ba675SRob Herring		reg = <0x00000000 0x40000000>;
26*724ba675SRob Herring	};
27*724ba675SRob Herring
28*724ba675SRob Herring	host1x@50000000 {
29*724ba675SRob Herring		dc@54200000 {
30*724ba675SRob Herring			rgb {
31*724ba675SRob Herring				status = "okay";
32*724ba675SRob Herring
33*724ba675SRob Herring				nvidia,panel = <&panel>;
34*724ba675SRob Herring			};
35*724ba675SRob Herring		};
36*724ba675SRob Herring
37*724ba675SRob Herring		hdmi@54280000 {
38*724ba675SRob Herring			status = "okay";
39*724ba675SRob Herring
40*724ba675SRob Herring			vdd-supply = <&hdmi_vdd_reg>;
41*724ba675SRob Herring			pll-supply = <&hdmi_pll_reg>;
42*724ba675SRob Herring
43*724ba675SRob Herring			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44*724ba675SRob Herring			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
45*724ba675SRob Herring				GPIO_ACTIVE_HIGH>;
46*724ba675SRob Herring		};
47*724ba675SRob Herring	};
48*724ba675SRob Herring
49*724ba675SRob Herring	pinmux@70000014 {
50*724ba675SRob Herring		pinctrl-names = "default";
51*724ba675SRob Herring		pinctrl-0 = <&state_default>;
52*724ba675SRob Herring
53*724ba675SRob Herring		state_default: pinmux {
54*724ba675SRob Herring			ata {
55*724ba675SRob Herring				nvidia,pins = "ata";
56*724ba675SRob Herring				nvidia,function = "ide";
57*724ba675SRob Herring			};
58*724ba675SRob Herring			atb {
59*724ba675SRob Herring				nvidia,pins = "atb", "gma", "gme";
60*724ba675SRob Herring				nvidia,function = "sdio4";
61*724ba675SRob Herring			};
62*724ba675SRob Herring			atc {
63*724ba675SRob Herring				nvidia,pins = "atc";
64*724ba675SRob Herring				nvidia,function = "nand";
65*724ba675SRob Herring			};
66*724ba675SRob Herring			atd {
67*724ba675SRob Herring				nvidia,pins = "atd", "ate", "gmb", "spia",
68*724ba675SRob Herring					"spib", "spic";
69*724ba675SRob Herring				nvidia,function = "gmi";
70*724ba675SRob Herring			};
71*724ba675SRob Herring			cdev1 {
72*724ba675SRob Herring				nvidia,pins = "cdev1";
73*724ba675SRob Herring				nvidia,function = "plla_out";
74*724ba675SRob Herring			};
75*724ba675SRob Herring			cdev2 {
76*724ba675SRob Herring				nvidia,pins = "cdev2";
77*724ba675SRob Herring				nvidia,function = "pllp_out4";
78*724ba675SRob Herring			};
79*724ba675SRob Herring			crtp {
80*724ba675SRob Herring				nvidia,pins = "crtp", "lm1";
81*724ba675SRob Herring				nvidia,function = "crt";
82*724ba675SRob Herring			};
83*724ba675SRob Herring			csus {
84*724ba675SRob Herring				nvidia,pins = "csus";
85*724ba675SRob Herring				nvidia,function = "vi_sensor_clk";
86*724ba675SRob Herring			};
87*724ba675SRob Herring			dap1 {
88*724ba675SRob Herring				nvidia,pins = "dap1";
89*724ba675SRob Herring				nvidia,function = "dap1";
90*724ba675SRob Herring			};
91*724ba675SRob Herring			dap2 {
92*724ba675SRob Herring				nvidia,pins = "dap2";
93*724ba675SRob Herring				nvidia,function = "dap2";
94*724ba675SRob Herring			};
95*724ba675SRob Herring			dap3 {
96*724ba675SRob Herring				nvidia,pins = "dap3";
97*724ba675SRob Herring				nvidia,function = "dap3";
98*724ba675SRob Herring			};
99*724ba675SRob Herring			dap4 {
100*724ba675SRob Herring				nvidia,pins = "dap4";
101*724ba675SRob Herring				nvidia,function = "dap4";
102*724ba675SRob Herring			};
103*724ba675SRob Herring			dta {
104*724ba675SRob Herring				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
105*724ba675SRob Herring				nvidia,function = "vi";
106*724ba675SRob Herring			};
107*724ba675SRob Herring			dtf {
108*724ba675SRob Herring				nvidia,pins = "dtf";
109*724ba675SRob Herring				nvidia,function = "i2c3";
110*724ba675SRob Herring			};
111*724ba675SRob Herring			gmc {
112*724ba675SRob Herring				nvidia,pins = "gmc";
113*724ba675SRob Herring				nvidia,function = "uartd";
114*724ba675SRob Herring			};
115*724ba675SRob Herring			gmd {
116*724ba675SRob Herring				nvidia,pins = "gmd";
117*724ba675SRob Herring				nvidia,function = "sflash";
118*724ba675SRob Herring			};
119*724ba675SRob Herring			gpu {
120*724ba675SRob Herring				nvidia,pins = "gpu";
121*724ba675SRob Herring				nvidia,function = "pwm";
122*724ba675SRob Herring			};
123*724ba675SRob Herring			gpu7 {
124*724ba675SRob Herring				nvidia,pins = "gpu7";
125*724ba675SRob Herring				nvidia,function = "rtck";
126*724ba675SRob Herring			};
127*724ba675SRob Herring			gpv {
128*724ba675SRob Herring				nvidia,pins = "gpv", "slxa", "slxk";
129*724ba675SRob Herring				nvidia,function = "pcie";
130*724ba675SRob Herring			};
131*724ba675SRob Herring			hdint {
132*724ba675SRob Herring				nvidia,pins = "hdint";
133*724ba675SRob Herring				nvidia,function = "hdmi";
134*724ba675SRob Herring			};
135*724ba675SRob Herring			i2cp {
136*724ba675SRob Herring				nvidia,pins = "i2cp";
137*724ba675SRob Herring				nvidia,function = "i2cp";
138*724ba675SRob Herring			};
139*724ba675SRob Herring			irrx {
140*724ba675SRob Herring				nvidia,pins = "irrx", "irtx";
141*724ba675SRob Herring				nvidia,function = "uartb";
142*724ba675SRob Herring			};
143*724ba675SRob Herring			kbca {
144*724ba675SRob Herring				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
145*724ba675SRob Herring					"kbce", "kbcf";
146*724ba675SRob Herring				nvidia,function = "kbc";
147*724ba675SRob Herring			};
148*724ba675SRob Herring			lcsn {
149*724ba675SRob Herring				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
150*724ba675SRob Herring					"lsdi", "lvp0";
151*724ba675SRob Herring				nvidia,function = "rsvd4";
152*724ba675SRob Herring			};
153*724ba675SRob Herring			ld0 {
154*724ba675SRob Herring				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
155*724ba675SRob Herring					"ld5", "ld6", "ld7", "ld8", "ld9",
156*724ba675SRob Herring					"ld10", "ld11", "ld12", "ld13", "ld14",
157*724ba675SRob Herring					"ld15", "ld16", "ld17", "ldi", "lhp0",
158*724ba675SRob Herring					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
159*724ba675SRob Herring					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
160*724ba675SRob Herring					"lspi", "lvp1", "lvs";
161*724ba675SRob Herring				nvidia,function = "displaya";
162*724ba675SRob Herring			};
163*724ba675SRob Herring			owc {
164*724ba675SRob Herring				nvidia,pins = "owc", "spdi", "spdo", "uac";
165*724ba675SRob Herring				nvidia,function = "rsvd2";
166*724ba675SRob Herring			};
167*724ba675SRob Herring			pmc {
168*724ba675SRob Herring				nvidia,pins = "pmc";
169*724ba675SRob Herring				nvidia,function = "pwr_on";
170*724ba675SRob Herring			};
171*724ba675SRob Herring			rm {
172*724ba675SRob Herring				nvidia,pins = "rm";
173*724ba675SRob Herring				nvidia,function = "i2c1";
174*724ba675SRob Herring			};
175*724ba675SRob Herring			sdb {
176*724ba675SRob Herring				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
177*724ba675SRob Herring				nvidia,function = "sdio3";
178*724ba675SRob Herring			};
179*724ba675SRob Herring			sdio1 {
180*724ba675SRob Herring				nvidia,pins = "sdio1";
181*724ba675SRob Herring				nvidia,function = "sdio1";
182*724ba675SRob Herring			};
183*724ba675SRob Herring			slxd {
184*724ba675SRob Herring				nvidia,pins = "slxd";
185*724ba675SRob Herring				nvidia,function = "spdif";
186*724ba675SRob Herring			};
187*724ba675SRob Herring			spid {
188*724ba675SRob Herring				nvidia,pins = "spid", "spie", "spif";
189*724ba675SRob Herring				nvidia,function = "spi1";
190*724ba675SRob Herring			};
191*724ba675SRob Herring			spig {
192*724ba675SRob Herring				nvidia,pins = "spig", "spih";
193*724ba675SRob Herring				nvidia,function = "spi2_alt";
194*724ba675SRob Herring			};
195*724ba675SRob Herring			uaa {
196*724ba675SRob Herring				nvidia,pins = "uaa", "uab", "uda";
197*724ba675SRob Herring				nvidia,function = "ulpi";
198*724ba675SRob Herring			};
199*724ba675SRob Herring			uad {
200*724ba675SRob Herring				nvidia,pins = "uad";
201*724ba675SRob Herring				nvidia,function = "irda";
202*724ba675SRob Herring			};
203*724ba675SRob Herring			uca {
204*724ba675SRob Herring				nvidia,pins = "uca", "ucb";
205*724ba675SRob Herring				nvidia,function = "uartc";
206*724ba675SRob Herring			};
207*724ba675SRob Herring			conf_ata {
208*724ba675SRob Herring				nvidia,pins = "ata", "atb", "atc", "atd",
209*724ba675SRob Herring					"cdev1", "cdev2", "dap1", "dap2",
210*724ba675SRob Herring					"dap4", "ddc", "dtf", "gma", "gmc",
211*724ba675SRob Herring					"gme", "gpu", "gpu7", "i2cp", "irrx",
212*724ba675SRob Herring					"irtx", "pta", "rm", "sdc", "sdd",
213*724ba675SRob Herring					"slxc", "slxd", "slxk", "spdi", "spdo",
214*724ba675SRob Herring					"uac", "uad", "uca", "ucb", "uda";
215*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
217*724ba675SRob Herring			};
218*724ba675SRob Herring			conf_ate {
219*724ba675SRob Herring				nvidia,pins = "ate", "csus", "dap3", "gmd",
220*724ba675SRob Herring					"gpv", "owc", "spia", "spib", "spic",
221*724ba675SRob Herring					"spid", "spie", "spig";
222*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
224*724ba675SRob Herring			};
225*724ba675SRob Herring			conf_ck32 {
226*724ba675SRob Herring				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
227*724ba675SRob Herring					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
228*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
229*724ba675SRob Herring			};
230*724ba675SRob Herring			conf_crtp {
231*724ba675SRob Herring				nvidia,pins = "crtp", "gmb", "slxa", "spih";
232*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
233*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
234*724ba675SRob Herring			};
235*724ba675SRob Herring			conf_dta {
236*724ba675SRob Herring				nvidia,pins = "dta", "dtb", "dtc", "dtd";
237*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
239*724ba675SRob Herring			};
240*724ba675SRob Herring			conf_dte {
241*724ba675SRob Herring				nvidia,pins = "dte", "spif";
242*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
243*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
244*724ba675SRob Herring			};
245*724ba675SRob Herring			conf_hdint {
246*724ba675SRob Herring				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
247*724ba675SRob Herring					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
248*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
249*724ba675SRob Herring			};
250*724ba675SRob Herring			conf_kbca {
251*724ba675SRob Herring				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
252*724ba675SRob Herring					"kbce", "kbcf", "sdio1", "uaa", "uab";
253*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
254*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
255*724ba675SRob Herring			};
256*724ba675SRob Herring			conf_lc {
257*724ba675SRob Herring				nvidia,pins = "lc", "ls";
258*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
259*724ba675SRob Herring			};
260*724ba675SRob Herring			conf_ld0 {
261*724ba675SRob Herring				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
262*724ba675SRob Herring					"ld5", "ld6", "ld7", "ld8", "ld9",
263*724ba675SRob Herring					"ld10", "ld11", "ld12", "ld13", "ld14",
264*724ba675SRob Herring					"ld15", "ld16", "ld17", "ldi", "lhp0",
265*724ba675SRob Herring					"lhp1", "lhp2", "lhs", "lm0", "lpp",
266*724ba675SRob Herring					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
267*724ba675SRob Herring					"lvp1", "lvs", "pmc", "sdb";
268*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
269*724ba675SRob Herring			};
270*724ba675SRob Herring			conf_ld17_0 {
271*724ba675SRob Herring				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
272*724ba675SRob Herring					"ld23_22";
273*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
274*724ba675SRob Herring			};
275*724ba675SRob Herring			drive_sdio1 {
276*724ba675SRob Herring				nvidia,pins = "drive_sdio1";
277*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
278*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
279*724ba675SRob Herring				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
280*724ba675SRob Herring				nvidia,pull-down-strength = <31>;
281*724ba675SRob Herring				nvidia,pull-up-strength = <31>;
282*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
283*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
284*724ba675SRob Herring			};
285*724ba675SRob Herring		};
286*724ba675SRob Herring
287*724ba675SRob Herring		state_i2cmux_ddc: pinmux-i2cmux-ddc {
288*724ba675SRob Herring			ddc {
289*724ba675SRob Herring				nvidia,pins = "ddc";
290*724ba675SRob Herring				nvidia,function = "i2c2";
291*724ba675SRob Herring			};
292*724ba675SRob Herring			pta {
293*724ba675SRob Herring				nvidia,pins = "pta";
294*724ba675SRob Herring				nvidia,function = "rsvd4";
295*724ba675SRob Herring			};
296*724ba675SRob Herring		};
297*724ba675SRob Herring
298*724ba675SRob Herring		state_i2cmux_idle: pinmux-i2cmux-idle {
299*724ba675SRob Herring			ddc {
300*724ba675SRob Herring				nvidia,pins = "ddc";
301*724ba675SRob Herring				nvidia,function = "rsvd4";
302*724ba675SRob Herring			};
303*724ba675SRob Herring			pta {
304*724ba675SRob Herring				nvidia,pins = "pta";
305*724ba675SRob Herring				nvidia,function = "rsvd4";
306*724ba675SRob Herring			};
307*724ba675SRob Herring		};
308*724ba675SRob Herring
309*724ba675SRob Herring		state_i2cmux_pta: pinmux-i2cmux-pta {
310*724ba675SRob Herring			ddc {
311*724ba675SRob Herring				nvidia,pins = "ddc";
312*724ba675SRob Herring				nvidia,function = "rsvd4";
313*724ba675SRob Herring			};
314*724ba675SRob Herring			pta {
315*724ba675SRob Herring				nvidia,pins = "pta";
316*724ba675SRob Herring				nvidia,function = "i2c2";
317*724ba675SRob Herring			};
318*724ba675SRob Herring		};
319*724ba675SRob Herring	};
320*724ba675SRob Herring
321*724ba675SRob Herring	i2s@70002800 {
322*724ba675SRob Herring		status = "okay";
323*724ba675SRob Herring	};
324*724ba675SRob Herring
325*724ba675SRob Herring	serial@70006300 {
326*724ba675SRob Herring		status = "okay";
327*724ba675SRob Herring	};
328*724ba675SRob Herring
329*724ba675SRob Herring	pwm: pwm@7000a000 {
330*724ba675SRob Herring		status = "okay";
331*724ba675SRob Herring	};
332*724ba675SRob Herring
333*724ba675SRob Herring	i2c@7000c000 {
334*724ba675SRob Herring		status = "okay";
335*724ba675SRob Herring		clock-frequency = <400000>;
336*724ba675SRob Herring
337*724ba675SRob Herring		wm8903: wm8903@1a {
338*724ba675SRob Herring			compatible = "wlf,wm8903";
339*724ba675SRob Herring			reg = <0x1a>;
340*724ba675SRob Herring			interrupt-parent = <&gpio>;
341*724ba675SRob Herring			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
342*724ba675SRob Herring
343*724ba675SRob Herring			gpio-controller;
344*724ba675SRob Herring			#gpio-cells = <2>;
345*724ba675SRob Herring
346*724ba675SRob Herring			micdet-cfg = <0>;
347*724ba675SRob Herring			micdet-delay = <100>;
348*724ba675SRob Herring			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
349*724ba675SRob Herring		};
350*724ba675SRob Herring
351*724ba675SRob Herring		/* ALS and proximity sensor */
352*724ba675SRob Herring		isl29018@44 {
353*724ba675SRob Herring			compatible = "isil,isl29018";
354*724ba675SRob Herring			reg = <0x44>;
355*724ba675SRob Herring			interrupt-parent = <&gpio>;
356*724ba675SRob Herring			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
357*724ba675SRob Herring		};
358*724ba675SRob Herring	};
359*724ba675SRob Herring
360*724ba675SRob Herring	i2c@7000c400 {
361*724ba675SRob Herring		status = "okay";
362*724ba675SRob Herring		clock-frequency = <100000>;
363*724ba675SRob Herring	};
364*724ba675SRob Herring
365*724ba675SRob Herring	i2c@7000c500 {
366*724ba675SRob Herring		status = "okay";
367*724ba675SRob Herring		clock-frequency = <400000>;
368*724ba675SRob Herring	};
369*724ba675SRob Herring
370*724ba675SRob Herring	i2c@7000d000 {
371*724ba675SRob Herring		status = "okay";
372*724ba675SRob Herring		clock-frequency = <400000>;
373*724ba675SRob Herring
374*724ba675SRob Herring		pmic: tps6586x@34 {
375*724ba675SRob Herring			compatible = "ti,tps6586x";
376*724ba675SRob Herring			reg = <0x34>;
377*724ba675SRob Herring			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
378*724ba675SRob Herring
379*724ba675SRob Herring			ti,system-power-controller;
380*724ba675SRob Herring
381*724ba675SRob Herring			#gpio-cells = <2>;
382*724ba675SRob Herring			gpio-controller;
383*724ba675SRob Herring
384*724ba675SRob Herring			sys-supply = <&vdd_5v0_reg>;
385*724ba675SRob Herring			vin-sm0-supply = <&sys_reg>;
386*724ba675SRob Herring			vin-sm1-supply = <&sys_reg>;
387*724ba675SRob Herring			vin-sm2-supply = <&sys_reg>;
388*724ba675SRob Herring			vinldo01-supply = <&sm2_reg>;
389*724ba675SRob Herring			vinldo23-supply = <&sm2_reg>;
390*724ba675SRob Herring			vinldo4-supply = <&sm2_reg>;
391*724ba675SRob Herring			vinldo678-supply = <&sm2_reg>;
392*724ba675SRob Herring			vinldo9-supply = <&sm2_reg>;
393*724ba675SRob Herring
394*724ba675SRob Herring			regulators {
395*724ba675SRob Herring				sys_reg: sys {
396*724ba675SRob Herring					regulator-name = "vdd_sys";
397*724ba675SRob Herring					regulator-always-on;
398*724ba675SRob Herring				};
399*724ba675SRob Herring
400*724ba675SRob Herring				vdd_core: sm0 {
401*724ba675SRob Herring					regulator-name = "vdd_sm0,vdd_core";
402*724ba675SRob Herring					regulator-min-microvolt = <950000>;
403*724ba675SRob Herring					regulator-max-microvolt = <1300000>;
404*724ba675SRob Herring					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
405*724ba675SRob Herring					regulator-coupled-max-spread = <170000 550000>;
406*724ba675SRob Herring					regulator-always-on;
407*724ba675SRob Herring					regulator-boot-on;
408*724ba675SRob Herring
409*724ba675SRob Herring					nvidia,tegra-core-regulator;
410*724ba675SRob Herring				};
411*724ba675SRob Herring
412*724ba675SRob Herring				vdd_cpu: sm1 {
413*724ba675SRob Herring					regulator-name = "vdd_sm1,vdd_cpu";
414*724ba675SRob Herring					regulator-min-microvolt = <750000>;
415*724ba675SRob Herring					regulator-max-microvolt = <1125000>;
416*724ba675SRob Herring					regulator-coupled-with = <&vdd_core &rtc_vdd>;
417*724ba675SRob Herring					regulator-coupled-max-spread = <550000 550000>;
418*724ba675SRob Herring					regulator-always-on;
419*724ba675SRob Herring					regulator-boot-on;
420*724ba675SRob Herring
421*724ba675SRob Herring					nvidia,tegra-cpu-regulator;
422*724ba675SRob Herring				};
423*724ba675SRob Herring
424*724ba675SRob Herring				sm2_reg: sm2 {
425*724ba675SRob Herring					regulator-name = "vdd_sm2,vin_ldo*";
426*724ba675SRob Herring					regulator-min-microvolt = <3700000>;
427*724ba675SRob Herring					regulator-max-microvolt = <3700000>;
428*724ba675SRob Herring					regulator-always-on;
429*724ba675SRob Herring				};
430*724ba675SRob Herring
431*724ba675SRob Herring				/* LDO0 is not connected to anything */
432*724ba675SRob Herring
433*724ba675SRob Herring				ldo1 {
434*724ba675SRob Herring					regulator-name = "vdd_ldo1,avdd_pll*";
435*724ba675SRob Herring					regulator-min-microvolt = <1100000>;
436*724ba675SRob Herring					regulator-max-microvolt = <1100000>;
437*724ba675SRob Herring					regulator-always-on;
438*724ba675SRob Herring				};
439*724ba675SRob Herring
440*724ba675SRob Herring				rtc_vdd: ldo2 {
441*724ba675SRob Herring					regulator-name = "vdd_ldo2,vdd_rtc";
442*724ba675SRob Herring					regulator-min-microvolt = <950000>;
443*724ba675SRob Herring					regulator-max-microvolt = <1300000>;
444*724ba675SRob Herring					regulator-coupled-with = <&vdd_core &vdd_cpu>;
445*724ba675SRob Herring					regulator-coupled-max-spread = <170000 550000>;
446*724ba675SRob Herring					regulator-always-on;
447*724ba675SRob Herring					regulator-boot-on;
448*724ba675SRob Herring
449*724ba675SRob Herring					nvidia,tegra-rtc-regulator;
450*724ba675SRob Herring				};
451*724ba675SRob Herring
452*724ba675SRob Herring				ldo3 {
453*724ba675SRob Herring					regulator-name = "vdd_ldo3,avdd_usb*";
454*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
455*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
456*724ba675SRob Herring					regulator-always-on;
457*724ba675SRob Herring				};
458*724ba675SRob Herring
459*724ba675SRob Herring				ldo4 {
460*724ba675SRob Herring					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
461*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
462*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
463*724ba675SRob Herring					regulator-always-on;
464*724ba675SRob Herring				};
465*724ba675SRob Herring
466*724ba675SRob Herring				ldo5 {
467*724ba675SRob Herring					regulator-name = "vdd_ldo5,vcore_mmc";
468*724ba675SRob Herring					regulator-min-microvolt = <2850000>;
469*724ba675SRob Herring					regulator-max-microvolt = <2850000>;
470*724ba675SRob Herring					regulator-always-on;
471*724ba675SRob Herring				};
472*724ba675SRob Herring
473*724ba675SRob Herring				ldo6 {
474*724ba675SRob Herring					regulator-name = "vdd_ldo6,avdd_vdac";
475*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
476*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
477*724ba675SRob Herring				};
478*724ba675SRob Herring
479*724ba675SRob Herring				hdmi_vdd_reg: ldo7 {
480*724ba675SRob Herring					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
481*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
482*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
483*724ba675SRob Herring				};
484*724ba675SRob Herring
485*724ba675SRob Herring				hdmi_pll_reg: ldo8 {
486*724ba675SRob Herring					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
487*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
488*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
489*724ba675SRob Herring				};
490*724ba675SRob Herring
491*724ba675SRob Herring				ldo9 {
492*724ba675SRob Herring					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
493*724ba675SRob Herring					regulator-min-microvolt = <2850000>;
494*724ba675SRob Herring					regulator-max-microvolt = <2850000>;
495*724ba675SRob Herring					regulator-always-on;
496*724ba675SRob Herring				};
497*724ba675SRob Herring
498*724ba675SRob Herring				ldo_rtc {
499*724ba675SRob Herring					regulator-name = "vdd_rtc_out,vdd_cell";
500*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
501*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
502*724ba675SRob Herring					regulator-always-on;
503*724ba675SRob Herring				};
504*724ba675SRob Herring			};
505*724ba675SRob Herring		};
506*724ba675SRob Herring
507*724ba675SRob Herring		nct1008: temperature-sensor@4c {
508*724ba675SRob Herring			compatible = "onnn,nct1008";
509*724ba675SRob Herring			reg = <0x4c>;
510*724ba675SRob Herring			#thermal-sensor-cells = <1>;
511*724ba675SRob Herring		};
512*724ba675SRob Herring	};
513*724ba675SRob Herring
514*724ba675SRob Herring	pmc@7000e400 {
515*724ba675SRob Herring		nvidia,invert-interrupt;
516*724ba675SRob Herring		nvidia,suspend-mode = <1>;
517*724ba675SRob Herring		nvidia,cpu-pwr-good-time = <2000>;
518*724ba675SRob Herring		nvidia,cpu-pwr-off-time = <100>;
519*724ba675SRob Herring		nvidia,core-pwr-good-time = <3845 3845>;
520*724ba675SRob Herring		nvidia,core-pwr-off-time = <458>;
521*724ba675SRob Herring		nvidia,sys-clock-req-active-high;
522*724ba675SRob Herring		core-supply = <&vdd_core>;
523*724ba675SRob Herring	};
524*724ba675SRob Herring
525*724ba675SRob Herring	usb@c5000000 {
526*724ba675SRob Herring		status = "okay";
527*724ba675SRob Herring	};
528*724ba675SRob Herring
529*724ba675SRob Herring	usb-phy@c5000000 {
530*724ba675SRob Herring		status = "okay";
531*724ba675SRob Herring	};
532*724ba675SRob Herring
533*724ba675SRob Herring	usb@c5004000 {
534*724ba675SRob Herring		status = "okay";
535*724ba675SRob Herring	};
536*724ba675SRob Herring
537*724ba675SRob Herring	usb-phy@c5004000 {
538*724ba675SRob Herring		status = "okay";
539*724ba675SRob Herring		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
540*724ba675SRob Herring			GPIO_ACTIVE_LOW>;
541*724ba675SRob Herring	};
542*724ba675SRob Herring
543*724ba675SRob Herring	usb@c5008000 {
544*724ba675SRob Herring		status = "okay";
545*724ba675SRob Herring	};
546*724ba675SRob Herring
547*724ba675SRob Herring	usb-phy@c5008000 {
548*724ba675SRob Herring		status = "okay";
549*724ba675SRob Herring	};
550*724ba675SRob Herring
551*724ba675SRob Herring	mmc@c8000000 {
552*724ba675SRob Herring		status = "okay";
553*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
554*724ba675SRob Herring		bus-width = <4>;
555*724ba675SRob Herring		keep-power-in-suspend;
556*724ba675SRob Herring	};
557*724ba675SRob Herring
558*724ba675SRob Herring	mmc@c8000400 {
559*724ba675SRob Herring		status = "okay";
560*724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
561*724ba675SRob Herring		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
562*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
563*724ba675SRob Herring		bus-width = <4>;
564*724ba675SRob Herring	};
565*724ba675SRob Herring
566*724ba675SRob Herring	mmc@c8000600 {
567*724ba675SRob Herring		status = "okay";
568*724ba675SRob Herring		bus-width = <8>;
569*724ba675SRob Herring		non-removable;
570*724ba675SRob Herring	};
571*724ba675SRob Herring
572*724ba675SRob Herring	backlight: backlight {
573*724ba675SRob Herring		compatible = "pwm-backlight";
574*724ba675SRob Herring
575*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
576*724ba675SRob Herring		power-supply = <&vdd_bl_reg>;
577*724ba675SRob Herring		pwms = <&pwm 2 5000000>;
578*724ba675SRob Herring
579*724ba675SRob Herring		brightness-levels = <0 4 8 16 32 64 128 255>;
580*724ba675SRob Herring		default-brightness-level = <6>;
581*724ba675SRob Herring	};
582*724ba675SRob Herring
583*724ba675SRob Herring	clk32k_in: clock-32k {
584*724ba675SRob Herring		compatible = "fixed-clock";
585*724ba675SRob Herring		clock-frequency = <32768>;
586*724ba675SRob Herring		#clock-cells = <0>;
587*724ba675SRob Herring	};
588*724ba675SRob Herring
589*724ba675SRob Herring	cpus {
590*724ba675SRob Herring		cpu0: cpu@0 {
591*724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
592*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
593*724ba675SRob Herring			#cooling-cells = <2>;
594*724ba675SRob Herring		};
595*724ba675SRob Herring
596*724ba675SRob Herring		cpu1: cpu@1 {
597*724ba675SRob Herring			cpu-supply = <&vdd_cpu>;
598*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
599*724ba675SRob Herring			#cooling-cells = <2>;
600*724ba675SRob Herring		};
601*724ba675SRob Herring	};
602*724ba675SRob Herring
603*724ba675SRob Herring	gpio-keys {
604*724ba675SRob Herring		compatible = "gpio-keys";
605*724ba675SRob Herring
606*724ba675SRob Herring		key-power {
607*724ba675SRob Herring			label = "Power";
608*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
609*724ba675SRob Herring			linux,code = <KEY_POWER>;
610*724ba675SRob Herring			wakeup-source;
611*724ba675SRob Herring		};
612*724ba675SRob Herring	};
613*724ba675SRob Herring
614*724ba675SRob Herring	i2cmux {
615*724ba675SRob Herring		compatible = "i2c-mux-pinctrl";
616*724ba675SRob Herring		#address-cells = <1>;
617*724ba675SRob Herring		#size-cells = <0>;
618*724ba675SRob Herring
619*724ba675SRob Herring		i2c-parent = <&{/i2c@7000c400}>;
620*724ba675SRob Herring
621*724ba675SRob Herring		pinctrl-names = "ddc", "pta", "idle";
622*724ba675SRob Herring		pinctrl-0 = <&state_i2cmux_ddc>;
623*724ba675SRob Herring		pinctrl-1 = <&state_i2cmux_pta>;
624*724ba675SRob Herring		pinctrl-2 = <&state_i2cmux_idle>;
625*724ba675SRob Herring
626*724ba675SRob Herring		hdmi_ddc: i2c@0 {
627*724ba675SRob Herring			reg = <0>;
628*724ba675SRob Herring			#address-cells = <1>;
629*724ba675SRob Herring			#size-cells = <0>;
630*724ba675SRob Herring		};
631*724ba675SRob Herring
632*724ba675SRob Herring		lvds_ddc: i2c@1 {
633*724ba675SRob Herring			reg = <1>;
634*724ba675SRob Herring			#address-cells = <1>;
635*724ba675SRob Herring			#size-cells = <0>;
636*724ba675SRob Herring		};
637*724ba675SRob Herring	};
638*724ba675SRob Herring
639*724ba675SRob Herring	panel: panel {
640*724ba675SRob Herring		compatible = "chunghwa,claa101wa01a";
641*724ba675SRob Herring
642*724ba675SRob Herring		power-supply = <&vdd_pnl_reg>;
643*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
644*724ba675SRob Herring
645*724ba675SRob Herring		backlight = <&backlight>;
646*724ba675SRob Herring		ddc-i2c-bus = <&lvds_ddc>;
647*724ba675SRob Herring	};
648*724ba675SRob Herring
649*724ba675SRob Herring	vdd_5v0_reg: regulator-5v0 {
650*724ba675SRob Herring		compatible = "regulator-fixed";
651*724ba675SRob Herring		regulator-name = "vdd_5v0";
652*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
653*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
654*724ba675SRob Herring		regulator-always-on;
655*724ba675SRob Herring	};
656*724ba675SRob Herring
657*724ba675SRob Herring	regulator-1v5 {
658*724ba675SRob Herring		compatible = "regulator-fixed";
659*724ba675SRob Herring		regulator-name = "vdd_1v5";
660*724ba675SRob Herring		regulator-min-microvolt = <1500000>;
661*724ba675SRob Herring		regulator-max-microvolt = <1500000>;
662*724ba675SRob Herring		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
663*724ba675SRob Herring	};
664*724ba675SRob Herring
665*724ba675SRob Herring	regulator-1v2 {
666*724ba675SRob Herring		compatible = "regulator-fixed";
667*724ba675SRob Herring		regulator-name = "vdd_1v2";
668*724ba675SRob Herring		regulator-min-microvolt = <1200000>;
669*724ba675SRob Herring		regulator-max-microvolt = <1200000>;
670*724ba675SRob Herring		gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
671*724ba675SRob Herring		enable-active-high;
672*724ba675SRob Herring	};
673*724ba675SRob Herring
674*724ba675SRob Herring	vdd_pnl_reg: regulator-pnl {
675*724ba675SRob Herring		compatible = "regulator-fixed";
676*724ba675SRob Herring		regulator-name = "vdd_pnl";
677*724ba675SRob Herring		regulator-min-microvolt = <2800000>;
678*724ba675SRob Herring		regulator-max-microvolt = <2800000>;
679*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
680*724ba675SRob Herring		enable-active-high;
681*724ba675SRob Herring	};
682*724ba675SRob Herring
683*724ba675SRob Herring	vdd_bl_reg: regulator-bl {
684*724ba675SRob Herring		compatible = "regulator-fixed";
685*724ba675SRob Herring		regulator-name = "vdd_bl";
686*724ba675SRob Herring		regulator-min-microvolt = <2800000>;
687*724ba675SRob Herring		regulator-max-microvolt = <2800000>;
688*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
689*724ba675SRob Herring		enable-active-high;
690*724ba675SRob Herring	};
691*724ba675SRob Herring
692*724ba675SRob Herring	sound {
693*724ba675SRob Herring		compatible = "nvidia,tegra-audio-wm8903-ventana",
694*724ba675SRob Herring			     "nvidia,tegra-audio-wm8903";
695*724ba675SRob Herring		nvidia,model = "NVIDIA Tegra Ventana";
696*724ba675SRob Herring
697*724ba675SRob Herring		nvidia,audio-routing =
698*724ba675SRob Herring			"Headphone Jack", "HPOUTR",
699*724ba675SRob Herring			"Headphone Jack", "HPOUTL",
700*724ba675SRob Herring			"Int Spk", "ROP",
701*724ba675SRob Herring			"Int Spk", "RON",
702*724ba675SRob Herring			"Int Spk", "LOP",
703*724ba675SRob Herring			"Int Spk", "LON",
704*724ba675SRob Herring			"Mic Jack", "MICBIAS",
705*724ba675SRob Herring			"IN1L", "Mic Jack";
706*724ba675SRob Herring
707*724ba675SRob Herring		nvidia,i2s-controller = <&tegra_i2s1>;
708*724ba675SRob Herring		nvidia,audio-codec = <&wm8903>;
709*724ba675SRob Herring
710*724ba675SRob Herring		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
711*724ba675SRob Herring		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
712*724ba675SRob Herring		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
713*724ba675SRob Herring			GPIO_ACTIVE_HIGH>;
714*724ba675SRob Herring		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
715*724ba675SRob Herring			GPIO_ACTIVE_HIGH>;
716*724ba675SRob Herring
717*724ba675SRob Herring		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
718*724ba675SRob Herring			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
719*724ba675SRob Herring			 <&tegra_car TEGRA20_CLK_CDEV1>;
720*724ba675SRob Herring		clock-names = "pll_a", "pll_a_out0", "mclk";
721*724ba675SRob Herring	};
722*724ba675SRob Herring
723*724ba675SRob Herring	thermal-zones {
724*724ba675SRob Herring		cpu-thermal {
725*724ba675SRob Herring			polling-delay-passive = <1000>; /* milliseconds */
726*724ba675SRob Herring			polling-delay = <5000>; /* milliseconds */
727*724ba675SRob Herring
728*724ba675SRob Herring			thermal-sensors = <&nct1008 1>;
729*724ba675SRob Herring
730*724ba675SRob Herring			trips {
731*724ba675SRob Herring				trip0: cpu-alert0 {
732*724ba675SRob Herring					/* start throttling at 50C */
733*724ba675SRob Herring					temperature = <50000>;
734*724ba675SRob Herring					hysteresis = <200>;
735*724ba675SRob Herring					type = "passive";
736*724ba675SRob Herring				};
737*724ba675SRob Herring
738*724ba675SRob Herring				trip1: cpu-crit {
739*724ba675SRob Herring					/* shut down at 60C */
740*724ba675SRob Herring					temperature = <60000>;
741*724ba675SRob Herring					hysteresis = <2000>;
742*724ba675SRob Herring					type = "critical";
743*724ba675SRob Herring				};
744*724ba675SRob Herring			};
745*724ba675SRob Herring
746*724ba675SRob Herring			cooling-maps {
747*724ba675SRob Herring				map0 {
748*724ba675SRob Herring					trip = <&trip0>;
749*724ba675SRob Herring					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
750*724ba675SRob Herring							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
751*724ba675SRob Herring				};
752*724ba675SRob Herring			};
753*724ba675SRob Herring		};
754*724ba675SRob Herring	};
755*724ba675SRob Herring};
756