1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/input/input.h> 5*724ba675SRob Herring#include "tegra20.dtsi" 6*724ba675SRob Herring#include "tegra20-cpu-opp.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Compulab TrimSlice board"; 10*724ba675SRob Herring compatible = "compulab,trimslice", "nvidia,tegra20"; 11*724ba675SRob Herring 12*724ba675SRob Herring aliases { 13*724ba675SRob Herring rtc0 = "/i2c@7000c500/rtc@56"; 14*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 15*724ba675SRob Herring serial0 = &uarta; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring chosen { 19*724ba675SRob Herring stdout-path = "serial0:115200n8"; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring memory@0 { 23*724ba675SRob Herring reg = <0x00000000 0x40000000>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring host1x@50000000 { 27*724ba675SRob Herring hdmi@54280000 { 28*724ba675SRob Herring status = "okay"; 29*724ba675SRob Herring 30*724ba675SRob Herring vdd-supply = <&hdmi_vdd_reg>; 31*724ba675SRob Herring pll-supply = <&hdmi_pll_reg>; 32*724ba675SRob Herring 33*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34*724ba675SRob Herring nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 35*724ba675SRob Herring GPIO_ACTIVE_HIGH>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring pinmux@70000014 { 40*724ba675SRob Herring pinctrl-names = "default"; 41*724ba675SRob Herring pinctrl-0 = <&state_default>; 42*724ba675SRob Herring 43*724ba675SRob Herring state_default: pinmux { 44*724ba675SRob Herring ata { 45*724ba675SRob Herring nvidia,pins = "ata"; 46*724ba675SRob Herring nvidia,function = "ide"; 47*724ba675SRob Herring }; 48*724ba675SRob Herring atb { 49*724ba675SRob Herring nvidia,pins = "atb", "gma"; 50*724ba675SRob Herring nvidia,function = "sdio4"; 51*724ba675SRob Herring }; 52*724ba675SRob Herring atc { 53*724ba675SRob Herring nvidia,pins = "atc", "gmb"; 54*724ba675SRob Herring nvidia,function = "nand"; 55*724ba675SRob Herring }; 56*724ba675SRob Herring atd { 57*724ba675SRob Herring nvidia,pins = "atd", "ate", "gme", "pta"; 58*724ba675SRob Herring nvidia,function = "gmi"; 59*724ba675SRob Herring }; 60*724ba675SRob Herring cdev1 { 61*724ba675SRob Herring nvidia,pins = "cdev1"; 62*724ba675SRob Herring nvidia,function = "plla_out"; 63*724ba675SRob Herring }; 64*724ba675SRob Herring cdev2 { 65*724ba675SRob Herring nvidia,pins = "cdev2"; 66*724ba675SRob Herring nvidia,function = "pllp_out4"; 67*724ba675SRob Herring }; 68*724ba675SRob Herring crtp { 69*724ba675SRob Herring nvidia,pins = "crtp"; 70*724ba675SRob Herring nvidia,function = "crt"; 71*724ba675SRob Herring }; 72*724ba675SRob Herring csus { 73*724ba675SRob Herring nvidia,pins = "csus"; 74*724ba675SRob Herring nvidia,function = "vi_sensor_clk"; 75*724ba675SRob Herring }; 76*724ba675SRob Herring dap1 { 77*724ba675SRob Herring nvidia,pins = "dap1"; 78*724ba675SRob Herring nvidia,function = "dap1"; 79*724ba675SRob Herring }; 80*724ba675SRob Herring dap2 { 81*724ba675SRob Herring nvidia,pins = "dap2"; 82*724ba675SRob Herring nvidia,function = "dap2"; 83*724ba675SRob Herring }; 84*724ba675SRob Herring dap3 { 85*724ba675SRob Herring nvidia,pins = "dap3"; 86*724ba675SRob Herring nvidia,function = "dap3"; 87*724ba675SRob Herring }; 88*724ba675SRob Herring dap4 { 89*724ba675SRob Herring nvidia,pins = "dap4"; 90*724ba675SRob Herring nvidia,function = "dap4"; 91*724ba675SRob Herring }; 92*724ba675SRob Herring ddc { 93*724ba675SRob Herring nvidia,pins = "ddc"; 94*724ba675SRob Herring nvidia,function = "i2c2"; 95*724ba675SRob Herring }; 96*724ba675SRob Herring dta { 97*724ba675SRob Herring nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 98*724ba675SRob Herring nvidia,function = "vi"; 99*724ba675SRob Herring }; 100*724ba675SRob Herring dtf { 101*724ba675SRob Herring nvidia,pins = "dtf"; 102*724ba675SRob Herring nvidia,function = "i2c3"; 103*724ba675SRob Herring }; 104*724ba675SRob Herring gmc { 105*724ba675SRob Herring nvidia,pins = "gmc", "gmd"; 106*724ba675SRob Herring nvidia,function = "sflash"; 107*724ba675SRob Herring }; 108*724ba675SRob Herring gpu { 109*724ba675SRob Herring nvidia,pins = "gpu"; 110*724ba675SRob Herring nvidia,function = "uarta"; 111*724ba675SRob Herring }; 112*724ba675SRob Herring gpu7 { 113*724ba675SRob Herring nvidia,pins = "gpu7"; 114*724ba675SRob Herring nvidia,function = "rtck"; 115*724ba675SRob Herring }; 116*724ba675SRob Herring gpv { 117*724ba675SRob Herring nvidia,pins = "gpv", "slxa", "slxk"; 118*724ba675SRob Herring nvidia,function = "pcie"; 119*724ba675SRob Herring }; 120*724ba675SRob Herring hdint { 121*724ba675SRob Herring nvidia,pins = "hdint"; 122*724ba675SRob Herring nvidia,function = "hdmi"; 123*724ba675SRob Herring }; 124*724ba675SRob Herring i2cp { 125*724ba675SRob Herring nvidia,pins = "i2cp"; 126*724ba675SRob Herring nvidia,function = "i2cp"; 127*724ba675SRob Herring }; 128*724ba675SRob Herring irrx { 129*724ba675SRob Herring nvidia,pins = "irrx", "irtx"; 130*724ba675SRob Herring nvidia,function = "uartb"; 131*724ba675SRob Herring }; 132*724ba675SRob Herring kbca { 133*724ba675SRob Herring nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 134*724ba675SRob Herring "kbce", "kbcf"; 135*724ba675SRob Herring nvidia,function = "kbc"; 136*724ba675SRob Herring }; 137*724ba675SRob Herring lcsn { 138*724ba675SRob Herring nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 139*724ba675SRob Herring "ld3", "ld4", "ld5", "ld6", "ld7", 140*724ba675SRob Herring "ld8", "ld9", "ld10", "ld11", "ld12", 141*724ba675SRob Herring "ld13", "ld14", "ld15", "ld16", "ld17", 142*724ba675SRob Herring "ldc", "ldi", "lhp0", "lhp1", "lhp2", 143*724ba675SRob Herring "lhs", "lm0", "lm1", "lpp", "lpw0", 144*724ba675SRob Herring "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 145*724ba675SRob Herring "lsda", "lsdi", "lspi", "lvp0", "lvp1", 146*724ba675SRob Herring "lvs"; 147*724ba675SRob Herring nvidia,function = "displaya"; 148*724ba675SRob Herring }; 149*724ba675SRob Herring owc { 150*724ba675SRob Herring nvidia,pins = "owc", "uac"; 151*724ba675SRob Herring nvidia,function = "rsvd2"; 152*724ba675SRob Herring }; 153*724ba675SRob Herring pmc { 154*724ba675SRob Herring nvidia,pins = "pmc"; 155*724ba675SRob Herring nvidia,function = "pwr_on"; 156*724ba675SRob Herring }; 157*724ba675SRob Herring rm { 158*724ba675SRob Herring nvidia,pins = "rm"; 159*724ba675SRob Herring nvidia,function = "i2c1"; 160*724ba675SRob Herring }; 161*724ba675SRob Herring sdb { 162*724ba675SRob Herring nvidia,pins = "sdb", "sdc", "sdd"; 163*724ba675SRob Herring nvidia,function = "pwm"; 164*724ba675SRob Herring }; 165*724ba675SRob Herring sdio1 { 166*724ba675SRob Herring nvidia,pins = "sdio1"; 167*724ba675SRob Herring nvidia,function = "sdio1"; 168*724ba675SRob Herring }; 169*724ba675SRob Herring slxc { 170*724ba675SRob Herring nvidia,pins = "slxc", "slxd"; 171*724ba675SRob Herring nvidia,function = "sdio3"; 172*724ba675SRob Herring }; 173*724ba675SRob Herring spdi { 174*724ba675SRob Herring nvidia,pins = "spdi", "spdo"; 175*724ba675SRob Herring nvidia,function = "spdif"; 176*724ba675SRob Herring }; 177*724ba675SRob Herring spia { 178*724ba675SRob Herring nvidia,pins = "spia", "spib", "spic"; 179*724ba675SRob Herring nvidia,function = "spi2"; 180*724ba675SRob Herring }; 181*724ba675SRob Herring spid { 182*724ba675SRob Herring nvidia,pins = "spid", "spie", "spif"; 183*724ba675SRob Herring nvidia,function = "spi1"; 184*724ba675SRob Herring }; 185*724ba675SRob Herring spig { 186*724ba675SRob Herring nvidia,pins = "spig", "spih"; 187*724ba675SRob Herring nvidia,function = "spi2_alt"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring uaa { 190*724ba675SRob Herring nvidia,pins = "uaa", "uab", "uda"; 191*724ba675SRob Herring nvidia,function = "ulpi"; 192*724ba675SRob Herring }; 193*724ba675SRob Herring uad { 194*724ba675SRob Herring nvidia,pins = "uad"; 195*724ba675SRob Herring nvidia,function = "irda"; 196*724ba675SRob Herring }; 197*724ba675SRob Herring uca { 198*724ba675SRob Herring nvidia,pins = "uca", "ucb"; 199*724ba675SRob Herring nvidia,function = "uartc"; 200*724ba675SRob Herring }; 201*724ba675SRob Herring conf_ata { 202*724ba675SRob Herring nvidia,pins = "ata", "atc", "atd", "ate", 203*724ba675SRob Herring "crtp", "dap2", "dap3", "dap4", "dta", 204*724ba675SRob Herring "dtb", "dtc", "dtd", "dte", "gmb", 205*724ba675SRob Herring "gme", "i2cp", "pta", "slxc", "slxd", 206*724ba675SRob Herring "spdi", "spdo", "uda"; 207*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 209*724ba675SRob Herring }; 210*724ba675SRob Herring conf_atb { 211*724ba675SRob Herring nvidia,pins = "atb", "cdev1", "cdev2", "dap1", 212*724ba675SRob Herring "gma", "gmc", "gmd", "gpu", "gpu7", 213*724ba675SRob Herring "gpv", "sdio1", "slxa", "slxk", "uac"; 214*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 216*724ba675SRob Herring }; 217*724ba675SRob Herring conf_ck32 { 218*724ba675SRob Herring nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 219*724ba675SRob Herring "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 220*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 221*724ba675SRob Herring }; 222*724ba675SRob Herring conf_csus { 223*724ba675SRob Herring nvidia,pins = "csus", "spia", "spib", 224*724ba675SRob Herring "spid", "spif"; 225*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 226*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring conf_ddc { 229*724ba675SRob Herring nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; 230*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 231*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 232*724ba675SRob Herring }; 233*724ba675SRob Herring conf_hdint { 234*724ba675SRob Herring nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 235*724ba675SRob Herring "lpw1", "lsc1", "lsck", "lsda", "lsdi", 236*724ba675SRob Herring "lvp0", "pmc"; 237*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 238*724ba675SRob Herring }; 239*724ba675SRob Herring conf_irrx { 240*724ba675SRob Herring nvidia,pins = "irrx", "irtx", "kbca", "kbcb", 241*724ba675SRob Herring "kbcc", "kbcd", "kbce", "kbcf", "owc", 242*724ba675SRob Herring "spic", "spie", "spig", "spih", "uaa", 243*724ba675SRob Herring "uab", "uad", "uca", "ucb"; 244*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 245*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 246*724ba675SRob Herring }; 247*724ba675SRob Herring conf_lc { 248*724ba675SRob Herring nvidia,pins = "lc", "ls"; 249*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 250*724ba675SRob Herring }; 251*724ba675SRob Herring conf_ld0 { 252*724ba675SRob Herring nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 253*724ba675SRob Herring "ld5", "ld6", "ld7", "ld8", "ld9", 254*724ba675SRob Herring "ld10", "ld11", "ld12", "ld13", "ld14", 255*724ba675SRob Herring "ld15", "ld16", "ld17", "ldi", "lhp0", 256*724ba675SRob Herring "lhp1", "lhp2", "lhs", "lm0", "lpp", 257*724ba675SRob Herring "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 258*724ba675SRob Herring "lvs", "sdb"; 259*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 260*724ba675SRob Herring }; 261*724ba675SRob Herring conf_ld17_0 { 262*724ba675SRob Herring nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 263*724ba675SRob Herring "ld23_22"; 264*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 265*724ba675SRob Herring }; 266*724ba675SRob Herring conf_spif { 267*724ba675SRob Herring nvidia,pins = "spif"; 268*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 269*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*724ba675SRob Herring }; 271*724ba675SRob Herring }; 272*724ba675SRob Herring }; 273*724ba675SRob Herring 274*724ba675SRob Herring i2s@70002800 { 275*724ba675SRob Herring status = "okay"; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring serial@70006000 { 279*724ba675SRob Herring status = "okay"; 280*724ba675SRob Herring }; 281*724ba675SRob Herring 282*724ba675SRob Herring dvi_ddc: i2c@7000c000 { 283*724ba675SRob Herring status = "okay"; 284*724ba675SRob Herring clock-frequency = <100000>; 285*724ba675SRob Herring }; 286*724ba675SRob Herring 287*724ba675SRob Herring spi@7000c380 { 288*724ba675SRob Herring status = "okay"; 289*724ba675SRob Herring spi-max-frequency = <48000000>; 290*724ba675SRob Herring 291*724ba675SRob Herring flash@0 { 292*724ba675SRob Herring compatible = "winbond,w25q80bl", "jedec,spi-nor"; 293*724ba675SRob Herring reg = <0>; 294*724ba675SRob Herring spi-max-frequency = <48000000>; 295*724ba675SRob Herring }; 296*724ba675SRob Herring }; 297*724ba675SRob Herring 298*724ba675SRob Herring hdmi_ddc: i2c@7000c400 { 299*724ba675SRob Herring status = "okay"; 300*724ba675SRob Herring clock-frequency = <100000>; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring i2c@7000c500 { 304*724ba675SRob Herring status = "okay"; 305*724ba675SRob Herring clock-frequency = <400000>; 306*724ba675SRob Herring 307*724ba675SRob Herring codec: codec@1a { 308*724ba675SRob Herring compatible = "ti,tlv320aic23"; 309*724ba675SRob Herring reg = <0x1a>; 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring rtc@56 { 313*724ba675SRob Herring compatible = "emmicro,em3027"; 314*724ba675SRob Herring reg = <0x56>; 315*724ba675SRob Herring }; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring pmc@7000e400 { 319*724ba675SRob Herring nvidia,suspend-mode = <1>; 320*724ba675SRob Herring nvidia,cpu-pwr-good-time = <5000>; 321*724ba675SRob Herring nvidia,cpu-pwr-off-time = <5000>; 322*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 323*724ba675SRob Herring nvidia,core-pwr-off-time = <3875>; 324*724ba675SRob Herring nvidia,sys-clock-req-active-high; 325*724ba675SRob Herring core-supply = <&vdd_core>; 326*724ba675SRob Herring }; 327*724ba675SRob Herring 328*724ba675SRob Herring pcie@80003000 { 329*724ba675SRob Herring status = "okay"; 330*724ba675SRob Herring 331*724ba675SRob Herring avdd-pex-supply = <&pci_vdd_reg>; 332*724ba675SRob Herring vdd-pex-supply = <&pci_vdd_reg>; 333*724ba675SRob Herring avdd-pex-pll-supply = <&pci_vdd_reg>; 334*724ba675SRob Herring avdd-plle-supply = <&pci_vdd_reg>; 335*724ba675SRob Herring vddio-pex-clk-supply = <&pci_clk_reg>; 336*724ba675SRob Herring 337*724ba675SRob Herring pci@1,0 { 338*724ba675SRob Herring status = "okay"; 339*724ba675SRob Herring }; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring usb@c5000000 { 343*724ba675SRob Herring status = "okay"; 344*724ba675SRob Herring }; 345*724ba675SRob Herring 346*724ba675SRob Herring usb-phy@c5000000 { 347*724ba675SRob Herring status = "okay"; 348*724ba675SRob Herring vbus-supply = <&vbus_reg>; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring usb@c5004000 { 352*724ba675SRob Herring status = "okay"; 353*724ba675SRob Herring }; 354*724ba675SRob Herring 355*724ba675SRob Herring usb-phy@c5004000 { 356*724ba675SRob Herring status = "okay"; 357*724ba675SRob Herring nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 358*724ba675SRob Herring GPIO_ACTIVE_LOW>; 359*724ba675SRob Herring }; 360*724ba675SRob Herring 361*724ba675SRob Herring usb@c5008000 { 362*724ba675SRob Herring status = "okay"; 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring usb-phy@c5008000 { 366*724ba675SRob Herring status = "okay"; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring mmc@c8000000 { 370*724ba675SRob Herring status = "okay"; 371*724ba675SRob Herring broken-cd; 372*724ba675SRob Herring bus-width = <4>; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring mmc@c8000600 { 376*724ba675SRob Herring status = "okay"; 377*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; 378*724ba675SRob Herring wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 379*724ba675SRob Herring bus-width = <4>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring clk32k_in: clock-32k { 383*724ba675SRob Herring compatible = "fixed-clock"; 384*724ba675SRob Herring clock-frequency = <32768>; 385*724ba675SRob Herring #clock-cells = <0>; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring cpus { 389*724ba675SRob Herring cpu0: cpu@0 { 390*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring cpu@1 { 394*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 395*724ba675SRob Herring }; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring gpio-keys { 399*724ba675SRob Herring compatible = "gpio-keys"; 400*724ba675SRob Herring 401*724ba675SRob Herring key-power { 402*724ba675SRob Herring label = "Power"; 403*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 404*724ba675SRob Herring linux,code = <KEY_POWER>; 405*724ba675SRob Herring wakeup-source; 406*724ba675SRob Herring }; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring poweroff { 410*724ba675SRob Herring compatible = "gpio-poweroff"; 411*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 412*724ba675SRob Herring }; 413*724ba675SRob Herring 414*724ba675SRob Herring hdmi_vdd_reg: regulator-hdmi { 415*724ba675SRob Herring compatible = "regulator-fixed"; 416*724ba675SRob Herring regulator-name = "avdd_hdmi"; 417*724ba675SRob Herring regulator-min-microvolt = <3300000>; 418*724ba675SRob Herring regulator-max-microvolt = <3300000>; 419*724ba675SRob Herring regulator-always-on; 420*724ba675SRob Herring }; 421*724ba675SRob Herring 422*724ba675SRob Herring hdmi_pll_reg: regulator-hdmipll { 423*724ba675SRob Herring compatible = "regulator-fixed"; 424*724ba675SRob Herring regulator-name = "avdd_hdmi_pll"; 425*724ba675SRob Herring regulator-min-microvolt = <1800000>; 426*724ba675SRob Herring regulator-max-microvolt = <1800000>; 427*724ba675SRob Herring regulator-always-on; 428*724ba675SRob Herring }; 429*724ba675SRob Herring 430*724ba675SRob Herring vbus_reg: regulator-vbus { 431*724ba675SRob Herring compatible = "regulator-fixed"; 432*724ba675SRob Herring regulator-name = "usb1_vbus"; 433*724ba675SRob Herring regulator-min-microvolt = <5000000>; 434*724ba675SRob Herring regulator-max-microvolt = <5000000>; 435*724ba675SRob Herring enable-active-high; 436*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(V, 2) 0>; 437*724ba675SRob Herring regulator-always-on; 438*724ba675SRob Herring regulator-boot-on; 439*724ba675SRob Herring }; 440*724ba675SRob Herring 441*724ba675SRob Herring pci_clk_reg: regulator-pciclk { 442*724ba675SRob Herring compatible = "regulator-fixed"; 443*724ba675SRob Herring regulator-name = "pci_clk"; 444*724ba675SRob Herring regulator-min-microvolt = <3300000>; 445*724ba675SRob Herring regulator-max-microvolt = <3300000>; 446*724ba675SRob Herring regulator-always-on; 447*724ba675SRob Herring }; 448*724ba675SRob Herring 449*724ba675SRob Herring pci_vdd_reg: regulator-pcivdd { 450*724ba675SRob Herring compatible = "regulator-fixed"; 451*724ba675SRob Herring regulator-name = "pci_vdd"; 452*724ba675SRob Herring regulator-min-microvolt = <1050000>; 453*724ba675SRob Herring regulator-max-microvolt = <1050000>; 454*724ba675SRob Herring regulator-always-on; 455*724ba675SRob Herring }; 456*724ba675SRob Herring 457*724ba675SRob Herring vdd_core: regulator-core { 458*724ba675SRob Herring compatible = "regulator-fixed"; 459*724ba675SRob Herring regulator-name = "vdd_core"; 460*724ba675SRob Herring regulator-min-microvolt = <1300000>; 461*724ba675SRob Herring regulator-max-microvolt = <1300000>; 462*724ba675SRob Herring regulator-always-on; 463*724ba675SRob Herring }; 464*724ba675SRob Herring 465*724ba675SRob Herring sound { 466*724ba675SRob Herring compatible = "nvidia,tegra-audio-trimslice"; 467*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 468*724ba675SRob Herring nvidia,audio-codec = <&codec>; 469*724ba675SRob Herring 470*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 471*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 472*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CDEV1>; 473*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 474*724ba675SRob Herring }; 475*724ba675SRob Herring}; 476