xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra20-paz00.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/dts-v1/;
3*724ba675SRob Herring
4*724ba675SRob Herring#include <dt-bindings/input/input.h>
5*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h>
6*724ba675SRob Herring
7*724ba675SRob Herring#include "tegra20.dtsi"
8*724ba675SRob Herring#include "tegra20-cpu-opp.dtsi"
9*724ba675SRob Herring#include "tegra20-cpu-opp-microvolt.dtsi"
10*724ba675SRob Herring
11*724ba675SRob Herring/ {
12*724ba675SRob Herring	model = "Toshiba AC100 / Dynabook AZ";
13*724ba675SRob Herring	compatible = "compal,paz00", "nvidia,tegra20";
14*724ba675SRob Herring
15*724ba675SRob Herring	aliases {
16*724ba675SRob Herring		mmc0 = &sdmmc4; /* eMMC */
17*724ba675SRob Herring		mmc1 = &sdmmc1; /* MicroSD */
18*724ba675SRob Herring		rtc0 = "/i2c@7000d000/tps6586x@34";
19*724ba675SRob Herring		rtc1 = "/rtc@7000e000";
20*724ba675SRob Herring		serial0 = &uarta;
21*724ba675SRob Herring		serial1 = &uartc;
22*724ba675SRob Herring	};
23*724ba675SRob Herring
24*724ba675SRob Herring	chosen {
25*724ba675SRob Herring		stdout-path = "serial0:115200n8";
26*724ba675SRob Herring	};
27*724ba675SRob Herring
28*724ba675SRob Herring	memory@0 {
29*724ba675SRob Herring		reg = <0x00000000 0x20000000>;
30*724ba675SRob Herring	};
31*724ba675SRob Herring
32*724ba675SRob Herring	host1x@50000000 {
33*724ba675SRob Herring		dc@54200000 {
34*724ba675SRob Herring			rgb {
35*724ba675SRob Herring				status = "okay";
36*724ba675SRob Herring
37*724ba675SRob Herring				nvidia,panel = <&panel>;
38*724ba675SRob Herring			};
39*724ba675SRob Herring		};
40*724ba675SRob Herring
41*724ba675SRob Herring		hdmi@54280000 {
42*724ba675SRob Herring			status = "okay";
43*724ba675SRob Herring
44*724ba675SRob Herring			vdd-supply = <&hdmi_vdd_reg>;
45*724ba675SRob Herring			pll-supply = <&hdmi_pll_reg>;
46*724ba675SRob Herring
47*724ba675SRob Herring			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
48*724ba675SRob Herring			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
49*724ba675SRob Herring				GPIO_ACTIVE_HIGH>;
50*724ba675SRob Herring		};
51*724ba675SRob Herring	};
52*724ba675SRob Herring
53*724ba675SRob Herring	pinmux@70000014 {
54*724ba675SRob Herring		pinctrl-names = "default";
55*724ba675SRob Herring		pinctrl-0 = <&state_default>;
56*724ba675SRob Herring
57*724ba675SRob Herring		state_default: pinmux {
58*724ba675SRob Herring			ata {
59*724ba675SRob Herring				nvidia,pins = "ata", "atc", "atd", "ate",
60*724ba675SRob Herring					"dap2", "gmb", "gmc", "gmd", "spia",
61*724ba675SRob Herring					"spib", "spic", "spid", "spie";
62*724ba675SRob Herring				nvidia,function = "gmi";
63*724ba675SRob Herring			};
64*724ba675SRob Herring			atb {
65*724ba675SRob Herring				nvidia,pins = "atb", "gma", "gme";
66*724ba675SRob Herring				nvidia,function = "sdio4";
67*724ba675SRob Herring			};
68*724ba675SRob Herring			cdev1 {
69*724ba675SRob Herring				nvidia,pins = "cdev1";
70*724ba675SRob Herring				nvidia,function = "plla_out";
71*724ba675SRob Herring			};
72*724ba675SRob Herring			cdev2 {
73*724ba675SRob Herring				nvidia,pins = "cdev2";
74*724ba675SRob Herring				nvidia,function = "pllp_out4";
75*724ba675SRob Herring			};
76*724ba675SRob Herring			crtp {
77*724ba675SRob Herring				nvidia,pins = "crtp";
78*724ba675SRob Herring				nvidia,function = "crt";
79*724ba675SRob Herring			};
80*724ba675SRob Herring			csus {
81*724ba675SRob Herring				nvidia,pins = "csus";
82*724ba675SRob Herring				nvidia,function = "pllc_out1";
83*724ba675SRob Herring			};
84*724ba675SRob Herring			dap1 {
85*724ba675SRob Herring				nvidia,pins = "dap1";
86*724ba675SRob Herring				nvidia,function = "dap1";
87*724ba675SRob Herring			};
88*724ba675SRob Herring			dap3 {
89*724ba675SRob Herring				nvidia,pins = "dap3";
90*724ba675SRob Herring				nvidia,function = "dap3";
91*724ba675SRob Herring			};
92*724ba675SRob Herring			dap4 {
93*724ba675SRob Herring				nvidia,pins = "dap4";
94*724ba675SRob Herring				nvidia,function = "dap4";
95*724ba675SRob Herring			};
96*724ba675SRob Herring			ddc {
97*724ba675SRob Herring				nvidia,pins = "ddc";
98*724ba675SRob Herring				nvidia,function = "i2c2";
99*724ba675SRob Herring			};
100*724ba675SRob Herring			dta {
101*724ba675SRob Herring				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
102*724ba675SRob Herring				nvidia,function = "rsvd1";
103*724ba675SRob Herring			};
104*724ba675SRob Herring			dtf {
105*724ba675SRob Herring				nvidia,pins = "dtf";
106*724ba675SRob Herring				nvidia,function = "i2c3";
107*724ba675SRob Herring			};
108*724ba675SRob Herring			gpu {
109*724ba675SRob Herring				nvidia,pins = "gpu", "sdb", "sdd";
110*724ba675SRob Herring				nvidia,function = "pwm";
111*724ba675SRob Herring			};
112*724ba675SRob Herring			gpu7 {
113*724ba675SRob Herring				nvidia,pins = "gpu7";
114*724ba675SRob Herring				nvidia,function = "rtck";
115*724ba675SRob Herring			};
116*724ba675SRob Herring			gpv {
117*724ba675SRob Herring				nvidia,pins = "gpv", "slxa", "slxk";
118*724ba675SRob Herring				nvidia,function = "pcie";
119*724ba675SRob Herring			};
120*724ba675SRob Herring			hdint {
121*724ba675SRob Herring				nvidia,pins = "hdint", "pta";
122*724ba675SRob Herring				nvidia,function = "hdmi";
123*724ba675SRob Herring			};
124*724ba675SRob Herring			i2cp {
125*724ba675SRob Herring				nvidia,pins = "i2cp";
126*724ba675SRob Herring				nvidia,function = "i2cp";
127*724ba675SRob Herring			};
128*724ba675SRob Herring			irrx {
129*724ba675SRob Herring				nvidia,pins = "irrx", "irtx";
130*724ba675SRob Herring				nvidia,function = "uarta";
131*724ba675SRob Herring			};
132*724ba675SRob Herring			kbca {
133*724ba675SRob Herring				nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
134*724ba675SRob Herring				nvidia,function = "kbc";
135*724ba675SRob Herring			};
136*724ba675SRob Herring			kbcb {
137*724ba675SRob Herring				nvidia,pins = "kbcb", "kbcd";
138*724ba675SRob Herring				nvidia,function = "sdio2";
139*724ba675SRob Herring			};
140*724ba675SRob Herring			lcsn {
141*724ba675SRob Herring				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
142*724ba675SRob Herring					"ld3", "ld4", "ld5", "ld6", "ld7",
143*724ba675SRob Herring					"ld8", "ld9", "ld10", "ld11", "ld12",
144*724ba675SRob Herring					"ld13", "ld14", "ld15", "ld16", "ld17",
145*724ba675SRob Herring					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
146*724ba675SRob Herring					"lhs", "lm0", "lm1", "lpp", "lpw0",
147*724ba675SRob Herring					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
148*724ba675SRob Herring					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
149*724ba675SRob Herring					"lvs";
150*724ba675SRob Herring				nvidia,function = "displaya";
151*724ba675SRob Herring			};
152*724ba675SRob Herring			owc {
153*724ba675SRob Herring				nvidia,pins = "owc";
154*724ba675SRob Herring				nvidia,function = "owr";
155*724ba675SRob Herring			};
156*724ba675SRob Herring			pmc {
157*724ba675SRob Herring				nvidia,pins = "pmc";
158*724ba675SRob Herring				nvidia,function = "pwr_on";
159*724ba675SRob Herring			};
160*724ba675SRob Herring			rm {
161*724ba675SRob Herring				nvidia,pins = "rm";
162*724ba675SRob Herring				nvidia,function = "i2c1";
163*724ba675SRob Herring			};
164*724ba675SRob Herring			sdc {
165*724ba675SRob Herring				nvidia,pins = "sdc";
166*724ba675SRob Herring				nvidia,function = "twc";
167*724ba675SRob Herring			};
168*724ba675SRob Herring			sdio1 {
169*724ba675SRob Herring				nvidia,pins = "sdio1";
170*724ba675SRob Herring				nvidia,function = "sdio1";
171*724ba675SRob Herring			};
172*724ba675SRob Herring			slxc {
173*724ba675SRob Herring				nvidia,pins = "slxc", "slxd";
174*724ba675SRob Herring				nvidia,function = "spi4";
175*724ba675SRob Herring			};
176*724ba675SRob Herring			spdi {
177*724ba675SRob Herring				nvidia,pins = "spdi", "spdo";
178*724ba675SRob Herring				nvidia,function = "rsvd2";
179*724ba675SRob Herring			};
180*724ba675SRob Herring			spif {
181*724ba675SRob Herring				nvidia,pins = "spif", "uac";
182*724ba675SRob Herring				nvidia,function = "rsvd4";
183*724ba675SRob Herring			};
184*724ba675SRob Herring			spig {
185*724ba675SRob Herring				nvidia,pins = "spig", "spih";
186*724ba675SRob Herring				nvidia,function = "spi2_alt";
187*724ba675SRob Herring			};
188*724ba675SRob Herring			uaa {
189*724ba675SRob Herring				nvidia,pins = "uaa", "uab", "uda";
190*724ba675SRob Herring				nvidia,function = "ulpi";
191*724ba675SRob Herring			};
192*724ba675SRob Herring			uad {
193*724ba675SRob Herring				nvidia,pins = "uad";
194*724ba675SRob Herring				nvidia,function = "spdif";
195*724ba675SRob Herring			};
196*724ba675SRob Herring			uca {
197*724ba675SRob Herring				nvidia,pins = "uca", "ucb";
198*724ba675SRob Herring				nvidia,function = "uartc";
199*724ba675SRob Herring			};
200*724ba675SRob Herring			conf_ata {
201*724ba675SRob Herring				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
202*724ba675SRob Herring					"cdev1", "cdev2", "dap1", "dap2", "dtf",
203*724ba675SRob Herring					"gma", "gmb", "gmc", "gmd", "gme",
204*724ba675SRob Herring					"gpu", "gpu7", "gpv", "i2cp", "pta",
205*724ba675SRob Herring					"rm", "sdio1", "slxk", "spdo", "uac",
206*724ba675SRob Herring					"uda";
207*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
209*724ba675SRob Herring			};
210*724ba675SRob Herring			conf_ck32 {
211*724ba675SRob Herring				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
212*724ba675SRob Herring					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
213*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214*724ba675SRob Herring			};
215*724ba675SRob Herring			conf_crtp {
216*724ba675SRob Herring				nvidia,pins = "crtp", "dap3", "dap4", "dtb",
217*724ba675SRob Herring					"dtc", "dte", "slxa", "slxc", "slxd",
218*724ba675SRob Herring					"spdi";
219*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
221*724ba675SRob Herring			};
222*724ba675SRob Herring			conf_csus {
223*724ba675SRob Herring				nvidia,pins = "csus", "spia", "spib", "spid",
224*724ba675SRob Herring					"spif";
225*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
226*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
227*724ba675SRob Herring			};
228*724ba675SRob Herring			conf_ddc {
229*724ba675SRob Herring				nvidia,pins = "ddc", "irrx", "irtx", "kbca",
230*724ba675SRob Herring					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
231*724ba675SRob Herring					"spic", "spig", "uaa", "uab";
232*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
233*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
234*724ba675SRob Herring			};
235*724ba675SRob Herring			conf_dta {
236*724ba675SRob Herring				nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
237*724ba675SRob Herring					"spie", "spih", "uad", "uca", "ucb";
238*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
239*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
240*724ba675SRob Herring			};
241*724ba675SRob Herring			conf_hdint {
242*724ba675SRob Herring				nvidia,pins = "hdint", "ld0", "ld1", "ld2",
243*724ba675SRob Herring					"ld3", "ld4", "ld5", "ld6", "ld7",
244*724ba675SRob Herring					"ld8", "ld9", "ld10", "ld11", "ld12",
245*724ba675SRob Herring					"ld13", "ld14", "ld15", "ld16", "ld17",
246*724ba675SRob Herring					"ldc", "ldi", "lhs", "lsc0", "lspi",
247*724ba675SRob Herring					"lvs", "pmc";
248*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
249*724ba675SRob Herring			};
250*724ba675SRob Herring			conf_lc {
251*724ba675SRob Herring				nvidia,pins = "lc", "ls";
252*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
253*724ba675SRob Herring			};
254*724ba675SRob Herring			conf_lcsn {
255*724ba675SRob Herring				nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
256*724ba675SRob Herring					"lm0", "lm1", "lpp", "lpw0", "lpw1",
257*724ba675SRob Herring					"lpw2", "lsc1", "lsck", "lsda", "lsdi",
258*724ba675SRob Herring					"lvp0", "lvp1", "sdb";
259*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
260*724ba675SRob Herring			};
261*724ba675SRob Herring			conf_ld17_0 {
262*724ba675SRob Herring				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
263*724ba675SRob Herring					"ld23_22";
264*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
265*724ba675SRob Herring			};
266*724ba675SRob Herring		};
267*724ba675SRob Herring	};
268*724ba675SRob Herring
269*724ba675SRob Herring	spdif@70002400 {
270*724ba675SRob Herring		status = "okay";
271*724ba675SRob Herring
272*724ba675SRob Herring		nvidia,fixed-parent-rate;
273*724ba675SRob Herring	};
274*724ba675SRob Herring
275*724ba675SRob Herring	i2s@70002800 {
276*724ba675SRob Herring		status = "okay";
277*724ba675SRob Herring
278*724ba675SRob Herring		nvidia,fixed-parent-rate;
279*724ba675SRob Herring	};
280*724ba675SRob Herring
281*724ba675SRob Herring	serial@70006000 {
282*724ba675SRob Herring		status = "okay";
283*724ba675SRob Herring	};
284*724ba675SRob Herring
285*724ba675SRob Herring	serial@70006200 {
286*724ba675SRob Herring		status = "okay";
287*724ba675SRob Herring	};
288*724ba675SRob Herring
289*724ba675SRob Herring	pwm: pwm@7000a000 {
290*724ba675SRob Herring		status = "okay";
291*724ba675SRob Herring	};
292*724ba675SRob Herring
293*724ba675SRob Herring	lvds_ddc: i2c@7000c000 {
294*724ba675SRob Herring		status = "okay";
295*724ba675SRob Herring		clock-frequency = <400000>;
296*724ba675SRob Herring
297*724ba675SRob Herring		alc5632: alc5632@1e {
298*724ba675SRob Herring			compatible = "realtek,alc5632";
299*724ba675SRob Herring			reg = <0x1e>;
300*724ba675SRob Herring			gpio-controller;
301*724ba675SRob Herring			#gpio-cells = <2>;
302*724ba675SRob Herring		};
303*724ba675SRob Herring	};
304*724ba675SRob Herring
305*724ba675SRob Herring	hdmi_ddc: i2c@7000c400 {
306*724ba675SRob Herring		status = "okay";
307*724ba675SRob Herring		clock-frequency = <100000>;
308*724ba675SRob Herring	};
309*724ba675SRob Herring
310*724ba675SRob Herring	nvec@7000c500 {
311*724ba675SRob Herring		compatible = "nvidia,nvec";
312*724ba675SRob Herring		reg = <0x7000c500 0x100>;
313*724ba675SRob Herring		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
314*724ba675SRob Herring		#address-cells = <1>;
315*724ba675SRob Herring		#size-cells = <0>;
316*724ba675SRob Herring		clock-frequency = <80000>;
317*724ba675SRob Herring		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
318*724ba675SRob Herring		slave-addr = <138>;
319*724ba675SRob Herring		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
320*724ba675SRob Herring			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
321*724ba675SRob Herring		clock-names = "div-clk", "fast-clk";
322*724ba675SRob Herring		resets = <&tegra_car 67>;
323*724ba675SRob Herring		reset-names = "i2c";
324*724ba675SRob Herring	};
325*724ba675SRob Herring
326*724ba675SRob Herring	i2c@7000d000 {
327*724ba675SRob Herring		status = "okay";
328*724ba675SRob Herring		clock-frequency = <400000>;
329*724ba675SRob Herring
330*724ba675SRob Herring		pmic: tps6586x@34 {
331*724ba675SRob Herring			compatible = "ti,tps6586x";
332*724ba675SRob Herring			reg = <0x34>;
333*724ba675SRob Herring			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
334*724ba675SRob Herring
335*724ba675SRob Herring			#gpio-cells = <2>;
336*724ba675SRob Herring			gpio-controller;
337*724ba675SRob Herring
338*724ba675SRob Herring			sys-supply = <&p5valw_reg>;
339*724ba675SRob Herring			vin-sm0-supply = <&sys_reg>;
340*724ba675SRob Herring			vin-sm1-supply = <&sys_reg>;
341*724ba675SRob Herring			vin-sm2-supply = <&sys_reg>;
342*724ba675SRob Herring			vinldo01-supply = <&sm2_reg>;
343*724ba675SRob Herring			vinldo23-supply = <&sm2_reg>;
344*724ba675SRob Herring			vinldo4-supply = <&sm2_reg>;
345*724ba675SRob Herring			vinldo678-supply = <&sm2_reg>;
346*724ba675SRob Herring			vinldo9-supply = <&sm2_reg>;
347*724ba675SRob Herring
348*724ba675SRob Herring			regulators {
349*724ba675SRob Herring				sys_reg: sys {
350*724ba675SRob Herring					regulator-name = "vdd_sys";
351*724ba675SRob Herring					regulator-always-on;
352*724ba675SRob Herring				};
353*724ba675SRob Herring
354*724ba675SRob Herring				core_vdd_reg: sm0 {
355*724ba675SRob Herring					regulator-name = "+1.2vs_sm0,vdd_core";
356*724ba675SRob Herring					regulator-min-microvolt = <950000>;
357*724ba675SRob Herring					regulator-max-microvolt = <1300000>;
358*724ba675SRob Herring					regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
359*724ba675SRob Herring					regulator-coupled-max-spread = <170000 550000>;
360*724ba675SRob Herring					regulator-always-on;
361*724ba675SRob Herring
362*724ba675SRob Herring					nvidia,tegra-core-regulator;
363*724ba675SRob Herring				};
364*724ba675SRob Herring
365*724ba675SRob Herring				cpu_vdd_reg: sm1 {
366*724ba675SRob Herring					regulator-name = "+1.0vs_sm1,vdd_cpu";
367*724ba675SRob Herring					regulator-min-microvolt = <750000>;
368*724ba675SRob Herring					regulator-max-microvolt = <1100000>;
369*724ba675SRob Herring					regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
370*724ba675SRob Herring					regulator-coupled-max-spread = <550000 550000>;
371*724ba675SRob Herring					regulator-always-on;
372*724ba675SRob Herring
373*724ba675SRob Herring					nvidia,tegra-cpu-regulator;
374*724ba675SRob Herring				};
375*724ba675SRob Herring
376*724ba675SRob Herring				sm2_reg: sm2 {
377*724ba675SRob Herring					regulator-name = "+3.7vs_sm2,vin_ldo*";
378*724ba675SRob Herring					regulator-min-microvolt = <3700000>;
379*724ba675SRob Herring					regulator-max-microvolt = <3700000>;
380*724ba675SRob Herring					regulator-always-on;
381*724ba675SRob Herring				};
382*724ba675SRob Herring
383*724ba675SRob Herring				/* LDO0 is not connected to anything */
384*724ba675SRob Herring
385*724ba675SRob Herring				ldo1 {
386*724ba675SRob Herring					regulator-name = "+1.1vs_ldo1,avdd_pll*";
387*724ba675SRob Herring					regulator-min-microvolt = <1100000>;
388*724ba675SRob Herring					regulator-max-microvolt = <1100000>;
389*724ba675SRob Herring					regulator-always-on;
390*724ba675SRob Herring				};
391*724ba675SRob Herring
392*724ba675SRob Herring				rtc_vdd_reg: ldo2 {
393*724ba675SRob Herring					regulator-name = "+1.2vs_ldo2,vdd_rtc";
394*724ba675SRob Herring					regulator-min-microvolt = <950000>;
395*724ba675SRob Herring					regulator-max-microvolt = <1300000>;
396*724ba675SRob Herring					regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
397*724ba675SRob Herring					regulator-coupled-max-spread = <170000 550000>;
398*724ba675SRob Herring					regulator-always-on;
399*724ba675SRob Herring
400*724ba675SRob Herring					nvidia,tegra-rtc-regulator;
401*724ba675SRob Herring				};
402*724ba675SRob Herring
403*724ba675SRob Herring				ldo3 {
404*724ba675SRob Herring					regulator-name = "+3.3vs_ldo3,avdd_usb*";
405*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
406*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
407*724ba675SRob Herring					regulator-always-on;
408*724ba675SRob Herring				};
409*724ba675SRob Herring
410*724ba675SRob Herring				ldo4 {
411*724ba675SRob Herring					regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
412*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
413*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
414*724ba675SRob Herring					regulator-always-on;
415*724ba675SRob Herring				};
416*724ba675SRob Herring
417*724ba675SRob Herring				ldo5 {
418*724ba675SRob Herring					regulator-name = "+2.85vs_ldo5,vcore_mmc";
419*724ba675SRob Herring					regulator-min-microvolt = <2850000>;
420*724ba675SRob Herring					regulator-max-microvolt = <2850000>;
421*724ba675SRob Herring					regulator-always-on;
422*724ba675SRob Herring				};
423*724ba675SRob Herring
424*724ba675SRob Herring				ldo6 {
425*724ba675SRob Herring					/*
426*724ba675SRob Herring					 * Research indicates this should be
427*724ba675SRob Herring					 * 1.8v; other boards that use this
428*724ba675SRob Herring					 * rail for the same purpose need it
429*724ba675SRob Herring					 * set to 1.8v. The schematic signal
430*724ba675SRob Herring					 * name is incorrect; perhaps copied
431*724ba675SRob Herring					 * from an incorrect NVIDIA reference.
432*724ba675SRob Herring					 */
433*724ba675SRob Herring					regulator-name = "+2.85vs_ldo6,avdd_vdac";
434*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
435*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
436*724ba675SRob Herring				};
437*724ba675SRob Herring
438*724ba675SRob Herring				hdmi_vdd_reg: ldo7 {
439*724ba675SRob Herring					regulator-name = "+3.3vs_ldo7,avdd_hdmi";
440*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
441*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
442*724ba675SRob Herring				};
443*724ba675SRob Herring
444*724ba675SRob Herring				hdmi_pll_reg: ldo8 {
445*724ba675SRob Herring					regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
446*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
447*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
448*724ba675SRob Herring				};
449*724ba675SRob Herring
450*724ba675SRob Herring				ldo9 {
451*724ba675SRob Herring					regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
452*724ba675SRob Herring					regulator-min-microvolt = <2850000>;
453*724ba675SRob Herring					regulator-max-microvolt = <2850000>;
454*724ba675SRob Herring					regulator-always-on;
455*724ba675SRob Herring				};
456*724ba675SRob Herring
457*724ba675SRob Herring				ldo_rtc {
458*724ba675SRob Herring					regulator-name = "+3.3vs_rtc";
459*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
460*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
461*724ba675SRob Herring					regulator-always-on;
462*724ba675SRob Herring				};
463*724ba675SRob Herring			};
464*724ba675SRob Herring		};
465*724ba675SRob Herring
466*724ba675SRob Herring		adt7461: temperature-sensor@4c {
467*724ba675SRob Herring			compatible = "adi,adt7461";
468*724ba675SRob Herring			reg = <0x4c>;
469*724ba675SRob Herring
470*724ba675SRob Herring			interrupt-parent = <&gpio>;
471*724ba675SRob Herring			interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
472*724ba675SRob Herring
473*724ba675SRob Herring			#thermal-sensor-cells = <1>;
474*724ba675SRob Herring		};
475*724ba675SRob Herring	};
476*724ba675SRob Herring
477*724ba675SRob Herring	pmc@7000e400 {
478*724ba675SRob Herring		nvidia,invert-interrupt;
479*724ba675SRob Herring		nvidia,suspend-mode = <1>;
480*724ba675SRob Herring		nvidia,cpu-pwr-good-time = <2000>;
481*724ba675SRob Herring		nvidia,cpu-pwr-off-time = <0>;
482*724ba675SRob Herring		nvidia,core-pwr-good-time = <3845 3845>;
483*724ba675SRob Herring		nvidia,core-pwr-off-time = <0>;
484*724ba675SRob Herring		nvidia,sys-clock-req-active-high;
485*724ba675SRob Herring		core-supply = <&core_vdd_reg>;
486*724ba675SRob Herring	};
487*724ba675SRob Herring
488*724ba675SRob Herring	memory-controller@7000f400 {
489*724ba675SRob Herring		nvidia,use-ram-code;
490*724ba675SRob Herring
491*724ba675SRob Herring		emc-tables@0 {
492*724ba675SRob Herring			nvidia,ram-code = <0x0>;
493*724ba675SRob Herring			#address-cells = <1>;
494*724ba675SRob Herring			#size-cells = <0>;
495*724ba675SRob Herring			reg = <0>;
496*724ba675SRob Herring
497*724ba675SRob Herring			emc-table@166500 {
498*724ba675SRob Herring				reg = <166500>;
499*724ba675SRob Herring				compatible = "nvidia,tegra20-emc-table";
500*724ba675SRob Herring				clock-frequency = <166500>;
501*724ba675SRob Herring				nvidia,emc-registers = <0x0000000a 0x00000016
502*724ba675SRob Herring					0x00000008 0x00000003 0x00000004 0x00000004
503*724ba675SRob Herring					0x00000002 0x0000000c 0x00000003 0x00000003
504*724ba675SRob Herring					0x00000002 0x00000001 0x00000004 0x00000005
505*724ba675SRob Herring					0x00000004 0x00000009 0x0000000d 0x000004df
506*724ba675SRob Herring					0x00000000 0x00000003 0x00000003 0x00000003
507*724ba675SRob Herring					0x00000003 0x00000001 0x0000000a 0x000000c8
508*724ba675SRob Herring					0x00000003 0x00000006 0x00000004 0x00000008
509*724ba675SRob Herring					0x00000002 0x00000000 0x00000000 0x00000002
510*724ba675SRob Herring					0x00000000 0x00000000 0x00000083 0xe03b0323
511*724ba675SRob Herring					0x007fe010 0x00001414 0x00000000 0x00000000
512*724ba675SRob Herring					0x00000000 0x00000000 0x00000000 0x00000000>;
513*724ba675SRob Herring			};
514*724ba675SRob Herring
515*724ba675SRob Herring			emc-table@333000 {
516*724ba675SRob Herring				reg = <333000>;
517*724ba675SRob Herring				compatible = "nvidia,tegra20-emc-table";
518*724ba675SRob Herring				clock-frequency = <333000>;
519*724ba675SRob Herring				nvidia,emc-registers = <0x00000018 0x00000033
520*724ba675SRob Herring					0x00000012 0x00000004 0x00000004 0x00000005
521*724ba675SRob Herring					0x00000003 0x0000000c 0x00000006 0x00000006
522*724ba675SRob Herring					0x00000003 0x00000001 0x00000004 0x00000005
523*724ba675SRob Herring					0x00000004 0x00000009 0x0000000d 0x00000bff
524*724ba675SRob Herring					0x00000000 0x00000003 0x00000003 0x00000006
525*724ba675SRob Herring					0x00000006 0x00000001 0x00000011 0x000000c8
526*724ba675SRob Herring					0x00000003 0x0000000e 0x00000007 0x00000008
527*724ba675SRob Herring					0x00000002 0x00000000 0x00000000 0x00000002
528*724ba675SRob Herring					0x00000000 0x00000000 0x00000083 0xf0440303
529*724ba675SRob Herring					0x007fe010 0x00001414 0x00000000 0x00000000
530*724ba675SRob Herring					0x00000000 0x00000000 0x00000000 0x00000000>;
531*724ba675SRob Herring			};
532*724ba675SRob Herring		};
533*724ba675SRob Herring	};
534*724ba675SRob Herring
535*724ba675SRob Herring	usb@c5000000 {
536*724ba675SRob Herring		compatible = "nvidia,tegra20-udc";
537*724ba675SRob Herring		status = "okay";
538*724ba675SRob Herring		dr_mode = "peripheral";
539*724ba675SRob Herring	};
540*724ba675SRob Herring
541*724ba675SRob Herring	usb-phy@c5000000 {
542*724ba675SRob Herring		status = "okay";
543*724ba675SRob Herring	};
544*724ba675SRob Herring
545*724ba675SRob Herring	usb@c5004000 {
546*724ba675SRob Herring		status = "okay";
547*724ba675SRob Herring	};
548*724ba675SRob Herring
549*724ba675SRob Herring	usb-phy@c5004000 {
550*724ba675SRob Herring		status = "okay";
551*724ba675SRob Herring		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
552*724ba675SRob Herring			GPIO_ACTIVE_LOW>;
553*724ba675SRob Herring	};
554*724ba675SRob Herring
555*724ba675SRob Herring	usb@c5008000 {
556*724ba675SRob Herring		status = "okay";
557*724ba675SRob Herring	};
558*724ba675SRob Herring
559*724ba675SRob Herring	usb-phy@c5008000 {
560*724ba675SRob Herring		status = "okay";
561*724ba675SRob Herring	};
562*724ba675SRob Herring
563*724ba675SRob Herring	sdmmc1: mmc@c8000000 {
564*724ba675SRob Herring		status = "okay";
565*724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
566*724ba675SRob Herring		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
567*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
568*724ba675SRob Herring		bus-width = <4>;
569*724ba675SRob Herring	};
570*724ba675SRob Herring
571*724ba675SRob Herring	sdmmc4: mmc@c8000600 {
572*724ba675SRob Herring		status = "okay";
573*724ba675SRob Herring		bus-width = <8>;
574*724ba675SRob Herring		non-removable;
575*724ba675SRob Herring	};
576*724ba675SRob Herring
577*724ba675SRob Herring	backlight: backlight {
578*724ba675SRob Herring		compatible = "pwm-backlight";
579*724ba675SRob Herring
580*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
581*724ba675SRob Herring		pwms = <&pwm 0 5000000>;
582*724ba675SRob Herring
583*724ba675SRob Herring		brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
584*724ba675SRob Herring		default-brightness-level = <10>;
585*724ba675SRob Herring
586*724ba675SRob Herring		/* close enough */
587*724ba675SRob Herring		power-supply = <&vdd_pnl_reg>;
588*724ba675SRob Herring	};
589*724ba675SRob Herring
590*724ba675SRob Herring	clk32k_in: clock-32k {
591*724ba675SRob Herring		compatible = "fixed-clock";
592*724ba675SRob Herring		clock-frequency = <32768>;
593*724ba675SRob Herring		#clock-cells = <0>;
594*724ba675SRob Herring	};
595*724ba675SRob Herring
596*724ba675SRob Herring	cpus {
597*724ba675SRob Herring		cpu0: cpu@0 {
598*724ba675SRob Herring			cpu-supply = <&cpu_vdd_reg>;
599*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
600*724ba675SRob Herring			#cooling-cells = <2>;
601*724ba675SRob Herring		};
602*724ba675SRob Herring
603*724ba675SRob Herring		cpu1: cpu@1 {
604*724ba675SRob Herring			cpu-supply = <&cpu_vdd_reg>;
605*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
606*724ba675SRob Herring			#cooling-cells = <2>;
607*724ba675SRob Herring		};
608*724ba675SRob Herring	};
609*724ba675SRob Herring
610*724ba675SRob Herring	gpio-keys {
611*724ba675SRob Herring		compatible = "gpio-keys";
612*724ba675SRob Herring
613*724ba675SRob Herring		key-wakeup {
614*724ba675SRob Herring			label = "Wakeup";
615*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
616*724ba675SRob Herring			linux,code = <KEY_WAKEUP>;
617*724ba675SRob Herring			wakeup-source;
618*724ba675SRob Herring		};
619*724ba675SRob Herring	};
620*724ba675SRob Herring
621*724ba675SRob Herring	gpio-leds {
622*724ba675SRob Herring		compatible = "gpio-leds";
623*724ba675SRob Herring
624*724ba675SRob Herring		led-0 {
625*724ba675SRob Herring			label = "wifi-led";
626*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
627*724ba675SRob Herring			linux,default-trigger = "rfkill0";
628*724ba675SRob Herring		};
629*724ba675SRob Herring	};
630*724ba675SRob Herring
631*724ba675SRob Herring	opp-table-emc {
632*724ba675SRob Herring		/delete-node/ opp-760000000;
633*724ba675SRob Herring	};
634*724ba675SRob Herring
635*724ba675SRob Herring	panel: panel {
636*724ba675SRob Herring		compatible = "samsung,ltn101nt05";
637*724ba675SRob Herring
638*724ba675SRob Herring		ddc-i2c-bus = <&lvds_ddc>;
639*724ba675SRob Herring		power-supply = <&vdd_pnl_reg>;
640*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
641*724ba675SRob Herring
642*724ba675SRob Herring		backlight = <&backlight>;
643*724ba675SRob Herring	};
644*724ba675SRob Herring
645*724ba675SRob Herring	p5valw_reg: regulator-5v0alw {
646*724ba675SRob Herring		compatible = "regulator-fixed";
647*724ba675SRob Herring		regulator-name = "+5valw";
648*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
649*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
650*724ba675SRob Herring		regulator-always-on;
651*724ba675SRob Herring	};
652*724ba675SRob Herring
653*724ba675SRob Herring	vdd_pnl_reg: regulator-3v0 {
654*724ba675SRob Herring		compatible = "regulator-fixed";
655*724ba675SRob Herring		regulator-name = "+3VS,vdd_pnl";
656*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
657*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
658*724ba675SRob Herring		regulator-boot-on;
659*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
660*724ba675SRob Herring		enable-active-high;
661*724ba675SRob Herring	};
662*724ba675SRob Herring
663*724ba675SRob Herring	sound {
664*724ba675SRob Herring		compatible = "nvidia,tegra-audio-alc5632-paz00",
665*724ba675SRob Herring			"nvidia,tegra-audio-alc5632";
666*724ba675SRob Herring
667*724ba675SRob Herring		nvidia,model = "Compal PAZ00";
668*724ba675SRob Herring
669*724ba675SRob Herring		nvidia,audio-routing =
670*724ba675SRob Herring			"Int Spk", "SPKOUT",
671*724ba675SRob Herring			"Int Spk", "SPKOUTN",
672*724ba675SRob Herring			"Headset Mic", "MICBIAS1",
673*724ba675SRob Herring			"MIC1", "Headset Mic",
674*724ba675SRob Herring			"Headset Stereophone", "HPR",
675*724ba675SRob Herring			"Headset Stereophone", "HPL",
676*724ba675SRob Herring			"DMICDAT", "Digital Mic";
677*724ba675SRob Herring
678*724ba675SRob Herring		nvidia,audio-codec = <&alc5632>;
679*724ba675SRob Herring		nvidia,i2s-controller = <&tegra_i2s1>;
680*724ba675SRob Herring		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
681*724ba675SRob Herring			GPIO_ACTIVE_HIGH>;
682*724ba675SRob Herring
683*724ba675SRob Herring		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
684*724ba675SRob Herring			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
685*724ba675SRob Herring			 <&tegra_car TEGRA20_CLK_CDEV1>;
686*724ba675SRob Herring		clock-names = "pll_a", "pll_a_out0", "mclk";
687*724ba675SRob Herring	};
688*724ba675SRob Herring
689*724ba675SRob Herring	thermal-zones {
690*724ba675SRob Herring		cpu-thermal {
691*724ba675SRob Herring			polling-delay-passive = <500>; /* milliseconds */
692*724ba675SRob Herring			polling-delay = <1500>; /* milliseconds */
693*724ba675SRob Herring
694*724ba675SRob Herring			thermal-sensors = <&adt7461 1>;
695*724ba675SRob Herring
696*724ba675SRob Herring			trips {
697*724ba675SRob Herring				trip0: cpu-alert0 {
698*724ba675SRob Herring					/* start throttling at 80C */
699*724ba675SRob Herring					temperature = <80000>;
700*724ba675SRob Herring					hysteresis = <200>;
701*724ba675SRob Herring					type = "passive";
702*724ba675SRob Herring				};
703*724ba675SRob Herring
704*724ba675SRob Herring				trip1: cpu-crit {
705*724ba675SRob Herring					/* shut down at 85C */
706*724ba675SRob Herring					temperature = <85000>;
707*724ba675SRob Herring					hysteresis = <2000>;
708*724ba675SRob Herring					type = "critical";
709*724ba675SRob Herring				};
710*724ba675SRob Herring			};
711*724ba675SRob Herring
712*724ba675SRob Herring			cooling-maps {
713*724ba675SRob Herring				map0 {
714*724ba675SRob Herring					trip = <&trip0>;
715*724ba675SRob Herring					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
716*724ba675SRob Herring							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
717*724ba675SRob Herring				};
718*724ba675SRob Herring			};
719*724ba675SRob Herring		};
720*724ba675SRob Herring	};
721*724ba675SRob Herring};
722