1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/input/atmel-maxtouch.h> 5*724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h> 6*724ba675SRob Herring#include <dt-bindings/input/input.h> 7*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 8*724ba675SRob Herring 9*724ba675SRob Herring#include "tegra20.dtsi" 10*724ba675SRob Herring#include "tegra20-cpu-opp.dtsi" 11*724ba675SRob Herring#include "tegra20-cpu-opp-microvolt.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "Acer Iconia Tab A500"; 15*724ba675SRob Herring compatible = "acer,picasso", "nvidia,tegra20"; 16*724ba675SRob Herring 17*724ba675SRob Herring aliases { 18*724ba675SRob Herring mmc0 = &sdmmc4; /* eMMC */ 19*724ba675SRob Herring mmc1 = &sdmmc3; /* MicroSD */ 20*724ba675SRob Herring mmc2 = &sdmmc1; /* WiFi */ 21*724ba675SRob Herring 22*724ba675SRob Herring rtc0 = &pmic; 23*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 24*724ba675SRob Herring 25*724ba675SRob Herring serial0 = &uartd; /* Docking station */ 26*724ba675SRob Herring serial1 = &uartc; /* Bluetooth */ 27*724ba675SRob Herring serial2 = &uartb; /* GPS */ 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring /* 31*724ba675SRob Herring * The decompressor and also some bootloaders rely on a 32*724ba675SRob Herring * pre-existing /chosen node to be available to insert the 33*724ba675SRob Herring * command line and merge other ATAGS info. 34*724ba675SRob Herring */ 35*724ba675SRob Herring chosen {}; 36*724ba675SRob Herring 37*724ba675SRob Herring memory@0 { 38*724ba675SRob Herring reg = <0x00000000 0x40000000>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring reserved-memory { 42*724ba675SRob Herring #address-cells = <1>; 43*724ba675SRob Herring #size-cells = <1>; 44*724ba675SRob Herring ranges; 45*724ba675SRob Herring 46*724ba675SRob Herring ramoops@2ffe0000 { 47*724ba675SRob Herring compatible = "ramoops"; 48*724ba675SRob Herring reg = <0x2ffe0000 0x10000>; /* 64kB */ 49*724ba675SRob Herring console-size = <0x8000>; /* 32kB */ 50*724ba675SRob Herring record-size = <0x400>; /* 1kB */ 51*724ba675SRob Herring ecc-size = <16>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring linux,cma@30000000 { 55*724ba675SRob Herring compatible = "shared-dma-pool"; 56*724ba675SRob Herring alloc-ranges = <0x30000000 0x10000000>; 57*724ba675SRob Herring size = <0x10000000>; /* 256MiB */ 58*724ba675SRob Herring linux,cma-default; 59*724ba675SRob Herring reusable; 60*724ba675SRob Herring }; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring host1x@50000000 { 64*724ba675SRob Herring dc@54200000 { 65*724ba675SRob Herring rgb { 66*724ba675SRob Herring status = "okay"; 67*724ba675SRob Herring 68*724ba675SRob Herring port@0 { 69*724ba675SRob Herring lcd_output: endpoint { 70*724ba675SRob Herring remote-endpoint = <&lvds_encoder_input>; 71*724ba675SRob Herring bus-width = <18>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring }; 74*724ba675SRob Herring }; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring hdmi@54280000 { 78*724ba675SRob Herring status = "okay"; 79*724ba675SRob Herring 80*724ba675SRob Herring vdd-supply = <&hdmi_vdd_reg>; 81*724ba675SRob Herring pll-supply = <&hdmi_pll_reg>; 82*724ba675SRob Herring hdmi-supply = <&vdd_5v0_sys>; 83*724ba675SRob Herring 84*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 85*724ba675SRob Herring nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 86*724ba675SRob Herring GPIO_ACTIVE_HIGH>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring pinmux@70000014 { 91*724ba675SRob Herring pinctrl-names = "default"; 92*724ba675SRob Herring pinctrl-0 = <&state_default>; 93*724ba675SRob Herring 94*724ba675SRob Herring state_default: pinmux { 95*724ba675SRob Herring ata { 96*724ba675SRob Herring nvidia,pins = "ata"; 97*724ba675SRob Herring nvidia,function = "ide"; 98*724ba675SRob Herring }; 99*724ba675SRob Herring atb { 100*724ba675SRob Herring nvidia,pins = "atb", "gma", "gme"; 101*724ba675SRob Herring nvidia,function = "sdio4"; 102*724ba675SRob Herring }; 103*724ba675SRob Herring atc { 104*724ba675SRob Herring nvidia,pins = "atc"; 105*724ba675SRob Herring nvidia,function = "nand"; 106*724ba675SRob Herring }; 107*724ba675SRob Herring atd { 108*724ba675SRob Herring nvidia,pins = "atd", "ate", "gmb", "spia", 109*724ba675SRob Herring "spib", "spic"; 110*724ba675SRob Herring nvidia,function = "gmi"; 111*724ba675SRob Herring }; 112*724ba675SRob Herring cdev1 { 113*724ba675SRob Herring nvidia,pins = "cdev1"; 114*724ba675SRob Herring nvidia,function = "plla_out"; 115*724ba675SRob Herring }; 116*724ba675SRob Herring cdev2 { 117*724ba675SRob Herring nvidia,pins = "cdev2"; 118*724ba675SRob Herring nvidia,function = "pllp_out4"; 119*724ba675SRob Herring }; 120*724ba675SRob Herring crtp { 121*724ba675SRob Herring nvidia,pins = "crtp", "lm1"; 122*724ba675SRob Herring nvidia,function = "crt"; 123*724ba675SRob Herring }; 124*724ba675SRob Herring csus { 125*724ba675SRob Herring nvidia,pins = "csus"; 126*724ba675SRob Herring nvidia,function = "vi_sensor_clk"; 127*724ba675SRob Herring }; 128*724ba675SRob Herring dap1 { 129*724ba675SRob Herring nvidia,pins = "dap1"; 130*724ba675SRob Herring nvidia,function = "dap1"; 131*724ba675SRob Herring }; 132*724ba675SRob Herring dap2 { 133*724ba675SRob Herring nvidia,pins = "dap2"; 134*724ba675SRob Herring nvidia,function = "dap2"; 135*724ba675SRob Herring }; 136*724ba675SRob Herring dap3 { 137*724ba675SRob Herring nvidia,pins = "dap3"; 138*724ba675SRob Herring nvidia,function = "dap3"; 139*724ba675SRob Herring }; 140*724ba675SRob Herring dap4 { 141*724ba675SRob Herring nvidia,pins = "dap4"; 142*724ba675SRob Herring nvidia,function = "dap4"; 143*724ba675SRob Herring }; 144*724ba675SRob Herring dta { 145*724ba675SRob Herring nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 146*724ba675SRob Herring nvidia,function = "vi"; 147*724ba675SRob Herring }; 148*724ba675SRob Herring dtf { 149*724ba675SRob Herring nvidia,pins = "dtf"; 150*724ba675SRob Herring nvidia,function = "i2c3"; 151*724ba675SRob Herring }; 152*724ba675SRob Herring gmc { 153*724ba675SRob Herring nvidia,pins = "gmc"; 154*724ba675SRob Herring nvidia,function = "uartd"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring gmd { 157*724ba675SRob Herring nvidia,pins = "gmd"; 158*724ba675SRob Herring nvidia,function = "sflash"; 159*724ba675SRob Herring }; 160*724ba675SRob Herring gpu { 161*724ba675SRob Herring nvidia,pins = "gpu"; 162*724ba675SRob Herring nvidia,function = "pwm"; 163*724ba675SRob Herring }; 164*724ba675SRob Herring gpu7 { 165*724ba675SRob Herring nvidia,pins = "gpu7"; 166*724ba675SRob Herring nvidia,function = "rtck"; 167*724ba675SRob Herring }; 168*724ba675SRob Herring gpv { 169*724ba675SRob Herring nvidia,pins = "gpv", "slxa"; 170*724ba675SRob Herring nvidia,function = "pcie"; 171*724ba675SRob Herring }; 172*724ba675SRob Herring hdint { 173*724ba675SRob Herring nvidia,pins = "hdint"; 174*724ba675SRob Herring nvidia,function = "hdmi"; 175*724ba675SRob Herring }; 176*724ba675SRob Herring i2cp { 177*724ba675SRob Herring nvidia,pins = "i2cp"; 178*724ba675SRob Herring nvidia,function = "i2cp"; 179*724ba675SRob Herring }; 180*724ba675SRob Herring irrx { 181*724ba675SRob Herring nvidia,pins = "irrx", "irtx"; 182*724ba675SRob Herring nvidia,function = "uartb"; 183*724ba675SRob Herring }; 184*724ba675SRob Herring kbca { 185*724ba675SRob Herring nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 186*724ba675SRob Herring "kbce", "kbcf"; 187*724ba675SRob Herring nvidia,function = "kbc"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring lcsn { 190*724ba675SRob Herring nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", 191*724ba675SRob Herring "lsdi", "lvp0"; 192*724ba675SRob Herring nvidia,function = "rsvd4"; 193*724ba675SRob Herring }; 194*724ba675SRob Herring ld0 { 195*724ba675SRob Herring nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 196*724ba675SRob Herring "ld5", "ld6", "ld7", "ld8", "ld9", 197*724ba675SRob Herring "ld10", "ld11", "ld12", "ld13", "ld14", 198*724ba675SRob Herring "ld15", "ld16", "ld17", "ldi", "lhp0", 199*724ba675SRob Herring "lhp1", "lhp2", "lhs", "lpp", "lsc0", 200*724ba675SRob Herring "lsc1", "lsck", "lsda", "lspi", "lvp1", 201*724ba675SRob Herring "lvs"; 202*724ba675SRob Herring nvidia,function = "displaya"; 203*724ba675SRob Herring }; 204*724ba675SRob Herring owc { 205*724ba675SRob Herring nvidia,pins = "owc", "spdi", "spdo", "uac"; 206*724ba675SRob Herring nvidia,function = "rsvd2"; 207*724ba675SRob Herring }; 208*724ba675SRob Herring pmc { 209*724ba675SRob Herring nvidia,pins = "pmc"; 210*724ba675SRob Herring nvidia,function = "pwr_on"; 211*724ba675SRob Herring }; 212*724ba675SRob Herring rm { 213*724ba675SRob Herring nvidia,pins = "rm"; 214*724ba675SRob Herring nvidia,function = "i2c1"; 215*724ba675SRob Herring }; 216*724ba675SRob Herring sdb { 217*724ba675SRob Herring nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; 218*724ba675SRob Herring nvidia,function = "sdio3"; 219*724ba675SRob Herring }; 220*724ba675SRob Herring sdio1 { 221*724ba675SRob Herring nvidia,pins = "sdio1"; 222*724ba675SRob Herring nvidia,function = "sdio1"; 223*724ba675SRob Herring }; 224*724ba675SRob Herring slxd { 225*724ba675SRob Herring nvidia,pins = "slxd"; 226*724ba675SRob Herring nvidia,function = "spdif"; 227*724ba675SRob Herring }; 228*724ba675SRob Herring spid { 229*724ba675SRob Herring nvidia,pins = "spid", "spie", "spif"; 230*724ba675SRob Herring nvidia,function = "spi1"; 231*724ba675SRob Herring }; 232*724ba675SRob Herring spig { 233*724ba675SRob Herring nvidia,pins = "spig", "spih"; 234*724ba675SRob Herring nvidia,function = "spi2_alt"; 235*724ba675SRob Herring }; 236*724ba675SRob Herring uaa { 237*724ba675SRob Herring nvidia,pins = "uaa", "uab", "uda"; 238*724ba675SRob Herring nvidia,function = "ulpi"; 239*724ba675SRob Herring }; 240*724ba675SRob Herring uad { 241*724ba675SRob Herring nvidia,pins = "uad"; 242*724ba675SRob Herring nvidia,function = "irda"; 243*724ba675SRob Herring }; 244*724ba675SRob Herring uca { 245*724ba675SRob Herring nvidia,pins = "uca", "ucb"; 246*724ba675SRob Herring nvidia,function = "uartc"; 247*724ba675SRob Herring }; 248*724ba675SRob Herring conf_ata { 249*724ba675SRob Herring nvidia,pins = "ata", "atb", "atc", "atd", 250*724ba675SRob Herring "cdev1", "cdev2", "csus", "dap1", 251*724ba675SRob Herring "dap4", "dte", "dtf", "gma", "gmc", 252*724ba675SRob Herring "gme", "gpu", "gpu7", "gpv", "i2cp", 253*724ba675SRob Herring "irrx", "irtx", "pta", "rm", 254*724ba675SRob Herring "sdc", "sdd", "slxc", "slxd", "slxk", 255*724ba675SRob Herring "spdi", "spdo", "uac", "uad", "uda"; 256*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 257*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 258*724ba675SRob Herring }; 259*724ba675SRob Herring conf_ate { 260*724ba675SRob Herring nvidia,pins = "ate", "dap2", "dap3", 261*724ba675SRob Herring "gmd", "owc", "spia", "spib", "spic", 262*724ba675SRob Herring "spid", "spie"; 263*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 264*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 265*724ba675SRob Herring }; 266*724ba675SRob Herring conf_ck32 { 267*724ba675SRob Herring nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 268*724ba675SRob Herring "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 269*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 270*724ba675SRob Herring }; 271*724ba675SRob Herring conf_crtp { 272*724ba675SRob Herring nvidia,pins = "crtp", "gmb", "slxa", "spig", 273*724ba675SRob Herring "spih"; 274*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 275*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring conf_dta { 278*724ba675SRob Herring nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; 279*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 280*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 281*724ba675SRob Herring }; 282*724ba675SRob Herring conf_dte { 283*724ba675SRob Herring nvidia,pins = "spif"; 284*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 285*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 286*724ba675SRob Herring }; 287*724ba675SRob Herring conf_hdint { 288*724ba675SRob Herring nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 289*724ba675SRob Herring "lpw1", "lsck", "lsda", "lsdi", 290*724ba675SRob Herring "lvp0"; 291*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring conf_kbca { 294*724ba675SRob Herring nvidia,pins = "kbca", "kbcc", "kbcd", 295*724ba675SRob Herring "kbce", "kbcf", "sdio1", "uaa", 296*724ba675SRob Herring "uab", "uca", "ucb"; 297*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 298*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 299*724ba675SRob Herring }; 300*724ba675SRob Herring conf_lc { 301*724ba675SRob Herring nvidia,pins = "lc", "ls"; 302*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring conf_ld0 { 305*724ba675SRob Herring nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 306*724ba675SRob Herring "ld5", "ld6", "ld7", "ld8", "ld9", 307*724ba675SRob Herring "ld10", "ld11", "ld12", "ld13", "ld14", 308*724ba675SRob Herring "ld15", "ld16", "ld17", "ldi", "lhp0", 309*724ba675SRob Herring "lhp1", "lhp2", "lhs", "lm0", "lpp", 310*724ba675SRob Herring "lpw0", "lpw2", "lsc0", "lsc1", "lspi", 311*724ba675SRob Herring "lvp1", "lvs", "pmc", "sdb"; 312*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 313*724ba675SRob Herring }; 314*724ba675SRob Herring conf_ld17_0 { 315*724ba675SRob Herring nvidia,pins = "ld17_0"; 316*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 317*724ba675SRob Herring }; 318*724ba675SRob Herring drive_ddc { 319*724ba675SRob Herring nvidia,pins = "drive_ddc", 320*724ba675SRob Herring "drive_vi1", 321*724ba675SRob Herring "drive_sdio1"; 322*724ba675SRob Herring nvidia,pull-up-strength = <31>; 323*724ba675SRob Herring nvidia,pull-down-strength = <31>; 324*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_ENABLE>; 325*724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 326*724ba675SRob Herring nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 327*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 328*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 329*724ba675SRob Herring }; 330*724ba675SRob Herring drive_dbg { 331*724ba675SRob Herring nvidia,pins = "drive_dbg", 332*724ba675SRob Herring "drive_vi2", 333*724ba675SRob Herring "drive_at1", 334*724ba675SRob Herring "drive_ao1"; 335*724ba675SRob Herring nvidia,pull-up-strength = <31>; 336*724ba675SRob Herring nvidia,pull-down-strength = <31>; 337*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_ENABLE>; 338*724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 339*724ba675SRob Herring nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 340*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 341*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 342*724ba675SRob Herring }; 343*724ba675SRob Herring }; 344*724ba675SRob Herring 345*724ba675SRob Herring state_i2cmux_ddc: pinmux-i2cmux-ddc { 346*724ba675SRob Herring ddc { 347*724ba675SRob Herring nvidia,pins = "ddc"; 348*724ba675SRob Herring nvidia,function = "i2c2"; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring pta { 352*724ba675SRob Herring nvidia,pins = "pta"; 353*724ba675SRob Herring nvidia,function = "rsvd4"; 354*724ba675SRob Herring }; 355*724ba675SRob Herring }; 356*724ba675SRob Herring 357*724ba675SRob Herring state_i2cmux_idle: pinmux-i2cmux-idle { 358*724ba675SRob Herring ddc { 359*724ba675SRob Herring nvidia,pins = "ddc"; 360*724ba675SRob Herring nvidia,function = "rsvd4"; 361*724ba675SRob Herring }; 362*724ba675SRob Herring 363*724ba675SRob Herring pta { 364*724ba675SRob Herring nvidia,pins = "pta"; 365*724ba675SRob Herring nvidia,function = "rsvd4"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring state_i2cmux_pta: pinmux-i2cmux-pta { 370*724ba675SRob Herring ddc { 371*724ba675SRob Herring nvidia,pins = "ddc"; 372*724ba675SRob Herring nvidia,function = "rsvd4"; 373*724ba675SRob Herring }; 374*724ba675SRob Herring 375*724ba675SRob Herring pta { 376*724ba675SRob Herring nvidia,pins = "pta"; 377*724ba675SRob Herring nvidia,function = "i2c2"; 378*724ba675SRob Herring }; 379*724ba675SRob Herring }; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring tegra_spdif: spdif@70002400 { 383*724ba675SRob Herring status = "okay"; 384*724ba675SRob Herring 385*724ba675SRob Herring nvidia,fixed-parent-rate; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring tegra_i2s1: i2s@70002800 { 389*724ba675SRob Herring status = "okay"; 390*724ba675SRob Herring 391*724ba675SRob Herring nvidia,fixed-parent-rate; 392*724ba675SRob Herring }; 393*724ba675SRob Herring 394*724ba675SRob Herring uartb: serial@70006040 { 395*724ba675SRob Herring compatible = "nvidia,tegra20-hsuart"; 396*724ba675SRob Herring /delete-property/ reg-shift; 397*724ba675SRob Herring /* GPS BCM4751 */ 398*724ba675SRob Herring }; 399*724ba675SRob Herring 400*724ba675SRob Herring uartc: serial@70006200 { 401*724ba675SRob Herring compatible = "nvidia,tegra20-hsuart"; 402*724ba675SRob Herring /delete-property/ reg-shift; 403*724ba675SRob Herring status = "okay"; 404*724ba675SRob Herring 405*724ba675SRob Herring /* Azurewave AW-NH665 BCM4329B1 */ 406*724ba675SRob Herring bluetooth { 407*724ba675SRob Herring compatible = "brcm,bcm4329-bt"; 408*724ba675SRob Herring 409*724ba675SRob Herring interrupt-parent = <&gpio>; 410*724ba675SRob Herring interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 411*724ba675SRob Herring interrupt-names = "host-wakeup"; 412*724ba675SRob Herring 413*724ba675SRob Herring /* PLLP 216MHz / 16 / 4 */ 414*724ba675SRob Herring max-speed = <3375000>; 415*724ba675SRob Herring 416*724ba675SRob Herring clocks = <&rtc_32k_wifi>; 417*724ba675SRob Herring clock-names = "txco"; 418*724ba675SRob Herring 419*724ba675SRob Herring vbat-supply = <&vdd_3v3_sys>; 420*724ba675SRob Herring vddio-supply = <&vdd_1v8_sys>; 421*724ba675SRob Herring 422*724ba675SRob Herring device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 423*724ba675SRob Herring shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 424*724ba675SRob Herring }; 425*724ba675SRob Herring }; 426*724ba675SRob Herring 427*724ba675SRob Herring uartd: serial@70006300 { 428*724ba675SRob Herring /* Docking station */ 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring pwm: pwm@7000a000 { 432*724ba675SRob Herring status = "okay"; 433*724ba675SRob Herring }; 434*724ba675SRob Herring 435*724ba675SRob Herring i2c@7000c000 { 436*724ba675SRob Herring clock-frequency = <400000>; 437*724ba675SRob Herring status = "okay"; 438*724ba675SRob Herring 439*724ba675SRob Herring wm8903: audio-codec@1a { 440*724ba675SRob Herring compatible = "wlf,wm8903"; 441*724ba675SRob Herring reg = <0x1a>; 442*724ba675SRob Herring 443*724ba675SRob Herring interrupt-parent = <&gpio>; 444*724ba675SRob Herring interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>; 445*724ba675SRob Herring 446*724ba675SRob Herring gpio-controller; 447*724ba675SRob Herring #gpio-cells = <2>; 448*724ba675SRob Herring 449*724ba675SRob Herring micdet-cfg = <0>; 450*724ba675SRob Herring micdet-delay = <100>; 451*724ba675SRob Herring 452*724ba675SRob Herring gpio-cfg = < 453*724ba675SRob Herring 0x0000 /* MIC_LR_OUT# GPIO, output, low */ 454*724ba675SRob Herring 0x0000 /* FM2018-enable GPIO, output, low */ 455*724ba675SRob Herring 0x0000 /* Speaker-enable GPIO, output, low */ 456*724ba675SRob Herring 0x0200 /* Interrupt, output */ 457*724ba675SRob Herring 0x01a0 /* BCLK, input, active high */ 458*724ba675SRob Herring >; 459*724ba675SRob Herring 460*724ba675SRob Herring AVDD-supply = <&vdd_1v8_sys>; 461*724ba675SRob Herring CPVDD-supply = <&vdd_1v8_sys>; 462*724ba675SRob Herring DBVDD-supply = <&vdd_1v8_sys>; 463*724ba675SRob Herring DCVDD-supply = <&vdd_1v8_sys>; 464*724ba675SRob Herring }; 465*724ba675SRob Herring 466*724ba675SRob Herring touchscreen@4c { 467*724ba675SRob Herring compatible = "atmel,maxtouch"; 468*724ba675SRob Herring reg = <0x4c>; 469*724ba675SRob Herring 470*724ba675SRob Herring interrupt-parent = <&gpio>; 471*724ba675SRob Herring interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>; 472*724ba675SRob Herring 473*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; 474*724ba675SRob Herring 475*724ba675SRob Herring vdda-supply = <&vdd_3v3_sys>; 476*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 477*724ba675SRob Herring 478*724ba675SRob Herring atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>; 479*724ba675SRob Herring }; 480*724ba675SRob Herring 481*724ba675SRob Herring gyroscope@68 { 482*724ba675SRob Herring compatible = "invensense,mpu3050"; 483*724ba675SRob Herring reg = <0x68>; 484*724ba675SRob Herring 485*724ba675SRob Herring interrupt-parent = <&gpio>; 486*724ba675SRob Herring interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>; 487*724ba675SRob Herring 488*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 489*724ba675SRob Herring vlogic-supply = <&vdd_1v8_sys>; 490*724ba675SRob Herring 491*724ba675SRob Herring mount-matrix = "0", "1", "0", 492*724ba675SRob Herring "1", "0", "0", 493*724ba675SRob Herring "0", "0", "-1"; 494*724ba675SRob Herring 495*724ba675SRob Herring i2c-gate { 496*724ba675SRob Herring #address-cells = <1>; 497*724ba675SRob Herring #size-cells = <0>; 498*724ba675SRob Herring 499*724ba675SRob Herring accelerometer@f { 500*724ba675SRob Herring compatible = "kionix,kxtf9"; 501*724ba675SRob Herring reg = <0x0f>; 502*724ba675SRob Herring 503*724ba675SRob Herring interrupt-parent = <&gpio>; 504*724ba675SRob Herring interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>; 505*724ba675SRob Herring 506*724ba675SRob Herring vdd-supply = <&vdd_1v8_sys>; 507*724ba675SRob Herring vddio-supply = <&vdd_1v8_sys>; 508*724ba675SRob Herring 509*724ba675SRob Herring mount-matrix = "0", "1", "0", 510*724ba675SRob Herring "1", "0", "0", 511*724ba675SRob Herring "0", "0", "-1"; 512*724ba675SRob Herring }; 513*724ba675SRob Herring }; 514*724ba675SRob Herring }; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring i2c@7000c400 { 518*724ba675SRob Herring clock-frequency = <10000>; 519*724ba675SRob Herring status = "okay"; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring i2c@7000d000 { 523*724ba675SRob Herring clock-frequency = <100000>; 524*724ba675SRob Herring status = "okay"; 525*724ba675SRob Herring 526*724ba675SRob Herring magnetometer@c { 527*724ba675SRob Herring compatible = "asahi-kasei,ak8975"; 528*724ba675SRob Herring reg = <0x0c>; 529*724ba675SRob Herring 530*724ba675SRob Herring interrupt-parent = <&gpio>; 531*724ba675SRob Herring interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>; 532*724ba675SRob Herring 533*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 534*724ba675SRob Herring vid-supply = <&vdd_1v8_sys>; 535*724ba675SRob Herring 536*724ba675SRob Herring mount-matrix = "1", "0", "0", 537*724ba675SRob Herring "0", "-1", "0", 538*724ba675SRob Herring "0", "0", "-1"; 539*724ba675SRob Herring }; 540*724ba675SRob Herring 541*724ba675SRob Herring pmic: pmic@34 { 542*724ba675SRob Herring compatible = "ti,tps6586x"; 543*724ba675SRob Herring reg = <0x34>; 544*724ba675SRob Herring 545*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 546*724ba675SRob Herring 547*724ba675SRob Herring #gpio-cells = <2>; 548*724ba675SRob Herring gpio-controller; 549*724ba675SRob Herring 550*724ba675SRob Herring sys-supply = <&vdd_5v0_sys>; 551*724ba675SRob Herring vin-sm0-supply = <&sys_reg>; 552*724ba675SRob Herring vin-sm1-supply = <&sys_reg>; 553*724ba675SRob Herring vin-sm2-supply = <&sys_reg>; 554*724ba675SRob Herring vinldo01-supply = <&sm2_reg>; 555*724ba675SRob Herring vinldo23-supply = <&sm2_reg>; 556*724ba675SRob Herring vinldo4-supply = <&sm2_reg>; 557*724ba675SRob Herring vinldo678-supply = <&sm2_reg>; 558*724ba675SRob Herring vinldo9-supply = <&sm2_reg>; 559*724ba675SRob Herring 560*724ba675SRob Herring regulators { 561*724ba675SRob Herring sys_reg: sys { 562*724ba675SRob Herring regulator-name = "vdd_sys"; 563*724ba675SRob Herring regulator-always-on; 564*724ba675SRob Herring }; 565*724ba675SRob Herring 566*724ba675SRob Herring vdd_core: sm0 { 567*724ba675SRob Herring regulator-name = "vdd_sm0,vdd_core"; 568*724ba675SRob Herring regulator-min-microvolt = <950000>; 569*724ba675SRob Herring regulator-max-microvolt = <1300000>; 570*724ba675SRob Herring regulator-coupled-with = <&rtc_vdd &vdd_cpu>; 571*724ba675SRob Herring regulator-coupled-max-spread = <170000 550000>; 572*724ba675SRob Herring regulator-always-on; 573*724ba675SRob Herring regulator-boot-on; 574*724ba675SRob Herring 575*724ba675SRob Herring nvidia,tegra-core-regulator; 576*724ba675SRob Herring }; 577*724ba675SRob Herring 578*724ba675SRob Herring vdd_cpu: sm1 { 579*724ba675SRob Herring regulator-name = "vdd_sm1,vdd_cpu"; 580*724ba675SRob Herring regulator-min-microvolt = <750000>; 581*724ba675SRob Herring regulator-max-microvolt = <1125000>; 582*724ba675SRob Herring regulator-coupled-with = <&vdd_core &rtc_vdd>; 583*724ba675SRob Herring regulator-coupled-max-spread = <550000 550000>; 584*724ba675SRob Herring regulator-always-on; 585*724ba675SRob Herring regulator-boot-on; 586*724ba675SRob Herring 587*724ba675SRob Herring nvidia,tegra-cpu-regulator; 588*724ba675SRob Herring }; 589*724ba675SRob Herring 590*724ba675SRob Herring sm2_reg: sm2 { 591*724ba675SRob Herring regulator-name = "vdd_sm2,vin_ldo*"; 592*724ba675SRob Herring regulator-min-microvolt = <3700000>; 593*724ba675SRob Herring regulator-max-microvolt = <3700000>; 594*724ba675SRob Herring regulator-always-on; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring /* LDO0 is not connected to anything */ 598*724ba675SRob Herring 599*724ba675SRob Herring ldo1 { 600*724ba675SRob Herring regulator-name = "vdd_ldo1,avdd_pll*"; 601*724ba675SRob Herring regulator-min-microvolt = <1100000>; 602*724ba675SRob Herring regulator-max-microvolt = <1100000>; 603*724ba675SRob Herring regulator-always-on; 604*724ba675SRob Herring regulator-boot-on; 605*724ba675SRob Herring }; 606*724ba675SRob Herring 607*724ba675SRob Herring rtc_vdd: ldo2 { 608*724ba675SRob Herring regulator-name = "vdd_ldo2,vdd_rtc"; 609*724ba675SRob Herring regulator-min-microvolt = <950000>; 610*724ba675SRob Herring regulator-max-microvolt = <1300000>; 611*724ba675SRob Herring regulator-coupled-with = <&vdd_core &vdd_cpu>; 612*724ba675SRob Herring regulator-coupled-max-spread = <170000 550000>; 613*724ba675SRob Herring regulator-always-on; 614*724ba675SRob Herring regulator-boot-on; 615*724ba675SRob Herring 616*724ba675SRob Herring nvidia,tegra-rtc-regulator; 617*724ba675SRob Herring }; 618*724ba675SRob Herring 619*724ba675SRob Herring ldo3 { 620*724ba675SRob Herring regulator-name = "vdd_ldo3,avdd_usb*"; 621*724ba675SRob Herring regulator-min-microvolt = <3300000>; 622*724ba675SRob Herring regulator-max-microvolt = <3300000>; 623*724ba675SRob Herring regulator-always-on; 624*724ba675SRob Herring }; 625*724ba675SRob Herring 626*724ba675SRob Herring ldo4 { 627*724ba675SRob Herring regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 628*724ba675SRob Herring regulator-min-microvolt = <1800000>; 629*724ba675SRob Herring regulator-max-microvolt = <1800000>; 630*724ba675SRob Herring regulator-always-on; 631*724ba675SRob Herring regulator-boot-on; 632*724ba675SRob Herring }; 633*724ba675SRob Herring 634*724ba675SRob Herring vcore_emmc: ldo5 { 635*724ba675SRob Herring regulator-name = "vdd_ldo5,vcore_mmc"; 636*724ba675SRob Herring regulator-min-microvolt = <2850000>; 637*724ba675SRob Herring regulator-max-microvolt = <2850000>; 638*724ba675SRob Herring regulator-always-on; 639*724ba675SRob Herring }; 640*724ba675SRob Herring 641*724ba675SRob Herring avdd_vdac_reg: ldo6 { 642*724ba675SRob Herring regulator-name = "vdd_ldo6,avdd_vdac"; 643*724ba675SRob Herring regulator-min-microvolt = <2850000>; 644*724ba675SRob Herring regulator-max-microvolt = <2850000>; 645*724ba675SRob Herring }; 646*724ba675SRob Herring 647*724ba675SRob Herring hdmi_vdd_reg: ldo7 { 648*724ba675SRob Herring regulator-name = "vdd_ldo7,avdd_hdmi"; 649*724ba675SRob Herring regulator-min-microvolt = <3300000>; 650*724ba675SRob Herring regulator-max-microvolt = <3300000>; 651*724ba675SRob Herring }; 652*724ba675SRob Herring 653*724ba675SRob Herring hdmi_pll_reg: ldo8 { 654*724ba675SRob Herring regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 655*724ba675SRob Herring regulator-min-microvolt = <1800000>; 656*724ba675SRob Herring regulator-max-microvolt = <1800000>; 657*724ba675SRob Herring }; 658*724ba675SRob Herring 659*724ba675SRob Herring ldo9 { 660*724ba675SRob Herring regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 661*724ba675SRob Herring regulator-min-microvolt = <2850000>; 662*724ba675SRob Herring regulator-max-microvolt = <2850000>; 663*724ba675SRob Herring regulator-always-on; 664*724ba675SRob Herring regulator-boot-on; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring ldo_rtc { 668*724ba675SRob Herring regulator-name = "vdd_rtc_out,vdd_cell"; 669*724ba675SRob Herring regulator-min-microvolt = <3300000>; 670*724ba675SRob Herring regulator-max-microvolt = <3300000>; 671*724ba675SRob Herring regulator-always-on; 672*724ba675SRob Herring regulator-boot-on; 673*724ba675SRob Herring }; 674*724ba675SRob Herring }; 675*724ba675SRob Herring }; 676*724ba675SRob Herring 677*724ba675SRob Herring nct1008: temperature-sensor@4c { 678*724ba675SRob Herring compatible = "onnn,nct1008"; 679*724ba675SRob Herring reg = <0x4c>; 680*724ba675SRob Herring vcc-supply = <&vdd_3v3_sys>; 681*724ba675SRob Herring 682*724ba675SRob Herring interrupt-parent = <&gpio>; 683*724ba675SRob Herring interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>; 684*724ba675SRob Herring 685*724ba675SRob Herring #thermal-sensor-cells = <1>; 686*724ba675SRob Herring }; 687*724ba675SRob Herring }; 688*724ba675SRob Herring 689*724ba675SRob Herring pmc@7000e400 { 690*724ba675SRob Herring nvidia,invert-interrupt; 691*724ba675SRob Herring nvidia,suspend-mode = <1>; 692*724ba675SRob Herring nvidia,cpu-pwr-good-time = <2000>; 693*724ba675SRob Herring nvidia,cpu-pwr-off-time = <100>; 694*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 695*724ba675SRob Herring nvidia,core-pwr-off-time = <458>; 696*724ba675SRob Herring nvidia,sys-clock-req-active-high; 697*724ba675SRob Herring core-supply = <&vdd_core>; 698*724ba675SRob Herring }; 699*724ba675SRob Herring 700*724ba675SRob Herring memory-controller@7000f400 { 701*724ba675SRob Herring nvidia,use-ram-code; 702*724ba675SRob Herring 703*724ba675SRob Herring emc-tables@0 { 704*724ba675SRob Herring nvidia,ram-code = <0>; /* elpida-8gb */ 705*724ba675SRob Herring reg = <0>; 706*724ba675SRob Herring 707*724ba675SRob Herring #address-cells = <1>; 708*724ba675SRob Herring #size-cells = <0>; 709*724ba675SRob Herring 710*724ba675SRob Herring emc-table@25000 { 711*724ba675SRob Herring reg = <25000>; 712*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 713*724ba675SRob Herring clock-frequency = <25000>; 714*724ba675SRob Herring nvidia,emc-registers = <0x00000002 0x00000006 715*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 716*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 717*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000004 718*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000004d 719*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 720*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000004 721*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 722*724ba675SRob Herring 0x00000002 0x00000068 0x00000000 0x00000003 723*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 724*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000003 725*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 726*724ba675SRob Herring }; 727*724ba675SRob Herring 728*724ba675SRob Herring emc-table@50000 { 729*724ba675SRob Herring reg = <50000>; 730*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 731*724ba675SRob Herring clock-frequency = <50000>; 732*724ba675SRob Herring nvidia,emc-registers = <0x00000003 0x00000007 733*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 734*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 735*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 736*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000009f 737*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 738*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000007 739*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 740*724ba675SRob Herring 0x00000002 0x000000d0 0x00000000 0x00000000 741*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 742*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000005 743*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 744*724ba675SRob Herring }; 745*724ba675SRob Herring 746*724ba675SRob Herring emc-table@75000 { 747*724ba675SRob Herring reg = <75000>; 748*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 749*724ba675SRob Herring clock-frequency = <75000>; 750*724ba675SRob Herring nvidia,emc-registers = <0x00000005 0x0000000a 751*724ba675SRob Herring 0x00000004 0x00000003 0x00000006 0x00000004 752*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 753*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 754*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x000000ff 755*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 756*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x0000000b 757*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 758*724ba675SRob Herring 0x00000002 0x00000138 0x00000000 0x00000000 759*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 760*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000007 761*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring emc-table@150000 { 765*724ba675SRob Herring reg = <150000>; 766*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 767*724ba675SRob Herring clock-frequency = <150000>; 768*724ba675SRob Herring nvidia,emc-registers = <0x00000009 0x00000014 769*724ba675SRob Herring 0x00000007 0x00000003 0x00000006 0x00000004 770*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 771*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 772*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000021f 773*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 774*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000015 775*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 776*724ba675SRob Herring 0x00000002 0x00000270 0x00000000 0x00000001 777*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa07c04ae 778*724ba675SRob Herring 0x007dd510 0x00000000 0x00000000 0x0000000e 779*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 780*724ba675SRob Herring }; 781*724ba675SRob Herring 782*724ba675SRob Herring emc-table@300000 { 783*724ba675SRob Herring reg = <300000>; 784*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 785*724ba675SRob Herring clock-frequency = <300000>; 786*724ba675SRob Herring nvidia,emc-registers = <0x00000012 0x00000027 787*724ba675SRob Herring 0x0000000d 0x00000006 0x00000007 0x00000005 788*724ba675SRob Herring 0x00000003 0x00000009 0x00000006 0x00000006 789*724ba675SRob Herring 0x00000003 0x00000003 0x00000002 0x00000006 790*724ba675SRob Herring 0x00000003 0x00000009 0x0000000c 0x0000045f 791*724ba675SRob Herring 0x00000000 0x00000004 0x00000004 0x00000006 792*724ba675SRob Herring 0x00000008 0x00000001 0x0000000e 0x0000002a 793*724ba675SRob Herring 0x00000003 0x0000000f 0x00000007 0x00000005 794*724ba675SRob Herring 0x00000002 0x000004e1 0x00000005 0x00000002 795*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xe059048b 796*724ba675SRob Herring 0x007e1510 0x00000000 0x00000000 0x0000001b 797*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 798*724ba675SRob Herring }; 799*724ba675SRob Herring }; 800*724ba675SRob Herring 801*724ba675SRob Herring emc-tables@1 { 802*724ba675SRob Herring nvidia,ram-code = <1>; /* elpida-4gb */ 803*724ba675SRob Herring reg = <1>; 804*724ba675SRob Herring 805*724ba675SRob Herring #address-cells = <1>; 806*724ba675SRob Herring #size-cells = <0>; 807*724ba675SRob Herring 808*724ba675SRob Herring emc-table@25000 { 809*724ba675SRob Herring reg = <25000>; 810*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 811*724ba675SRob Herring clock-frequency = <25000>; 812*724ba675SRob Herring nvidia,emc-registers = <0x00000002 0x00000006 813*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 814*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 815*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000004 816*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000004d 817*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 818*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000004 819*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 820*724ba675SRob Herring 0x00000002 0x00000068 0x00000000 0x00000003 821*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 822*724ba675SRob Herring 0x0007c000 0x00000000 0x00000000 0x00000003 823*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 824*724ba675SRob Herring }; 825*724ba675SRob Herring 826*724ba675SRob Herring emc-table@50000 { 827*724ba675SRob Herring reg = <50000>; 828*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 829*724ba675SRob Herring clock-frequency = <50000>; 830*724ba675SRob Herring nvidia,emc-registers = <0x00000003 0x00000007 831*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 832*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 833*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 834*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000009f 835*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 836*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000007 837*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 838*724ba675SRob Herring 0x00000002 0x000000d0 0x00000000 0x00000000 839*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 840*724ba675SRob Herring 0x0007c000 0x00000000 0x00000000 0x00000005 841*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 842*724ba675SRob Herring }; 843*724ba675SRob Herring 844*724ba675SRob Herring emc-table@75000 { 845*724ba675SRob Herring reg = <75000>; 846*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 847*724ba675SRob Herring clock-frequency = <75000>; 848*724ba675SRob Herring nvidia,emc-registers = <0x00000005 0x0000000a 849*724ba675SRob Herring 0x00000004 0x00000003 0x00000006 0x00000004 850*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 851*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 852*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x000000ff 853*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 854*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x0000000b 855*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 856*724ba675SRob Herring 0x00000002 0x00000138 0x00000000 0x00000000 857*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 858*724ba675SRob Herring 0x0007c000 0x00000000 0x00000000 0x00000007 859*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 860*724ba675SRob Herring }; 861*724ba675SRob Herring 862*724ba675SRob Herring emc-table@150000 { 863*724ba675SRob Herring reg = <150000>; 864*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 865*724ba675SRob Herring clock-frequency = <150000>; 866*724ba675SRob Herring nvidia,emc-registers = <0x00000009 0x00000014 867*724ba675SRob Herring 0x00000007 0x00000003 0x00000006 0x00000004 868*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 869*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 870*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000021f 871*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 872*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000015 873*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 874*724ba675SRob Herring 0x00000002 0x00000270 0x00000000 0x00000001 875*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa07c04ae 876*724ba675SRob Herring 0x007e4010 0x00000000 0x00000000 0x0000000e 877*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 878*724ba675SRob Herring }; 879*724ba675SRob Herring 880*724ba675SRob Herring emc-table@300000 { 881*724ba675SRob Herring reg = <300000>; 882*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 883*724ba675SRob Herring clock-frequency = <300000>; 884*724ba675SRob Herring nvidia,emc-registers = <0x00000012 0x00000027 885*724ba675SRob Herring 0x0000000d 0x00000006 0x00000007 0x00000005 886*724ba675SRob Herring 0x00000003 0x00000009 0x00000006 0x00000006 887*724ba675SRob Herring 0x00000003 0x00000003 0x00000002 0x00000006 888*724ba675SRob Herring 0x00000003 0x00000009 0x0000000c 0x0000045f 889*724ba675SRob Herring 0x00000000 0x00000004 0x00000004 0x00000006 890*724ba675SRob Herring 0x00000008 0x00000001 0x0000000e 0x0000002a 891*724ba675SRob Herring 0x00000003 0x0000000f 0x00000007 0x00000005 892*724ba675SRob Herring 0x00000002 0x000004e1 0x00000005 0x00000002 893*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xe059048b 894*724ba675SRob Herring 0x007e0010 0x00000000 0x00000000 0x0000001b 895*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 896*724ba675SRob Herring }; 897*724ba675SRob Herring }; 898*724ba675SRob Herring 899*724ba675SRob Herring emc-tables@2 { 900*724ba675SRob Herring nvidia,ram-code = <2>; /* hynix-8gb */ 901*724ba675SRob Herring reg = <2>; 902*724ba675SRob Herring 903*724ba675SRob Herring #address-cells = <1>; 904*724ba675SRob Herring #size-cells = <0>; 905*724ba675SRob Herring 906*724ba675SRob Herring emc-table@25000 { 907*724ba675SRob Herring reg = <25000>; 908*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 909*724ba675SRob Herring clock-frequency = <25000>; 910*724ba675SRob Herring nvidia,emc-registers = <0x00000002 0x00000006 911*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 912*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 913*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000004 914*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000004d 915*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 916*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000004 917*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 918*724ba675SRob Herring 0x00000002 0x00000068 0x00000000 0x00000003 919*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 920*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000003 921*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 922*724ba675SRob Herring }; 923*724ba675SRob Herring 924*724ba675SRob Herring emc-table@50000 { 925*724ba675SRob Herring reg = <50000>; 926*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 927*724ba675SRob Herring clock-frequency = <50000>; 928*724ba675SRob Herring nvidia,emc-registers = <0x00000003 0x00000007 929*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 930*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 931*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 932*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000009f 933*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 934*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000007 935*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 936*724ba675SRob Herring 0x00000002 0x000000d0 0x00000000 0x00000000 937*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 938*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000005 939*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 940*724ba675SRob Herring }; 941*724ba675SRob Herring 942*724ba675SRob Herring emc-table@75000 { 943*724ba675SRob Herring reg = <75000>; 944*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 945*724ba675SRob Herring clock-frequency = <75000>; 946*724ba675SRob Herring nvidia,emc-registers = <0x00000005 0x0000000a 947*724ba675SRob Herring 0x00000004 0x00000003 0x00000006 0x00000004 948*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 949*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 950*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x000000ff 951*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 952*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x0000000b 953*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 954*724ba675SRob Herring 0x00000002 0x00000138 0x00000000 0x00000000 955*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 956*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000007 957*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 958*724ba675SRob Herring }; 959*724ba675SRob Herring 960*724ba675SRob Herring emc-table@150000 { 961*724ba675SRob Herring reg = <150000>; 962*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 963*724ba675SRob Herring clock-frequency = <150000>; 964*724ba675SRob Herring nvidia,emc-registers = <0x00000009 0x00000014 965*724ba675SRob Herring 0x00000007 0x00000003 0x00000006 0x00000004 966*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 967*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 968*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000021f 969*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 970*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000015 971*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 972*724ba675SRob Herring 0x00000002 0x00000270 0x00000000 0x00000001 973*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa07c04ae 974*724ba675SRob Herring 0x007dd010 0x00000000 0x00000000 0x0000000e 975*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 976*724ba675SRob Herring }; 977*724ba675SRob Herring 978*724ba675SRob Herring emc-table@300000 { 979*724ba675SRob Herring reg = <300000>; 980*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 981*724ba675SRob Herring clock-frequency = <300000>; 982*724ba675SRob Herring nvidia,emc-registers = <0x00000012 0x00000027 983*724ba675SRob Herring 0x0000000d 0x00000006 0x00000007 0x00000005 984*724ba675SRob Herring 0x00000003 0x00000009 0x00000006 0x00000006 985*724ba675SRob Herring 0x00000003 0x00000003 0x00000002 0x00000006 986*724ba675SRob Herring 0x00000003 0x00000009 0x0000000c 0x0000045f 987*724ba675SRob Herring 0x00000000 0x00000004 0x00000004 0x00000006 988*724ba675SRob Herring 0x00000008 0x00000001 0x0000000e 0x0000002a 989*724ba675SRob Herring 0x00000003 0x0000000f 0x00000007 0x00000005 990*724ba675SRob Herring 0x00000002 0x000004e1 0x00000005 0x00000002 991*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xe059048b 992*724ba675SRob Herring 0x007e2010 0x00000000 0x00000000 0x0000001b 993*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 994*724ba675SRob Herring }; 995*724ba675SRob Herring }; 996*724ba675SRob Herring 997*724ba675SRob Herring emc-tables@3 { 998*724ba675SRob Herring nvidia,ram-code = <3>; /* hynix-4gb */ 999*724ba675SRob Herring reg = <3>; 1000*724ba675SRob Herring 1001*724ba675SRob Herring #address-cells = <1>; 1002*724ba675SRob Herring #size-cells = <0>; 1003*724ba675SRob Herring 1004*724ba675SRob Herring emc-table@25000 { 1005*724ba675SRob Herring reg = <25000>; 1006*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 1007*724ba675SRob Herring clock-frequency = <25000>; 1008*724ba675SRob Herring nvidia,emc-registers = <0x00000002 0x00000006 1009*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 1010*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 1011*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000004 1012*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000004d 1013*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 1014*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000004 1015*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 1016*724ba675SRob Herring 0x00000002 0x00000068 0x00000000 0x00000003 1017*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1018*724ba675SRob Herring 0x0007c000 0x00000000 0x00000000 0x00000003 1019*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 1020*724ba675SRob Herring }; 1021*724ba675SRob Herring 1022*724ba675SRob Herring emc-table@50000 { 1023*724ba675SRob Herring reg = <50000>; 1024*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 1025*724ba675SRob Herring clock-frequency = <50000>; 1026*724ba675SRob Herring nvidia,emc-registers = <0x00000003 0x00000007 1027*724ba675SRob Herring 0x00000003 0x00000003 0x00000006 0x00000004 1028*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 1029*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 1030*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000009f 1031*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 1032*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000007 1033*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 1034*724ba675SRob Herring 0x00000002 0x000000d0 0x00000000 0x00000000 1035*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1036*724ba675SRob Herring 0x0007c000 0x00078000 0x00000000 0x00000005 1037*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 1038*724ba675SRob Herring }; 1039*724ba675SRob Herring 1040*724ba675SRob Herring emc-table@75000 { 1041*724ba675SRob Herring reg = <75000>; 1042*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 1043*724ba675SRob Herring clock-frequency = <75000>; 1044*724ba675SRob Herring nvidia,emc-registers = <0x00000005 0x0000000a 1045*724ba675SRob Herring 0x00000004 0x00000003 0x00000006 0x00000004 1046*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 1047*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 1048*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x000000ff 1049*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 1050*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x0000000b 1051*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 1052*724ba675SRob Herring 0x00000002 0x00000138 0x00000000 0x00000000 1053*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1054*724ba675SRob Herring 0x0007c000 0x00000000 0x00000000 0x00000007 1055*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 1056*724ba675SRob Herring }; 1057*724ba675SRob Herring 1058*724ba675SRob Herring emc-table@150000 { 1059*724ba675SRob Herring reg = <150000>; 1060*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 1061*724ba675SRob Herring clock-frequency = <150000>; 1062*724ba675SRob Herring nvidia,emc-registers = <0x00000009 0x00000014 1063*724ba675SRob Herring 0x00000007 0x00000003 0x00000006 0x00000004 1064*724ba675SRob Herring 0x00000002 0x00000009 0x00000003 0x00000003 1065*724ba675SRob Herring 0x00000002 0x00000002 0x00000002 0x00000005 1066*724ba675SRob Herring 0x00000003 0x00000008 0x0000000b 0x0000021f 1067*724ba675SRob Herring 0x00000000 0x00000003 0x00000003 0x00000003 1068*724ba675SRob Herring 0x00000008 0x00000001 0x0000000a 0x00000015 1069*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000006 1070*724ba675SRob Herring 0x00000002 0x00000270 0x00000000 0x00000001 1071*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xa07c04ae 1072*724ba675SRob Herring 0x007e4010 0x00000000 0x00000000 0x0000000e 1073*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 1074*724ba675SRob Herring }; 1075*724ba675SRob Herring 1076*724ba675SRob Herring emc-table@300000 { 1077*724ba675SRob Herring reg = <300000>; 1078*724ba675SRob Herring compatible = "nvidia,tegra20-emc-table"; 1079*724ba675SRob Herring clock-frequency = <300000>; 1080*724ba675SRob Herring nvidia,emc-registers = <0x00000012 0x00000027 1081*724ba675SRob Herring 0x0000000d 0x00000006 0x00000007 0x00000005 1082*724ba675SRob Herring 0x00000003 0x00000009 0x00000006 0x00000006 1083*724ba675SRob Herring 0x00000003 0x00000003 0x00000002 0x00000006 1084*724ba675SRob Herring 0x00000003 0x00000009 0x0000000c 0x0000045f 1085*724ba675SRob Herring 0x00000000 0x00000004 0x00000004 0x00000006 1086*724ba675SRob Herring 0x00000008 0x00000001 0x0000000e 0x0000002a 1087*724ba675SRob Herring 0x00000003 0x0000000f 0x00000007 0x00000005 1088*724ba675SRob Herring 0x00000002 0x000004e1 0x00000005 0x00000002 1089*724ba675SRob Herring 0x00000000 0x00000000 0x00000282 0xe059048b 1090*724ba675SRob Herring 0x007e0010 0x00000000 0x00000000 0x0000001b 1091*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000>; 1092*724ba675SRob Herring }; 1093*724ba675SRob Herring }; 1094*724ba675SRob Herring }; 1095*724ba675SRob Herring 1096*724ba675SRob Herring usb@c5000000 { 1097*724ba675SRob Herring compatible = "nvidia,tegra20-udc"; 1098*724ba675SRob Herring status = "okay"; 1099*724ba675SRob Herring dr_mode = "peripheral"; 1100*724ba675SRob Herring }; 1101*724ba675SRob Herring 1102*724ba675SRob Herring usb-phy@c5000000 { 1103*724ba675SRob Herring status = "okay"; 1104*724ba675SRob Herring dr_mode = "peripheral"; 1105*724ba675SRob Herring nvidia,xcvr-setup-use-fuses; 1106*724ba675SRob Herring nvidia,xcvr-lsfslew = <2>; 1107*724ba675SRob Herring nvidia,xcvr-lsrslew = <2>; 1108*724ba675SRob Herring }; 1109*724ba675SRob Herring 1110*724ba675SRob Herring usb@c5008000 { 1111*724ba675SRob Herring status = "okay"; 1112*724ba675SRob Herring }; 1113*724ba675SRob Herring 1114*724ba675SRob Herring usb-phy@c5008000 { 1115*724ba675SRob Herring status = "okay"; 1116*724ba675SRob Herring nvidia,xcvr-setup-use-fuses; 1117*724ba675SRob Herring nvidia,xcvr-lsfslew = <2>; 1118*724ba675SRob Herring nvidia,xcvr-lsrslew = <2>; 1119*724ba675SRob Herring vbus-supply = <&vdd_5v0_sys>; 1120*724ba675SRob Herring }; 1121*724ba675SRob Herring 1122*724ba675SRob Herring sdmmc1: mmc@c8000000 { 1123*724ba675SRob Herring status = "okay"; 1124*724ba675SRob Herring 1125*724ba675SRob Herring #address-cells = <1>; 1126*724ba675SRob Herring #size-cells = <0>; 1127*724ba675SRob Herring 1128*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 1129*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; 1130*724ba675SRob Herring assigned-clock-rates = <50000000>; 1131*724ba675SRob Herring 1132*724ba675SRob Herring max-frequency = <50000000>; 1133*724ba675SRob Herring keep-power-in-suspend; 1134*724ba675SRob Herring bus-width = <4>; 1135*724ba675SRob Herring non-removable; 1136*724ba675SRob Herring 1137*724ba675SRob Herring mmc-pwrseq = <&brcm_wifi_pwrseq>; 1138*724ba675SRob Herring vmmc-supply = <&vdd_3v3_sys>; 1139*724ba675SRob Herring vqmmc-supply = <&vdd_1v8_sys>; 1140*724ba675SRob Herring 1141*724ba675SRob Herring /* Azurewave AW-NH611 BCM4329 */ 1142*724ba675SRob Herring wifi@1 { 1143*724ba675SRob Herring reg = <1>; 1144*724ba675SRob Herring compatible = "brcm,bcm4329-fmac"; 1145*724ba675SRob Herring interrupt-parent = <&gpio>; 1146*724ba675SRob Herring interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; 1147*724ba675SRob Herring interrupt-names = "host-wake"; 1148*724ba675SRob Herring }; 1149*724ba675SRob Herring }; 1150*724ba675SRob Herring 1151*724ba675SRob Herring sdmmc3: mmc@c8000400 { 1152*724ba675SRob Herring status = "okay"; 1153*724ba675SRob Herring bus-width = <4>; 1154*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 1155*724ba675SRob Herring power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 1156*724ba675SRob Herring vmmc-supply = <&vdd_3v3_sys>; 1157*724ba675SRob Herring vqmmc-supply = <&vdd_3v3_sys>; 1158*724ba675SRob Herring }; 1159*724ba675SRob Herring 1160*724ba675SRob Herring sdmmc4: mmc@c8000600 { 1161*724ba675SRob Herring status = "okay"; 1162*724ba675SRob Herring bus-width = <8>; 1163*724ba675SRob Herring vmmc-supply = <&vcore_emmc>; 1164*724ba675SRob Herring vqmmc-supply = <&vdd_3v3_sys>; 1165*724ba675SRob Herring non-removable; 1166*724ba675SRob Herring }; 1167*724ba675SRob Herring 1168*724ba675SRob Herring mains: ac-adapter-detect { 1169*724ba675SRob Herring compatible = "gpio-charger"; 1170*724ba675SRob Herring charger-type = "mains"; 1171*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring 1174*724ba675SRob Herring backlight: backlight { 1175*724ba675SRob Herring compatible = "pwm-backlight"; 1176*724ba675SRob Herring 1177*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 1178*724ba675SRob Herring power-supply = <&vdd_3v3_sys>; 1179*724ba675SRob Herring pwms = <&pwm 2 41667>; 1180*724ba675SRob Herring 1181*724ba675SRob Herring brightness-levels = <7 255>; 1182*724ba675SRob Herring num-interpolated-steps = <248>; 1183*724ba675SRob Herring default-brightness-level = <20>; 1184*724ba675SRob Herring }; 1185*724ba675SRob Herring 1186*724ba675SRob Herring bat1010: battery-2s1p { 1187*724ba675SRob Herring compatible = "simple-battery"; 1188*724ba675SRob Herring charge-full-design-microamp-hours = <3260000>; 1189*724ba675SRob Herring energy-full-design-microwatt-hours = <24000000>; 1190*724ba675SRob Herring operating-range-celsius = <0 40>; 1191*724ba675SRob Herring }; 1192*724ba675SRob Herring 1193*724ba675SRob Herring /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1194*724ba675SRob Herring clk32k_in: clock-32k-in { 1195*724ba675SRob Herring compatible = "fixed-clock"; 1196*724ba675SRob Herring #clock-cells = <0>; 1197*724ba675SRob Herring clock-frequency = <32768>; 1198*724ba675SRob Herring clock-output-names = "tps658621-out32k"; 1199*724ba675SRob Herring }; 1200*724ba675SRob Herring 1201*724ba675SRob Herring /* 1202*724ba675SRob Herring * This standalone onboard fixed-clock always-ON 32KHz 1203*724ba675SRob Herring * oscillator is used as a reference clock-source by the 1204*724ba675SRob Herring * Azurewave WiFi/BT module. 1205*724ba675SRob Herring */ 1206*724ba675SRob Herring rtc_32k_wifi: clock-32k-wifi { 1207*724ba675SRob Herring compatible = "fixed-clock"; 1208*724ba675SRob Herring #clock-cells = <0>; 1209*724ba675SRob Herring clock-frequency = <32768>; 1210*724ba675SRob Herring clock-output-names = "kk3270032"; 1211*724ba675SRob Herring }; 1212*724ba675SRob Herring 1213*724ba675SRob Herring cpus { 1214*724ba675SRob Herring cpu0: cpu@0 { 1215*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1216*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1217*724ba675SRob Herring #cooling-cells = <2>; 1218*724ba675SRob Herring }; 1219*724ba675SRob Herring 1220*724ba675SRob Herring cpu1: cpu@1 { 1221*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 1222*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 1223*724ba675SRob Herring #cooling-cells = <2>; 1224*724ba675SRob Herring }; 1225*724ba675SRob Herring }; 1226*724ba675SRob Herring 1227*724ba675SRob Herring display-panel { 1228*724ba675SRob Herring compatible = "auo,b101ew05", "panel-lvds"; 1229*724ba675SRob Herring 1230*724ba675SRob Herring ddc-i2c-bus = <&panel_ddc>; 1231*724ba675SRob Herring power-supply = <&vdd_pnl>; 1232*724ba675SRob Herring backlight = <&backlight>; 1233*724ba675SRob Herring 1234*724ba675SRob Herring width-mm = <218>; 1235*724ba675SRob Herring height-mm = <135>; 1236*724ba675SRob Herring 1237*724ba675SRob Herring data-mapping = "jeida-18"; 1238*724ba675SRob Herring 1239*724ba675SRob Herring panel-timing { 1240*724ba675SRob Herring clock-frequency = <71200000>; 1241*724ba675SRob Herring hactive = <1280>; 1242*724ba675SRob Herring vactive = <800>; 1243*724ba675SRob Herring hfront-porch = <8>; 1244*724ba675SRob Herring hback-porch = <18>; 1245*724ba675SRob Herring hsync-len = <184>; 1246*724ba675SRob Herring vsync-len = <3>; 1247*724ba675SRob Herring vfront-porch = <4>; 1248*724ba675SRob Herring vback-porch = <8>; 1249*724ba675SRob Herring }; 1250*724ba675SRob Herring 1251*724ba675SRob Herring port { 1252*724ba675SRob Herring panel_input: endpoint { 1253*724ba675SRob Herring remote-endpoint = <&lvds_encoder_output>; 1254*724ba675SRob Herring }; 1255*724ba675SRob Herring }; 1256*724ba675SRob Herring }; 1257*724ba675SRob Herring 1258*724ba675SRob Herring gpio-keys { 1259*724ba675SRob Herring compatible = "gpio-keys"; 1260*724ba675SRob Herring 1261*724ba675SRob Herring key-power { 1262*724ba675SRob Herring label = "Power"; 1263*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; 1264*724ba675SRob Herring linux,code = <KEY_POWER>; 1265*724ba675SRob Herring debounce-interval = <10>; 1266*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1267*724ba675SRob Herring wakeup-source; 1268*724ba675SRob Herring }; 1269*724ba675SRob Herring 1270*724ba675SRob Herring key-rotation-lock { 1271*724ba675SRob Herring label = "Rotate-lock"; 1272*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; 1273*724ba675SRob Herring linux,code = <SW_ROTATE_LOCK>; 1274*724ba675SRob Herring linux,input-type = <EV_SW>; 1275*724ba675SRob Herring debounce-interval = <10>; 1276*724ba675SRob Herring }; 1277*724ba675SRob Herring 1278*724ba675SRob Herring key-volume-down { 1279*724ba675SRob Herring label = "Volume Down"; 1280*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; 1281*724ba675SRob Herring linux,code = <KEY_VOLUMEDOWN>; 1282*724ba675SRob Herring debounce-interval = <10>; 1283*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1284*724ba675SRob Herring wakeup-source; 1285*724ba675SRob Herring }; 1286*724ba675SRob Herring 1287*724ba675SRob Herring key-volume-up { 1288*724ba675SRob Herring label = "Volume Up"; 1289*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 1290*724ba675SRob Herring linux,code = <KEY_VOLUMEUP>; 1291*724ba675SRob Herring debounce-interval = <10>; 1292*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 1293*724ba675SRob Herring wakeup-source; 1294*724ba675SRob Herring }; 1295*724ba675SRob Herring }; 1296*724ba675SRob Herring 1297*724ba675SRob Herring haptic-feedback { 1298*724ba675SRob Herring compatible = "gpio-vibrator"; 1299*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 1300*724ba675SRob Herring vcc-supply = <&vdd_3v3_sys>; 1301*724ba675SRob Herring }; 1302*724ba675SRob Herring 1303*724ba675SRob Herring i2cmux { 1304*724ba675SRob Herring compatible = "i2c-mux-pinctrl"; 1305*724ba675SRob Herring #address-cells = <1>; 1306*724ba675SRob Herring #size-cells = <0>; 1307*724ba675SRob Herring 1308*724ba675SRob Herring i2c-parent = <&{/i2c@7000c400}>; 1309*724ba675SRob Herring 1310*724ba675SRob Herring pinctrl-names = "ddc", "pta", "idle"; 1311*724ba675SRob Herring pinctrl-0 = <&state_i2cmux_ddc>; 1312*724ba675SRob Herring pinctrl-1 = <&state_i2cmux_pta>; 1313*724ba675SRob Herring pinctrl-2 = <&state_i2cmux_idle>; 1314*724ba675SRob Herring 1315*724ba675SRob Herring hdmi_ddc: i2c@0 { 1316*724ba675SRob Herring reg = <0>; 1317*724ba675SRob Herring #address-cells = <1>; 1318*724ba675SRob Herring #size-cells = <0>; 1319*724ba675SRob Herring }; 1320*724ba675SRob Herring 1321*724ba675SRob Herring panel_ddc: i2c@1 { 1322*724ba675SRob Herring reg = <1>; 1323*724ba675SRob Herring #address-cells = <1>; 1324*724ba675SRob Herring #size-cells = <0>; 1325*724ba675SRob Herring 1326*724ba675SRob Herring embedded-controller@58 { 1327*724ba675SRob Herring compatible = "acer,a500-iconia-ec", "ene,kb930"; 1328*724ba675SRob Herring reg = <0x58>; 1329*724ba675SRob Herring 1330*724ba675SRob Herring system-power-controller; 1331*724ba675SRob Herring 1332*724ba675SRob Herring monitored-battery = <&bat1010>; 1333*724ba675SRob Herring power-supplies = <&mains>; 1334*724ba675SRob Herring }; 1335*724ba675SRob Herring }; 1336*724ba675SRob Herring }; 1337*724ba675SRob Herring 1338*724ba675SRob Herring lvds-encoder { 1339*724ba675SRob Herring compatible = "ti,sn75lvds83", "lvds-encoder"; 1340*724ba675SRob Herring 1341*724ba675SRob Herring powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; 1342*724ba675SRob Herring power-supply = <&vdd_3v3_sys>; 1343*724ba675SRob Herring 1344*724ba675SRob Herring ports { 1345*724ba675SRob Herring #address-cells = <1>; 1346*724ba675SRob Herring #size-cells = <0>; 1347*724ba675SRob Herring 1348*724ba675SRob Herring port@0 { 1349*724ba675SRob Herring reg = <0>; 1350*724ba675SRob Herring 1351*724ba675SRob Herring lvds_encoder_input: endpoint { 1352*724ba675SRob Herring remote-endpoint = <&lcd_output>; 1353*724ba675SRob Herring }; 1354*724ba675SRob Herring }; 1355*724ba675SRob Herring 1356*724ba675SRob Herring port@1 { 1357*724ba675SRob Herring reg = <1>; 1358*724ba675SRob Herring 1359*724ba675SRob Herring lvds_encoder_output: endpoint { 1360*724ba675SRob Herring remote-endpoint = <&panel_input>; 1361*724ba675SRob Herring }; 1362*724ba675SRob Herring }; 1363*724ba675SRob Herring }; 1364*724ba675SRob Herring }; 1365*724ba675SRob Herring 1366*724ba675SRob Herring opp-table-emc { 1367*724ba675SRob Herring /delete-node/ opp-666000000; 1368*724ba675SRob Herring /delete-node/ opp-760000000; 1369*724ba675SRob Herring }; 1370*724ba675SRob Herring 1371*724ba675SRob Herring vdd_5v0_sys: regulator-5v0 { 1372*724ba675SRob Herring compatible = "regulator-fixed"; 1373*724ba675SRob Herring regulator-name = "vdd_5v0"; 1374*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1375*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1376*724ba675SRob Herring regulator-always-on; 1377*724ba675SRob Herring }; 1378*724ba675SRob Herring 1379*724ba675SRob Herring vdd_3v3_sys: regulator-3v3 { 1380*724ba675SRob Herring compatible = "regulator-fixed"; 1381*724ba675SRob Herring regulator-name = "vdd_3v3_vs"; 1382*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1383*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1384*724ba675SRob Herring regulator-always-on; 1385*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1386*724ba675SRob Herring }; 1387*724ba675SRob Herring 1388*724ba675SRob Herring vdd_1v8_sys: regulator-1v8 { 1389*724ba675SRob Herring compatible = "regulator-fixed"; 1390*724ba675SRob Herring regulator-name = "vdd_1v8_vs"; 1391*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1392*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1393*724ba675SRob Herring regulator-always-on; 1394*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1395*724ba675SRob Herring }; 1396*724ba675SRob Herring 1397*724ba675SRob Herring vdd_pnl: regulator-panel { 1398*724ba675SRob Herring compatible = "regulator-fixed"; 1399*724ba675SRob Herring regulator-name = "vdd_panel"; 1400*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1401*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1402*724ba675SRob Herring regulator-enable-ramp-delay = <300000>; 1403*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 1404*724ba675SRob Herring enable-active-high; 1405*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1406*724ba675SRob Herring }; 1407*724ba675SRob Herring 1408*724ba675SRob Herring sound { 1409*724ba675SRob Herring compatible = "nvidia,tegra-audio-wm8903-picasso", 1410*724ba675SRob Herring "nvidia,tegra-audio-wm8903"; 1411*724ba675SRob Herring nvidia,model = "Acer Iconia Tab A500 WM8903"; 1412*724ba675SRob Herring 1413*724ba675SRob Herring nvidia,audio-routing = 1414*724ba675SRob Herring "Headphone Jack", "HPOUTR", 1415*724ba675SRob Herring "Headphone Jack", "HPOUTL", 1416*724ba675SRob Herring "Int Spk", "LINEOUTL", 1417*724ba675SRob Herring "Int Spk", "LINEOUTR", 1418*724ba675SRob Herring "Mic Jack", "MICBIAS", 1419*724ba675SRob Herring "IN2L", "Mic Jack", 1420*724ba675SRob Herring "IN2R", "Mic Jack", 1421*724ba675SRob Herring "IN1L", "Int Mic", 1422*724ba675SRob Herring "IN1R", "Int Mic"; 1423*724ba675SRob Herring 1424*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 1425*724ba675SRob Herring nvidia,audio-codec = <&wm8903>; 1426*724ba675SRob Herring 1427*724ba675SRob Herring nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 1428*724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1429*724ba675SRob Herring nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; 1430*724ba675SRob Herring nvidia,headset; 1431*724ba675SRob Herring 1432*724ba675SRob Herring clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 1433*724ba675SRob Herring <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 1434*724ba675SRob Herring <&tegra_car TEGRA20_CLK_CDEV1>; 1435*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 1436*724ba675SRob Herring }; 1437*724ba675SRob Herring 1438*724ba675SRob Herring thermal-zones { 1439*724ba675SRob Herring /* 1440*724ba675SRob Herring * NCT1008 has two sensors: 1441*724ba675SRob Herring * 1442*724ba675SRob Herring * 0: internal that monitors ambient/skin temperature 1443*724ba675SRob Herring * 1: external that is connected to the CPU's diode 1444*724ba675SRob Herring * 1445*724ba675SRob Herring * Ideally we should use userspace thermal governor, 1446*724ba675SRob Herring * but it's a much more complex solution. The "skin" 1447*724ba675SRob Herring * zone is a simpler solution which prevents A500 from 1448*724ba675SRob Herring * getting too hot from a user's tactile perspective. 1449*724ba675SRob Herring * The CPU zone is intended to protect silicon from damage. 1450*724ba675SRob Herring */ 1451*724ba675SRob Herring 1452*724ba675SRob Herring skin-thermal { 1453*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 1454*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 1455*724ba675SRob Herring 1456*724ba675SRob Herring thermal-sensors = <&nct1008 0>; 1457*724ba675SRob Herring 1458*724ba675SRob Herring trips { 1459*724ba675SRob Herring trip0: skin-alert { 1460*724ba675SRob Herring /* start throttling at 60C */ 1461*724ba675SRob Herring temperature = <60000>; 1462*724ba675SRob Herring hysteresis = <200>; 1463*724ba675SRob Herring type = "passive"; 1464*724ba675SRob Herring }; 1465*724ba675SRob Herring 1466*724ba675SRob Herring trip1: skin-crit { 1467*724ba675SRob Herring /* shut down at 70C */ 1468*724ba675SRob Herring temperature = <70000>; 1469*724ba675SRob Herring hysteresis = <2000>; 1470*724ba675SRob Herring type = "critical"; 1471*724ba675SRob Herring }; 1472*724ba675SRob Herring }; 1473*724ba675SRob Herring 1474*724ba675SRob Herring cooling-maps { 1475*724ba675SRob Herring map0 { 1476*724ba675SRob Herring trip = <&trip0>; 1477*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1478*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1479*724ba675SRob Herring }; 1480*724ba675SRob Herring }; 1481*724ba675SRob Herring }; 1482*724ba675SRob Herring 1483*724ba675SRob Herring cpu-thermal { 1484*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 1485*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 1486*724ba675SRob Herring 1487*724ba675SRob Herring thermal-sensors = <&nct1008 1>; 1488*724ba675SRob Herring 1489*724ba675SRob Herring trips { 1490*724ba675SRob Herring trip2: cpu-alert { 1491*724ba675SRob Herring /* throttle at 85C until temperature drops to 84.8C */ 1492*724ba675SRob Herring temperature = <85000>; 1493*724ba675SRob Herring hysteresis = <200>; 1494*724ba675SRob Herring type = "passive"; 1495*724ba675SRob Herring }; 1496*724ba675SRob Herring 1497*724ba675SRob Herring trip3: cpu-crit { 1498*724ba675SRob Herring /* shut down at 90C */ 1499*724ba675SRob Herring temperature = <90000>; 1500*724ba675SRob Herring hysteresis = <2000>; 1501*724ba675SRob Herring type = "critical"; 1502*724ba675SRob Herring }; 1503*724ba675SRob Herring }; 1504*724ba675SRob Herring 1505*724ba675SRob Herring cooling-maps { 1506*724ba675SRob Herring map1 { 1507*724ba675SRob Herring trip = <&trip2>; 1508*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1509*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1510*724ba675SRob Herring }; 1511*724ba675SRob Herring }; 1512*724ba675SRob Herring }; 1513*724ba675SRob Herring }; 1514*724ba675SRob Herring 1515*724ba675SRob Herring brcm_wifi_pwrseq: wifi-pwrseq { 1516*724ba675SRob Herring compatible = "mmc-pwrseq-simple"; 1517*724ba675SRob Herring 1518*724ba675SRob Herring clocks = <&rtc_32k_wifi>; 1519*724ba675SRob Herring clock-names = "ext_clock"; 1520*724ba675SRob Herring 1521*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; 1522*724ba675SRob Herring post-power-on-delay-ms = <300>; 1523*724ba675SRob Herring power-off-delay-us = <300>; 1524*724ba675SRob Herring }; 1525*724ba675SRob Herring}; 1526