1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/input/input.h> 5*724ba675SRob Herring#include "tegra124.dtsi" 6*724ba675SRob Herring 7*724ba675SRob Herring#include "tegra124-jetson-tk1-emc.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring model = "NVIDIA Tegra124 Jetson TK1"; 11*724ba675SRob Herring compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; 12*724ba675SRob Herring 13*724ba675SRob Herring aliases { 14*724ba675SRob Herring rtc0 = "/i2c@7000d000/pmic@40"; 15*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 16*724ba675SRob Herring 17*724ba675SRob Herring /* This order keeps the mapping DB9 connector <-> ttyS0 */ 18*724ba675SRob Herring serial0 = &uartd; 19*724ba675SRob Herring serial1 = &uarta; 20*724ba675SRob Herring serial2 = &uartb; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring chosen { 24*724ba675SRob Herring stdout-path = "serial0:115200n8"; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring memory@80000000 { 28*724ba675SRob Herring reg = <0x0 0x80000000 0x0 0x80000000>; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring pcie@1003000 { 32*724ba675SRob Herring status = "okay"; 33*724ba675SRob Herring 34*724ba675SRob Herring avddio-pex-supply = <&vdd_1v05_run>; 35*724ba675SRob Herring dvddio-pex-supply = <&vdd_1v05_run>; 36*724ba675SRob Herring avdd-pex-pll-supply = <&vdd_1v05_run>; 37*724ba675SRob Herring hvdd-pex-supply = <&vdd_3v3_lp0>; 38*724ba675SRob Herring hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; 39*724ba675SRob Herring vddio-pex-ctl-supply = <&vdd_3v3_lp0>; 40*724ba675SRob Herring avdd-pll-erefe-supply = <&avdd_1v05_run>; 41*724ba675SRob Herring 42*724ba675SRob Herring /* Mini PCIe */ 43*724ba675SRob Herring pci@1,0 { 44*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 45*724ba675SRob Herring phy-names = "pcie-0"; 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring }; 48*724ba675SRob Herring 49*724ba675SRob Herring /* Gigabit Ethernet */ 50*724ba675SRob Herring pci@2,0 { 51*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 52*724ba675SRob Herring phy-names = "pcie-0"; 53*724ba675SRob Herring status = "okay"; 54*724ba675SRob Herring }; 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring host1x@50000000 { 58*724ba675SRob Herring hdmi@54280000 { 59*724ba675SRob Herring status = "okay"; 60*724ba675SRob Herring 61*724ba675SRob Herring hdmi-supply = <&vdd_5v0_hdmi>; 62*724ba675SRob Herring pll-supply = <&vdd_hdmi_pll>; 63*724ba675SRob Herring vdd-supply = <&vdd_3v3_hdmi>; 64*724ba675SRob Herring 65*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 66*724ba675SRob Herring nvidia,hpd-gpio = 67*724ba675SRob Herring <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring gpu@57000000 { 72*724ba675SRob Herring /* 73*724ba675SRob Herring * Node left disabled on purpose - the bootloader will enable 74*724ba675SRob Herring * it after having set the VPR up 75*724ba675SRob Herring */ 76*724ba675SRob Herring vdd-supply = <&vdd_gpu>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring pinmux: pinmux@70000868 { 80*724ba675SRob Herring pinctrl-names = "boot"; 81*724ba675SRob Herring pinctrl-0 = <&state_boot>; 82*724ba675SRob Herring 83*724ba675SRob Herring state_boot: pinmux { 84*724ba675SRob Herring clk_32k_out_pa0 { 85*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 86*724ba675SRob Herring nvidia,function = "soc"; 87*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 88*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 89*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring uart3_cts_n_pa1 { 92*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1"; 93*724ba675SRob Herring nvidia,function = "gmi"; 94*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 95*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 96*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring dap2_fs_pa2 { 99*724ba675SRob Herring nvidia,pins = "dap2_fs_pa2"; 100*724ba675SRob Herring nvidia,function = "i2s1"; 101*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 102*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 103*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 104*724ba675SRob Herring }; 105*724ba675SRob Herring dap2_sclk_pa3 { 106*724ba675SRob Herring nvidia,pins = "dap2_sclk_pa3"; 107*724ba675SRob Herring nvidia,function = "i2s1"; 108*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 109*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 110*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring dap2_din_pa4 { 113*724ba675SRob Herring nvidia,pins = "dap2_din_pa4"; 114*724ba675SRob Herring nvidia,function = "i2s1"; 115*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 116*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 117*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 118*724ba675SRob Herring }; 119*724ba675SRob Herring dap2_dout_pa5 { 120*724ba675SRob Herring nvidia,pins = "dap2_dout_pa5"; 121*724ba675SRob Herring nvidia,function = "i2s1"; 122*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 123*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 124*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring sdmmc3_clk_pa6 { 127*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 128*724ba675SRob Herring nvidia,function = "sdmmc3"; 129*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 130*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 131*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring sdmmc3_cmd_pa7 { 134*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7"; 135*724ba675SRob Herring nvidia,function = "sdmmc3"; 136*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 137*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 138*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring pb0 { 141*724ba675SRob Herring nvidia,pins = "pb0"; 142*724ba675SRob Herring nvidia,function = "uartd"; 143*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 144*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 145*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring pb1 { 148*724ba675SRob Herring nvidia,pins = "pb1"; 149*724ba675SRob Herring nvidia,function = "uartd"; 150*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 151*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 152*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 153*724ba675SRob Herring }; 154*724ba675SRob Herring sdmmc3_dat3_pb4 { 155*724ba675SRob Herring nvidia,pins = "sdmmc3_dat3_pb4"; 156*724ba675SRob Herring nvidia,function = "sdmmc3"; 157*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 158*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 159*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 160*724ba675SRob Herring }; 161*724ba675SRob Herring sdmmc3_dat2_pb5 { 162*724ba675SRob Herring nvidia,pins = "sdmmc3_dat2_pb5"; 163*724ba675SRob Herring nvidia,function = "sdmmc3"; 164*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 165*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 166*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167*724ba675SRob Herring }; 168*724ba675SRob Herring sdmmc3_dat1_pb6 { 169*724ba675SRob Herring nvidia,pins = "sdmmc3_dat1_pb6"; 170*724ba675SRob Herring nvidia,function = "sdmmc3"; 171*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 172*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 173*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 174*724ba675SRob Herring }; 175*724ba675SRob Herring sdmmc3_dat0_pb7 { 176*724ba675SRob Herring nvidia,pins = "sdmmc3_dat0_pb7"; 177*724ba675SRob Herring nvidia,function = "sdmmc3"; 178*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 179*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 180*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 181*724ba675SRob Herring }; 182*724ba675SRob Herring uart3_rts_n_pc0 { 183*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0"; 184*724ba675SRob Herring nvidia,function = "gmi"; 185*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 186*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 187*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 188*724ba675SRob Herring }; 189*724ba675SRob Herring uart2_txd_pc2 { 190*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2"; 191*724ba675SRob Herring nvidia,function = "irda"; 192*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 193*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 194*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 195*724ba675SRob Herring }; 196*724ba675SRob Herring uart2_rxd_pc3 { 197*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3"; 198*724ba675SRob Herring nvidia,function = "irda"; 199*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 200*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 201*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 202*724ba675SRob Herring }; 203*724ba675SRob Herring gen1_i2c_scl_pc4 { 204*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4"; 205*724ba675SRob Herring nvidia,function = "i2c1"; 206*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 207*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 208*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 209*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 210*724ba675SRob Herring }; 211*724ba675SRob Herring gen1_i2c_sda_pc5 { 212*724ba675SRob Herring nvidia,pins = "gen1_i2c_sda_pc5"; 213*724ba675SRob Herring nvidia,function = "i2c1"; 214*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 216*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 217*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring pc7 { 220*724ba675SRob Herring nvidia,pins = "pc7"; 221*724ba675SRob Herring nvidia,function = "rsvd1"; 222*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 223*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 224*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring pg0 { 227*724ba675SRob Herring nvidia,pins = "pg0"; 228*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 229*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 230*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 231*724ba675SRob Herring }; 232*724ba675SRob Herring pg1 { 233*724ba675SRob Herring nvidia,pins = "pg1"; 234*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 235*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 236*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 237*724ba675SRob Herring }; 238*724ba675SRob Herring pg2 { 239*724ba675SRob Herring nvidia,pins = "pg2"; 240*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 241*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 242*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 243*724ba675SRob Herring }; 244*724ba675SRob Herring pg3 { 245*724ba675SRob Herring nvidia,pins = "pg3"; 246*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 248*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 249*724ba675SRob Herring }; 250*724ba675SRob Herring pg4 { 251*724ba675SRob Herring nvidia,pins = "pg4"; 252*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 253*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 254*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 255*724ba675SRob Herring }; 256*724ba675SRob Herring pg5 { 257*724ba675SRob Herring nvidia,pins = "pg5"; 258*724ba675SRob Herring nvidia,function = "spi4"; 259*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 260*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 261*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 262*724ba675SRob Herring }; 263*724ba675SRob Herring pg6 { 264*724ba675SRob Herring nvidia,pins = "pg6"; 265*724ba675SRob Herring nvidia,function = "spi4"; 266*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 267*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 268*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 269*724ba675SRob Herring }; 270*724ba675SRob Herring pg7 { 271*724ba675SRob Herring nvidia,pins = "pg7"; 272*724ba675SRob Herring nvidia,function = "spi4"; 273*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 274*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 275*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring ph0 { 278*724ba675SRob Herring nvidia,pins = "ph0"; 279*724ba675SRob Herring nvidia,function = "gmi"; 280*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 281*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 282*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 283*724ba675SRob Herring }; 284*724ba675SRob Herring ph1 { 285*724ba675SRob Herring nvidia,pins = "ph1"; 286*724ba675SRob Herring nvidia,function = "pwm1"; 287*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 289*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 290*724ba675SRob Herring }; 291*724ba675SRob Herring ph2 { 292*724ba675SRob Herring nvidia,pins = "ph2"; 293*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 294*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 295*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 296*724ba675SRob Herring }; 297*724ba675SRob Herring ph3 { 298*724ba675SRob Herring nvidia,pins = "ph3"; 299*724ba675SRob Herring nvidia,function = "gmi"; 300*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 301*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 302*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring ph4 { 305*724ba675SRob Herring nvidia,pins = "ph4"; 306*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 308*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 309*724ba675SRob Herring }; 310*724ba675SRob Herring ph5 { 311*724ba675SRob Herring nvidia,pins = "ph5"; 312*724ba675SRob Herring nvidia,function = "rsvd2"; 313*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 314*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 315*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 316*724ba675SRob Herring }; 317*724ba675SRob Herring ph6 { 318*724ba675SRob Herring nvidia,pins = "ph6"; 319*724ba675SRob Herring nvidia,function = "gmi"; 320*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 321*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 322*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 323*724ba675SRob Herring }; 324*724ba675SRob Herring ph7 { 325*724ba675SRob Herring nvidia,pins = "ph7"; 326*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 327*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 328*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 329*724ba675SRob Herring }; 330*724ba675SRob Herring pi0 { 331*724ba675SRob Herring nvidia,pins = "pi0"; 332*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 333*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 334*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 335*724ba675SRob Herring }; 336*724ba675SRob Herring pi1 { 337*724ba675SRob Herring nvidia,pins = "pi1"; 338*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 339*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 340*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring pi2 { 343*724ba675SRob Herring nvidia,pins = "pi2"; 344*724ba675SRob Herring nvidia,function = "rsvd4"; 345*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 346*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 347*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 348*724ba675SRob Herring }; 349*724ba675SRob Herring pi3 { 350*724ba675SRob Herring nvidia,pins = "pi3"; 351*724ba675SRob Herring nvidia,function = "spi4"; 352*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 353*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 354*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 355*724ba675SRob Herring }; 356*724ba675SRob Herring pi4 { 357*724ba675SRob Herring nvidia,pins = "pi4"; 358*724ba675SRob Herring nvidia,function = "gmi"; 359*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 360*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 361*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 362*724ba675SRob Herring }; 363*724ba675SRob Herring pi5 { 364*724ba675SRob Herring nvidia,pins = "pi5"; 365*724ba675SRob Herring nvidia,function = "rsvd2"; 366*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 367*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 368*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 369*724ba675SRob Herring }; 370*724ba675SRob Herring pi6 { 371*724ba675SRob Herring nvidia,pins = "pi6"; 372*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 373*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 374*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375*724ba675SRob Herring }; 376*724ba675SRob Herring pi7 { 377*724ba675SRob Herring nvidia,pins = "pi7"; 378*724ba675SRob Herring nvidia,function = "rsvd1"; 379*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 380*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 381*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 382*724ba675SRob Herring }; 383*724ba675SRob Herring pj0 { 384*724ba675SRob Herring nvidia,pins = "pj0"; 385*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 386*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 387*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 388*724ba675SRob Herring }; 389*724ba675SRob Herring pj2 { 390*724ba675SRob Herring nvidia,pins = "pj2"; 391*724ba675SRob Herring nvidia,function = "rsvd1"; 392*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 393*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 394*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 395*724ba675SRob Herring }; 396*724ba675SRob Herring uart2_cts_n_pj5 { 397*724ba675SRob Herring nvidia,pins = "uart2_cts_n_pj5"; 398*724ba675SRob Herring nvidia,function = "uartb"; 399*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 400*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 401*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 402*724ba675SRob Herring }; 403*724ba675SRob Herring uart2_rts_n_pj6 { 404*724ba675SRob Herring nvidia,pins = "uart2_rts_n_pj6"; 405*724ba675SRob Herring nvidia,function = "uartb"; 406*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 407*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 408*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 409*724ba675SRob Herring }; 410*724ba675SRob Herring pj7 { 411*724ba675SRob Herring nvidia,pins = "pj7"; 412*724ba675SRob Herring nvidia,function = "uartd"; 413*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 414*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 415*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 416*724ba675SRob Herring }; 417*724ba675SRob Herring pk0 { 418*724ba675SRob Herring nvidia,pins = "pk0"; 419*724ba675SRob Herring nvidia,function = "rsvd1"; 420*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 421*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 422*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 423*724ba675SRob Herring }; 424*724ba675SRob Herring pk1 { 425*724ba675SRob Herring nvidia,pins = "pk1"; 426*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 428*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 429*724ba675SRob Herring }; 430*724ba675SRob Herring pk2 { 431*724ba675SRob Herring nvidia,pins = "pk2"; 432*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 433*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 434*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 435*724ba675SRob Herring }; 436*724ba675SRob Herring pk3 { 437*724ba675SRob Herring nvidia,pins = "pk3"; 438*724ba675SRob Herring nvidia,function = "gmi"; 439*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 440*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 441*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 442*724ba675SRob Herring }; 443*724ba675SRob Herring pk4 { 444*724ba675SRob Herring nvidia,pins = "pk4"; 445*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 446*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 447*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 448*724ba675SRob Herring }; 449*724ba675SRob Herring spdif_out_pk5 { 450*724ba675SRob Herring nvidia,pins = "spdif_out_pk5"; 451*724ba675SRob Herring nvidia,function = "rsvd2"; 452*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 453*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 454*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 455*724ba675SRob Herring }; 456*724ba675SRob Herring spdif_in_pk6 { 457*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 458*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 459*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 460*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring pk7 { 463*724ba675SRob Herring nvidia,pins = "pk7"; 464*724ba675SRob Herring nvidia,function = "uartd"; 465*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 466*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 467*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 468*724ba675SRob Herring }; 469*724ba675SRob Herring dap1_fs_pn0 { 470*724ba675SRob Herring nvidia,pins = "dap1_fs_pn0"; 471*724ba675SRob Herring nvidia,function = "rsvd4"; 472*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 473*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 474*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 475*724ba675SRob Herring }; 476*724ba675SRob Herring dap1_din_pn1 { 477*724ba675SRob Herring nvidia,pins = "dap1_din_pn1"; 478*724ba675SRob Herring nvidia,function = "rsvd4"; 479*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 480*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 481*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring dap1_dout_pn2 { 484*724ba675SRob Herring nvidia,pins = "dap1_dout_pn2"; 485*724ba675SRob Herring nvidia,function = "sata"; 486*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 487*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 488*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 489*724ba675SRob Herring }; 490*724ba675SRob Herring dap1_sclk_pn3 { 491*724ba675SRob Herring nvidia,pins = "dap1_sclk_pn3"; 492*724ba675SRob Herring nvidia,function = "rsvd4"; 493*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 494*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 495*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 496*724ba675SRob Herring }; 497*724ba675SRob Herring usb_vbus_en0_pn4 { 498*724ba675SRob Herring nvidia,pins = "usb_vbus_en0_pn4"; 499*724ba675SRob Herring nvidia,function = "usb"; 500*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 501*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 502*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 503*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 504*724ba675SRob Herring }; 505*724ba675SRob Herring usb_vbus_en1_pn5 { 506*724ba675SRob Herring nvidia,pins = "usb_vbus_en1_pn5"; 507*724ba675SRob Herring nvidia,function = "usb"; 508*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 509*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 510*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 511*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 512*724ba675SRob Herring }; 513*724ba675SRob Herring hdmi_int_pn7 { 514*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 515*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 516*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 517*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 518*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 519*724ba675SRob Herring }; 520*724ba675SRob Herring ulpi_data7_po0 { 521*724ba675SRob Herring nvidia,pins = "ulpi_data7_po0"; 522*724ba675SRob Herring nvidia,function = "ulpi"; 523*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 524*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 525*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 526*724ba675SRob Herring }; 527*724ba675SRob Herring ulpi_data0_po1 { 528*724ba675SRob Herring nvidia,pins = "ulpi_data0_po1"; 529*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 530*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 531*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 532*724ba675SRob Herring }; 533*724ba675SRob Herring ulpi_data1_po2 { 534*724ba675SRob Herring nvidia,pins = "ulpi_data1_po2"; 535*724ba675SRob Herring nvidia,function = "ulpi"; 536*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 537*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 538*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 539*724ba675SRob Herring }; 540*724ba675SRob Herring ulpi_data2_po3 { 541*724ba675SRob Herring nvidia,pins = "ulpi_data2_po3"; 542*724ba675SRob Herring nvidia,function = "ulpi"; 543*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 544*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 545*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 546*724ba675SRob Herring }; 547*724ba675SRob Herring ulpi_data3_po4 { 548*724ba675SRob Herring nvidia,pins = "ulpi_data3_po4"; 549*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 550*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 551*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 552*724ba675SRob Herring }; 553*724ba675SRob Herring ulpi_data4_po5 { 554*724ba675SRob Herring nvidia,pins = "ulpi_data4_po5"; 555*724ba675SRob Herring nvidia,function = "ulpi"; 556*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 557*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 558*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 559*724ba675SRob Herring }; 560*724ba675SRob Herring ulpi_data5_po6 { 561*724ba675SRob Herring nvidia,pins = "ulpi_data5_po6"; 562*724ba675SRob Herring nvidia,function = "ulpi"; 563*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 564*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 565*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 566*724ba675SRob Herring }; 567*724ba675SRob Herring ulpi_data6_po7 { 568*724ba675SRob Herring nvidia,pins = "ulpi_data6_po7"; 569*724ba675SRob Herring nvidia,function = "ulpi"; 570*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 571*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 572*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 573*724ba675SRob Herring }; 574*724ba675SRob Herring dap3_fs_pp0 { 575*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0"; 576*724ba675SRob Herring nvidia,function = "i2s2"; 577*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 578*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 579*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 580*724ba675SRob Herring }; 581*724ba675SRob Herring dap3_din_pp1 { 582*724ba675SRob Herring nvidia,pins = "dap3_din_pp1"; 583*724ba675SRob Herring nvidia,function = "i2s2"; 584*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 585*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 586*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 587*724ba675SRob Herring }; 588*724ba675SRob Herring dap3_dout_pp2 { 589*724ba675SRob Herring nvidia,pins = "dap3_dout_pp2"; 590*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 591*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 592*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring dap3_sclk_pp3 { 595*724ba675SRob Herring nvidia,pins = "dap3_sclk_pp3"; 596*724ba675SRob Herring nvidia,function = "rsvd3"; 597*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 598*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 599*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 600*724ba675SRob Herring }; 601*724ba675SRob Herring dap4_fs_pp4 { 602*724ba675SRob Herring nvidia,pins = "dap4_fs_pp4"; 603*724ba675SRob Herring nvidia,function = "rsvd4"; 604*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 605*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 606*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 607*724ba675SRob Herring }; 608*724ba675SRob Herring dap4_din_pp5 { 609*724ba675SRob Herring nvidia,pins = "dap4_din_pp5"; 610*724ba675SRob Herring nvidia,function = "rsvd3"; 611*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 612*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 613*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 614*724ba675SRob Herring }; 615*724ba675SRob Herring dap4_dout_pp6 { 616*724ba675SRob Herring nvidia,pins = "dap4_dout_pp6"; 617*724ba675SRob Herring nvidia,function = "rsvd4"; 618*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 619*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 620*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 621*724ba675SRob Herring }; 622*724ba675SRob Herring dap4_sclk_pp7 { 623*724ba675SRob Herring nvidia,pins = "dap4_sclk_pp7"; 624*724ba675SRob Herring nvidia,function = "rsvd3"; 625*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 626*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 627*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 628*724ba675SRob Herring }; 629*724ba675SRob Herring kb_col0_pq0 { 630*724ba675SRob Herring nvidia,pins = "kb_col0_pq0"; 631*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 632*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 633*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 634*724ba675SRob Herring }; 635*724ba675SRob Herring kb_col1_pq1 { 636*724ba675SRob Herring nvidia,pins = "kb_col1_pq1"; 637*724ba675SRob Herring nvidia,function = "rsvd2"; 638*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 639*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 640*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 641*724ba675SRob Herring }; 642*724ba675SRob Herring kb_col2_pq2 { 643*724ba675SRob Herring nvidia,pins = "kb_col2_pq2"; 644*724ba675SRob Herring nvidia,function = "rsvd2"; 645*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 646*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 647*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 648*724ba675SRob Herring }; 649*724ba675SRob Herring kb_col3_pq3 { 650*724ba675SRob Herring nvidia,pins = "kb_col3_pq3"; 651*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 652*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 653*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 654*724ba675SRob Herring }; 655*724ba675SRob Herring kb_col4_pq4 { 656*724ba675SRob Herring nvidia,pins = "kb_col4_pq4"; 657*724ba675SRob Herring nvidia,function = "sdmmc3"; 658*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 659*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 660*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 661*724ba675SRob Herring }; 662*724ba675SRob Herring kb_col5_pq5 { 663*724ba675SRob Herring nvidia,pins = "kb_col5_pq5"; 664*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 665*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 666*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 667*724ba675SRob Herring }; 668*724ba675SRob Herring kb_col6_pq6 { 669*724ba675SRob Herring nvidia,pins = "kb_col6_pq6"; 670*724ba675SRob Herring nvidia,function = "rsvd2"; 671*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 672*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 673*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 674*724ba675SRob Herring }; 675*724ba675SRob Herring kb_col7_pq7 { 676*724ba675SRob Herring nvidia,pins = "kb_col7_pq7"; 677*724ba675SRob Herring nvidia,function = "rsvd2"; 678*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 679*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 680*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 681*724ba675SRob Herring }; 682*724ba675SRob Herring kb_row0_pr0 { 683*724ba675SRob Herring nvidia,pins = "kb_row0_pr0"; 684*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 685*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 686*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 687*724ba675SRob Herring }; 688*724ba675SRob Herring kb_row1_pr1 { 689*724ba675SRob Herring nvidia,pins = "kb_row1_pr1"; 690*724ba675SRob Herring nvidia,function = "rsvd2"; 691*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 692*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 693*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 694*724ba675SRob Herring }; 695*724ba675SRob Herring kb_row2_pr2 { 696*724ba675SRob Herring nvidia,pins = "kb_row2_pr2"; 697*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 698*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 699*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 700*724ba675SRob Herring }; 701*724ba675SRob Herring kb_row3_pr3 { 702*724ba675SRob Herring nvidia,pins = "kb_row3_pr3"; 703*724ba675SRob Herring nvidia,function = "kbc"; 704*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 705*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 706*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 707*724ba675SRob Herring }; 708*724ba675SRob Herring kb_row4_pr4 { 709*724ba675SRob Herring nvidia,pins = "kb_row4_pr4"; 710*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 712*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 713*724ba675SRob Herring }; 714*724ba675SRob Herring kb_row5_pr5 { 715*724ba675SRob Herring nvidia,pins = "kb_row5_pr5"; 716*724ba675SRob Herring nvidia,function = "rsvd3"; 717*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 718*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 719*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 720*724ba675SRob Herring }; 721*724ba675SRob Herring kb_row6_pr6 { 722*724ba675SRob Herring nvidia,pins = "kb_row6_pr6"; 723*724ba675SRob Herring nvidia,function = "displaya_alt"; 724*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 725*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 726*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 727*724ba675SRob Herring }; 728*724ba675SRob Herring kb_row7_pr7 { 729*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 730*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 731*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 732*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring kb_row8_ps0 { 735*724ba675SRob Herring nvidia,pins = "kb_row8_ps0"; 736*724ba675SRob Herring nvidia,function = "rsvd2"; 737*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 738*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 739*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 740*724ba675SRob Herring }; 741*724ba675SRob Herring kb_row9_ps1 { 742*724ba675SRob Herring nvidia,pins = "kb_row9_ps1"; 743*724ba675SRob Herring nvidia,function = "uarta"; 744*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 745*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 746*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 747*724ba675SRob Herring }; 748*724ba675SRob Herring kb_row10_ps2 { 749*724ba675SRob Herring nvidia,pins = "kb_row10_ps2"; 750*724ba675SRob Herring nvidia,function = "uarta"; 751*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 752*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 753*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 754*724ba675SRob Herring }; 755*724ba675SRob Herring kb_row11_ps3 { 756*724ba675SRob Herring nvidia,pins = "kb_row11_ps3"; 757*724ba675SRob Herring nvidia,function = "rsvd2"; 758*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 759*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 760*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 761*724ba675SRob Herring }; 762*724ba675SRob Herring kb_row12_ps4 { 763*724ba675SRob Herring nvidia,pins = "kb_row12_ps4"; 764*724ba675SRob Herring nvidia,function = "rsvd2"; 765*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 766*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 767*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 768*724ba675SRob Herring }; 769*724ba675SRob Herring kb_row13_ps5 { 770*724ba675SRob Herring nvidia,pins = "kb_row13_ps5"; 771*724ba675SRob Herring nvidia,function = "rsvd2"; 772*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 773*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 774*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 775*724ba675SRob Herring }; 776*724ba675SRob Herring kb_row14_ps6 { 777*724ba675SRob Herring nvidia,pins = "kb_row14_ps6"; 778*724ba675SRob Herring nvidia,function = "rsvd2"; 779*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 780*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 781*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 782*724ba675SRob Herring }; 783*724ba675SRob Herring kb_row15_ps7 { 784*724ba675SRob Herring nvidia,pins = "kb_row15_ps7"; 785*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 786*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 787*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 788*724ba675SRob Herring }; 789*724ba675SRob Herring kb_row16_pt0 { 790*724ba675SRob Herring nvidia,pins = "kb_row16_pt0"; 791*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 792*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 793*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 794*724ba675SRob Herring }; 795*724ba675SRob Herring kb_row17_pt1 { 796*724ba675SRob Herring nvidia,pins = "kb_row17_pt1"; 797*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 798*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 799*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 800*724ba675SRob Herring }; 801*724ba675SRob Herring gen2_i2c_scl_pt5 { 802*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5"; 803*724ba675SRob Herring nvidia,function = "i2c2"; 804*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 805*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 806*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 807*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 808*724ba675SRob Herring }; 809*724ba675SRob Herring gen2_i2c_sda_pt6 { 810*724ba675SRob Herring nvidia,pins = "gen2_i2c_sda_pt6"; 811*724ba675SRob Herring nvidia,function = "i2c2"; 812*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 813*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 814*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 815*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 816*724ba675SRob Herring }; 817*724ba675SRob Herring sdmmc4_cmd_pt7 { 818*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7"; 819*724ba675SRob Herring nvidia,function = "sdmmc4"; 820*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 821*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 822*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 823*724ba675SRob Herring }; 824*724ba675SRob Herring pu0 { 825*724ba675SRob Herring nvidia,pins = "pu0"; 826*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 827*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 828*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 829*724ba675SRob Herring }; 830*724ba675SRob Herring pu1 { 831*724ba675SRob Herring nvidia,pins = "pu1"; 832*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 833*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 834*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 835*724ba675SRob Herring }; 836*724ba675SRob Herring pu2 { 837*724ba675SRob Herring nvidia,pins = "pu2"; 838*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 839*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 840*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 841*724ba675SRob Herring }; 842*724ba675SRob Herring pu3 { 843*724ba675SRob Herring nvidia,pins = "pu3"; 844*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 845*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 846*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 847*724ba675SRob Herring }; 848*724ba675SRob Herring pu4 { 849*724ba675SRob Herring nvidia,pins = "pu4"; 850*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 851*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 852*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 853*724ba675SRob Herring }; 854*724ba675SRob Herring pu5 { 855*724ba675SRob Herring nvidia,pins = "pu5"; 856*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 857*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 858*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 859*724ba675SRob Herring }; 860*724ba675SRob Herring pu6 { 861*724ba675SRob Herring nvidia,pins = "pu6"; 862*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 863*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 864*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 865*724ba675SRob Herring }; 866*724ba675SRob Herring pv0 { 867*724ba675SRob Herring nvidia,pins = "pv0"; 868*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 869*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 870*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 871*724ba675SRob Herring }; 872*724ba675SRob Herring pv1 { 873*724ba675SRob Herring nvidia,pins = "pv1"; 874*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 875*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 876*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 877*724ba675SRob Herring }; 878*724ba675SRob Herring sdmmc3_cd_n_pv2 { 879*724ba675SRob Herring nvidia,pins = "sdmmc3_cd_n_pv2"; 880*724ba675SRob Herring nvidia,function = "sdmmc3"; 881*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 882*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 883*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 884*724ba675SRob Herring }; 885*724ba675SRob Herring sdmmc1_wp_n_pv3 { 886*724ba675SRob Herring nvidia,pins = "sdmmc1_wp_n_pv3"; 887*724ba675SRob Herring nvidia,function = "sdmmc1"; 888*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 889*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 890*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 891*724ba675SRob Herring }; 892*724ba675SRob Herring ddc_scl_pv4 { 893*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4"; 894*724ba675SRob Herring nvidia,function = "i2c4"; 895*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 896*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 897*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 898*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 899*724ba675SRob Herring }; 900*724ba675SRob Herring ddc_sda_pv5 { 901*724ba675SRob Herring nvidia,pins = "ddc_sda_pv5"; 902*724ba675SRob Herring nvidia,function = "i2c4"; 903*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 904*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 905*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 906*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 907*724ba675SRob Herring }; 908*724ba675SRob Herring gpio_w2_aud_pw2 { 909*724ba675SRob Herring nvidia,pins = "gpio_w2_aud_pw2"; 910*724ba675SRob Herring nvidia,function = "rsvd2"; 911*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 912*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 913*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 914*724ba675SRob Herring }; 915*724ba675SRob Herring gpio_w3_aud_pw3 { 916*724ba675SRob Herring nvidia,pins = "gpio_w3_aud_pw3"; 917*724ba675SRob Herring nvidia,function = "spi6"; 918*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 919*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 920*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 921*724ba675SRob Herring }; 922*724ba675SRob Herring dap_mclk1_pw4 { 923*724ba675SRob Herring nvidia,pins = "dap_mclk1_pw4"; 924*724ba675SRob Herring nvidia,function = "extperiph1"; 925*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 926*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 927*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 928*724ba675SRob Herring }; 929*724ba675SRob Herring clk2_out_pw5 { 930*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 931*724ba675SRob Herring nvidia,function = "extperiph2"; 932*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 933*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 934*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 935*724ba675SRob Herring }; 936*724ba675SRob Herring uart3_txd_pw6 { 937*724ba675SRob Herring nvidia,pins = "uart3_txd_pw6"; 938*724ba675SRob Herring nvidia,function = "rsvd2"; 939*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 940*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 941*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 942*724ba675SRob Herring }; 943*724ba675SRob Herring uart3_rxd_pw7 { 944*724ba675SRob Herring nvidia,pins = "uart3_rxd_pw7"; 945*724ba675SRob Herring nvidia,function = "rsvd2"; 946*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 947*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 948*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 949*724ba675SRob Herring }; 950*724ba675SRob Herring dvfs_pwm_px0 { 951*724ba675SRob Herring nvidia,pins = "dvfs_pwm_px0"; 952*724ba675SRob Herring nvidia,function = "cldvfs"; 953*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 954*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 955*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 956*724ba675SRob Herring }; 957*724ba675SRob Herring gpio_x1_aud_px1 { 958*724ba675SRob Herring nvidia,pins = "gpio_x1_aud_px1"; 959*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 960*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 961*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 962*724ba675SRob Herring }; 963*724ba675SRob Herring dvfs_clk_px2 { 964*724ba675SRob Herring nvidia,pins = "dvfs_clk_px2"; 965*724ba675SRob Herring nvidia,function = "cldvfs"; 966*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 967*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 968*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 969*724ba675SRob Herring }; 970*724ba675SRob Herring gpio_x3_aud_px3 { 971*724ba675SRob Herring nvidia,pins = "gpio_x3_aud_px3"; 972*724ba675SRob Herring nvidia,function = "rsvd4"; 973*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 974*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 975*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 976*724ba675SRob Herring }; 977*724ba675SRob Herring gpio_x4_aud_px4 { 978*724ba675SRob Herring nvidia,pins = "gpio_x4_aud_px4"; 979*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 980*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 981*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 982*724ba675SRob Herring }; 983*724ba675SRob Herring gpio_x5_aud_px5 { 984*724ba675SRob Herring nvidia,pins = "gpio_x5_aud_px5"; 985*724ba675SRob Herring nvidia,function = "rsvd4"; 986*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 987*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 988*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 989*724ba675SRob Herring }; 990*724ba675SRob Herring gpio_x6_aud_px6 { 991*724ba675SRob Herring nvidia,pins = "gpio_x6_aud_px6"; 992*724ba675SRob Herring nvidia,function = "gmi"; 993*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 994*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 995*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 996*724ba675SRob Herring }; 997*724ba675SRob Herring gpio_x7_aud_px7 { 998*724ba675SRob Herring nvidia,pins = "gpio_x7_aud_px7"; 999*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1000*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1001*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1002*724ba675SRob Herring }; 1003*724ba675SRob Herring ulpi_clk_py0 { 1004*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0"; 1005*724ba675SRob Herring nvidia,function = "spi1"; 1006*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1007*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1008*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1009*724ba675SRob Herring }; 1010*724ba675SRob Herring ulpi_dir_py1 { 1011*724ba675SRob Herring nvidia,pins = "ulpi_dir_py1"; 1012*724ba675SRob Herring nvidia,function = "spi1"; 1013*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1014*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1015*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1016*724ba675SRob Herring }; 1017*724ba675SRob Herring ulpi_nxt_py2 { 1018*724ba675SRob Herring nvidia,pins = "ulpi_nxt_py2"; 1019*724ba675SRob Herring nvidia,function = "spi1"; 1020*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1021*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1022*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1023*724ba675SRob Herring }; 1024*724ba675SRob Herring ulpi_stp_py3 { 1025*724ba675SRob Herring nvidia,pins = "ulpi_stp_py3"; 1026*724ba675SRob Herring nvidia,function = "spi1"; 1027*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1028*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1029*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1030*724ba675SRob Herring }; 1031*724ba675SRob Herring sdmmc1_dat3_py4 { 1032*724ba675SRob Herring nvidia,pins = "sdmmc1_dat3_py4"; 1033*724ba675SRob Herring nvidia,function = "sdmmc1"; 1034*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1035*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1036*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1037*724ba675SRob Herring }; 1038*724ba675SRob Herring sdmmc1_dat2_py5 { 1039*724ba675SRob Herring nvidia,pins = "sdmmc1_dat2_py5"; 1040*724ba675SRob Herring nvidia,function = "sdmmc1"; 1041*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1042*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1043*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1044*724ba675SRob Herring }; 1045*724ba675SRob Herring sdmmc1_dat1_py6 { 1046*724ba675SRob Herring nvidia,pins = "sdmmc1_dat1_py6"; 1047*724ba675SRob Herring nvidia,function = "sdmmc1"; 1048*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1049*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1050*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1051*724ba675SRob Herring }; 1052*724ba675SRob Herring sdmmc1_dat0_py7 { 1053*724ba675SRob Herring nvidia,pins = "sdmmc1_dat0_py7"; 1054*724ba675SRob Herring nvidia,function = "rsvd2"; 1055*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1056*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1057*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring sdmmc1_clk_pz0 { 1060*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 1061*724ba675SRob Herring nvidia,function = "rsvd3"; 1062*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1063*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1064*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring sdmmc1_cmd_pz1 { 1067*724ba675SRob Herring nvidia,pins = "sdmmc1_cmd_pz1"; 1068*724ba675SRob Herring nvidia,function = "sdmmc1"; 1069*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1070*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1071*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1072*724ba675SRob Herring }; 1073*724ba675SRob Herring pwr_i2c_scl_pz6 { 1074*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6"; 1075*724ba675SRob Herring nvidia,function = "i2cpwr"; 1076*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1077*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1078*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1079*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1080*724ba675SRob Herring }; 1081*724ba675SRob Herring pwr_i2c_sda_pz7 { 1082*724ba675SRob Herring nvidia,pins = "pwr_i2c_sda_pz7"; 1083*724ba675SRob Herring nvidia,function = "i2cpwr"; 1084*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1085*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1086*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1087*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1088*724ba675SRob Herring }; 1089*724ba675SRob Herring sdmmc4_dat0_paa0 { 1090*724ba675SRob Herring nvidia,pins = "sdmmc4_dat0_paa0"; 1091*724ba675SRob Herring nvidia,function = "sdmmc4"; 1092*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1093*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1094*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1095*724ba675SRob Herring }; 1096*724ba675SRob Herring sdmmc4_dat1_paa1 { 1097*724ba675SRob Herring nvidia,pins = "sdmmc4_dat1_paa1"; 1098*724ba675SRob Herring nvidia,function = "sdmmc4"; 1099*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1100*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1101*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1102*724ba675SRob Herring }; 1103*724ba675SRob Herring sdmmc4_dat2_paa2 { 1104*724ba675SRob Herring nvidia,pins = "sdmmc4_dat2_paa2"; 1105*724ba675SRob Herring nvidia,function = "sdmmc4"; 1106*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1107*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1108*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1109*724ba675SRob Herring }; 1110*724ba675SRob Herring sdmmc4_dat3_paa3 { 1111*724ba675SRob Herring nvidia,pins = "sdmmc4_dat3_paa3"; 1112*724ba675SRob Herring nvidia,function = "sdmmc4"; 1113*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1114*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1115*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1116*724ba675SRob Herring }; 1117*724ba675SRob Herring sdmmc4_dat4_paa4 { 1118*724ba675SRob Herring nvidia,pins = "sdmmc4_dat4_paa4"; 1119*724ba675SRob Herring nvidia,function = "sdmmc4"; 1120*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1121*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1122*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring sdmmc4_dat5_paa5 { 1125*724ba675SRob Herring nvidia,pins = "sdmmc4_dat5_paa5"; 1126*724ba675SRob Herring nvidia,function = "sdmmc4"; 1127*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1128*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1129*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1130*724ba675SRob Herring }; 1131*724ba675SRob Herring sdmmc4_dat6_paa6 { 1132*724ba675SRob Herring nvidia,pins = "sdmmc4_dat6_paa6"; 1133*724ba675SRob Herring nvidia,function = "sdmmc4"; 1134*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1135*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1136*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1137*724ba675SRob Herring }; 1138*724ba675SRob Herring sdmmc4_dat7_paa7 { 1139*724ba675SRob Herring nvidia,pins = "sdmmc4_dat7_paa7"; 1140*724ba675SRob Herring nvidia,function = "sdmmc4"; 1141*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1142*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1143*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1144*724ba675SRob Herring }; 1145*724ba675SRob Herring pbb0 { 1146*724ba675SRob Herring nvidia,pins = "pbb0"; 1147*724ba675SRob Herring nvidia,function = "vimclk2_alt"; 1148*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1149*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1150*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1151*724ba675SRob Herring }; 1152*724ba675SRob Herring cam_i2c_scl_pbb1 { 1153*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1"; 1154*724ba675SRob Herring nvidia,function = "i2c3"; 1155*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1156*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1157*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1158*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1159*724ba675SRob Herring }; 1160*724ba675SRob Herring cam_i2c_sda_pbb2 { 1161*724ba675SRob Herring nvidia,pins = "cam_i2c_sda_pbb2"; 1162*724ba675SRob Herring nvidia,function = "i2c3"; 1163*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1164*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1165*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1166*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1167*724ba675SRob Herring }; 1168*724ba675SRob Herring pbb3 { 1169*724ba675SRob Herring nvidia,pins = "pbb3"; 1170*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1171*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1172*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1173*724ba675SRob Herring }; 1174*724ba675SRob Herring pbb4 { 1175*724ba675SRob Herring nvidia,pins = "pbb4"; 1176*724ba675SRob Herring nvidia,function = "vgp4"; 1177*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1178*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1179*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1180*724ba675SRob Herring }; 1181*724ba675SRob Herring pbb5 { 1182*724ba675SRob Herring nvidia,pins = "pbb5"; 1183*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1184*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1185*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1186*724ba675SRob Herring }; 1187*724ba675SRob Herring pbb6 { 1188*724ba675SRob Herring nvidia,pins = "pbb6"; 1189*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1190*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1191*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1192*724ba675SRob Herring }; 1193*724ba675SRob Herring pbb7 { 1194*724ba675SRob Herring nvidia,pins = "pbb7"; 1195*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1196*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1197*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1198*724ba675SRob Herring }; 1199*724ba675SRob Herring cam_mclk_pcc0 { 1200*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0"; 1201*724ba675SRob Herring nvidia,function = "vi_alt3"; 1202*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1203*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1204*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1205*724ba675SRob Herring }; 1206*724ba675SRob Herring pcc1 { 1207*724ba675SRob Herring nvidia,pins = "pcc1"; 1208*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1209*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1210*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1211*724ba675SRob Herring }; 1212*724ba675SRob Herring pcc2 { 1213*724ba675SRob Herring nvidia,pins = "pcc2"; 1214*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1215*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1216*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1217*724ba675SRob Herring }; 1218*724ba675SRob Herring sdmmc4_clk_pcc4 { 1219*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 1220*724ba675SRob Herring nvidia,function = "sdmmc4"; 1221*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1222*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1223*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1224*724ba675SRob Herring }; 1225*724ba675SRob Herring clk2_req_pcc5 { 1226*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 1227*724ba675SRob Herring nvidia,function = "rsvd2"; 1228*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1229*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1230*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1231*724ba675SRob Herring }; 1232*724ba675SRob Herring pex_l0_rst_n_pdd1 { 1233*724ba675SRob Herring nvidia,pins = "pex_l0_rst_n_pdd1"; 1234*724ba675SRob Herring nvidia,function = "pe0"; 1235*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1236*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1237*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring pex_l0_clkreq_n_pdd2 { 1240*724ba675SRob Herring nvidia,pins = "pex_l0_clkreq_n_pdd2"; 1241*724ba675SRob Herring nvidia,function = "pe0"; 1242*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1243*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1244*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1245*724ba675SRob Herring }; 1246*724ba675SRob Herring pex_wake_n_pdd3 { 1247*724ba675SRob Herring nvidia,pins = "pex_wake_n_pdd3"; 1248*724ba675SRob Herring nvidia,function = "pe"; 1249*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1250*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1251*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1252*724ba675SRob Herring }; 1253*724ba675SRob Herring pex_l1_rst_n_pdd5 { 1254*724ba675SRob Herring nvidia,pins = "pex_l1_rst_n_pdd5"; 1255*724ba675SRob Herring nvidia,function = "pe1"; 1256*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1257*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1258*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1259*724ba675SRob Herring }; 1260*724ba675SRob Herring pex_l1_clkreq_n_pdd6 { 1261*724ba675SRob Herring nvidia,pins = "pex_l1_clkreq_n_pdd6"; 1262*724ba675SRob Herring nvidia,function = "pe1"; 1263*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1264*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1265*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1266*724ba675SRob Herring }; 1267*724ba675SRob Herring clk3_out_pee0 { 1268*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 1269*724ba675SRob Herring nvidia,function = "extperiph3"; 1270*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1271*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1272*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1273*724ba675SRob Herring }; 1274*724ba675SRob Herring clk3_req_pee1 { 1275*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 1276*724ba675SRob Herring nvidia,function = "rsvd2"; 1277*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1278*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1279*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1280*724ba675SRob Herring }; 1281*724ba675SRob Herring dap_mclk1_req_pee2 { 1282*724ba675SRob Herring nvidia,pins = "dap_mclk1_req_pee2"; 1283*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1284*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1285*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1286*724ba675SRob Herring }; 1287*724ba675SRob Herring hdmi_cec_pee3 { 1288*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 1289*724ba675SRob Herring nvidia,function = "cec"; 1290*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1291*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1292*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1293*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1294*724ba675SRob Herring }; 1295*724ba675SRob Herring sdmmc3_clk_lb_out_pee4 { 1296*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1297*724ba675SRob Herring nvidia,function = "sdmmc3"; 1298*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1299*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1300*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1301*724ba675SRob Herring }; 1302*724ba675SRob Herring sdmmc3_clk_lb_in_pee5 { 1303*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 1304*724ba675SRob Herring nvidia,function = "sdmmc3"; 1305*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1306*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1307*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1308*724ba675SRob Herring }; 1309*724ba675SRob Herring dp_hpd_pff0 { 1310*724ba675SRob Herring nvidia,pins = "dp_hpd_pff0"; 1311*724ba675SRob Herring nvidia,function = "dp"; 1312*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1313*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1314*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1315*724ba675SRob Herring }; 1316*724ba675SRob Herring usb_vbus_en2_pff1 { 1317*724ba675SRob Herring nvidia,pins = "usb_vbus_en2_pff1"; 1318*724ba675SRob Herring nvidia,function = "rsvd2"; 1319*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1320*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1321*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1322*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1323*724ba675SRob Herring }; 1324*724ba675SRob Herring pff2 { 1325*724ba675SRob Herring nvidia,pins = "pff2"; 1326*724ba675SRob Herring nvidia,function = "rsvd2"; 1327*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1328*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1329*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1330*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1331*724ba675SRob Herring }; 1332*724ba675SRob Herring core_pwr_req { 1333*724ba675SRob Herring nvidia,pins = "core_pwr_req"; 1334*724ba675SRob Herring nvidia,function = "pwron"; 1335*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1336*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1337*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1338*724ba675SRob Herring }; 1339*724ba675SRob Herring cpu_pwr_req { 1340*724ba675SRob Herring nvidia,pins = "cpu_pwr_req"; 1341*724ba675SRob Herring nvidia,function = "cpu"; 1342*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1343*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1344*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1345*724ba675SRob Herring }; 1346*724ba675SRob Herring pwr_int_n { 1347*724ba675SRob Herring nvidia,pins = "pwr_int_n"; 1348*724ba675SRob Herring nvidia,function = "pmi"; 1349*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1350*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1351*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1352*724ba675SRob Herring }; 1353*724ba675SRob Herring reset_out_n { 1354*724ba675SRob Herring nvidia,pins = "reset_out_n"; 1355*724ba675SRob Herring nvidia,function = "reset_out_n"; 1356*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1357*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1358*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1359*724ba675SRob Herring }; 1360*724ba675SRob Herring clk_32k_in { 1361*724ba675SRob Herring nvidia,pins = "clk_32k_in"; 1362*724ba675SRob Herring nvidia,function = "clk"; 1363*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1364*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 1365*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1366*724ba675SRob Herring }; 1367*724ba675SRob Herring jtag_rtck { 1368*724ba675SRob Herring nvidia,pins = "jtag_rtck"; 1369*724ba675SRob Herring nvidia,function = "rtck"; 1370*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1371*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1372*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1373*724ba675SRob Herring }; 1374*724ba675SRob Herring dsi_b { 1375*724ba675SRob Herring nvidia,pins = "mipi_pad_ctrl_dsi_b"; 1376*724ba675SRob Herring nvidia,function = "dsi_b"; 1377*724ba675SRob Herring }; 1378*724ba675SRob Herring }; 1379*724ba675SRob Herring }; 1380*724ba675SRob Herring 1381*724ba675SRob Herring /* 1382*724ba675SRob Herring * First high speed UART, exposed on the expansion connector J3A2 1383*724ba675SRob Herring * Pin 41: BR_UART1_TXD 1384*724ba675SRob Herring * Pin 44: BR_UART1_RXD 1385*724ba675SRob Herring */ 1386*724ba675SRob Herring serial@70006000 { 1387*724ba675SRob Herring compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1388*724ba675SRob Herring /delete-property/ reg-shift; 1389*724ba675SRob Herring status = "okay"; 1390*724ba675SRob Herring }; 1391*724ba675SRob Herring 1392*724ba675SRob Herring /* 1393*724ba675SRob Herring * Second high speed UART, exposed on the expansion connector J3A2 1394*724ba675SRob Herring * Pin 65: UART2_RXD 1395*724ba675SRob Herring * Pin 68: UART2_TXD 1396*724ba675SRob Herring * Pin 71: UART2_CTS_L 1397*724ba675SRob Herring * Pin 74: UART2_RTS_L 1398*724ba675SRob Herring */ 1399*724ba675SRob Herring serial@70006040 { 1400*724ba675SRob Herring compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1401*724ba675SRob Herring /delete-property/ reg-shift; 1402*724ba675SRob Herring status = "okay"; 1403*724ba675SRob Herring }; 1404*724ba675SRob Herring 1405*724ba675SRob Herring /* DB9 serial port */ 1406*724ba675SRob Herring serial@70006300 { 1407*724ba675SRob Herring status = "okay"; 1408*724ba675SRob Herring }; 1409*724ba675SRob Herring 1410*724ba675SRob Herring /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ 1411*724ba675SRob Herring i2c@7000c000 { 1412*724ba675SRob Herring status = "okay"; 1413*724ba675SRob Herring clock-frequency = <100000>; 1414*724ba675SRob Herring 1415*724ba675SRob Herring rt5639: audio-codec@1c { 1416*724ba675SRob Herring compatible = "realtek,rt5639"; 1417*724ba675SRob Herring reg = <0x1c>; 1418*724ba675SRob Herring interrupt-parent = <&gpio>; 1419*724ba675SRob Herring interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; 1420*724ba675SRob Herring realtek,ldo1-en-gpios = 1421*724ba675SRob Herring <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; 1422*724ba675SRob Herring }; 1423*724ba675SRob Herring 1424*724ba675SRob Herring temperature-sensor@4c { 1425*724ba675SRob Herring compatible = "ti,tmp451"; 1426*724ba675SRob Herring reg = <0x4c>; 1427*724ba675SRob Herring interrupt-parent = <&gpio>; 1428*724ba675SRob Herring interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>; 1429*724ba675SRob Herring }; 1430*724ba675SRob Herring 1431*724ba675SRob Herring eeprom@56 { 1432*724ba675SRob Herring compatible = "atmel,24c02"; 1433*724ba675SRob Herring reg = <0x56>; 1434*724ba675SRob Herring pagesize = <8>; 1435*724ba675SRob Herring }; 1436*724ba675SRob Herring }; 1437*724ba675SRob Herring 1438*724ba675SRob Herring /* Expansion GEN2_I2C_* */ 1439*724ba675SRob Herring i2c@7000c400 { 1440*724ba675SRob Herring status = "okay"; 1441*724ba675SRob Herring clock-frequency = <100000>; 1442*724ba675SRob Herring }; 1443*724ba675SRob Herring 1444*724ba675SRob Herring /* Expansion CAM_I2C_* */ 1445*724ba675SRob Herring i2c@7000c500 { 1446*724ba675SRob Herring status = "okay"; 1447*724ba675SRob Herring clock-frequency = <100000>; 1448*724ba675SRob Herring }; 1449*724ba675SRob Herring 1450*724ba675SRob Herring /* HDMI DDC */ 1451*724ba675SRob Herring hdmi_ddc: i2c@7000c700 { 1452*724ba675SRob Herring status = "okay"; 1453*724ba675SRob Herring clock-frequency = <100000>; 1454*724ba675SRob Herring }; 1455*724ba675SRob Herring 1456*724ba675SRob Herring /* Expansion PWR_I2C_*, on-board components */ 1457*724ba675SRob Herring i2c@7000d000 { 1458*724ba675SRob Herring status = "okay"; 1459*724ba675SRob Herring clock-frequency = <400000>; 1460*724ba675SRob Herring 1461*724ba675SRob Herring pmic: pmic@40 { 1462*724ba675SRob Herring compatible = "ams,as3722"; 1463*724ba675SRob Herring reg = <0x40>; 1464*724ba675SRob Herring interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1465*724ba675SRob Herring 1466*724ba675SRob Herring ams,system-power-controller; 1467*724ba675SRob Herring 1468*724ba675SRob Herring #interrupt-cells = <2>; 1469*724ba675SRob Herring interrupt-controller; 1470*724ba675SRob Herring 1471*724ba675SRob Herring gpio-controller; 1472*724ba675SRob Herring #gpio-cells = <2>; 1473*724ba675SRob Herring 1474*724ba675SRob Herring pinctrl-names = "default"; 1475*724ba675SRob Herring pinctrl-0 = <&as3722_default>; 1476*724ba675SRob Herring 1477*724ba675SRob Herring as3722_default: pinmux { 1478*724ba675SRob Herring gpio0 { 1479*724ba675SRob Herring pins = "gpio0"; 1480*724ba675SRob Herring function = "gpio"; 1481*724ba675SRob Herring bias-pull-down; 1482*724ba675SRob Herring }; 1483*724ba675SRob Herring 1484*724ba675SRob Herring gpio1_2_4_7 { 1485*724ba675SRob Herring pins = "gpio1", "gpio2", "gpio4", "gpio7"; 1486*724ba675SRob Herring function = "gpio"; 1487*724ba675SRob Herring bias-pull-up; 1488*724ba675SRob Herring }; 1489*724ba675SRob Herring 1490*724ba675SRob Herring gpio3_5_6 { 1491*724ba675SRob Herring pins = "gpio3", "gpio5", "gpio6"; 1492*724ba675SRob Herring bias-high-impedance; 1493*724ba675SRob Herring }; 1494*724ba675SRob Herring }; 1495*724ba675SRob Herring 1496*724ba675SRob Herring regulators { 1497*724ba675SRob Herring vsup-sd2-supply = <&vdd_5v0_sys>; 1498*724ba675SRob Herring vsup-sd3-supply = <&vdd_5v0_sys>; 1499*724ba675SRob Herring vsup-sd4-supply = <&vdd_5v0_sys>; 1500*724ba675SRob Herring vsup-sd5-supply = <&vdd_5v0_sys>; 1501*724ba675SRob Herring vin-ldo0-supply = <&vdd_1v35_lp0>; 1502*724ba675SRob Herring vin-ldo1-6-supply = <&vdd_3v3_run>; 1503*724ba675SRob Herring vin-ldo2-5-7-supply = <&vddio_1v8>; 1504*724ba675SRob Herring vin-ldo3-4-supply = <&vdd_3v3_sys>; 1505*724ba675SRob Herring vin-ldo9-10-supply = <&vdd_5v0_sys>; 1506*724ba675SRob Herring vin-ldo11-supply = <&vdd_3v3_run>; 1507*724ba675SRob Herring 1508*724ba675SRob Herring vdd_cpu: sd0 { 1509*724ba675SRob Herring regulator-name = "+VDD_CPU_AP"; 1510*724ba675SRob Herring regulator-min-microvolt = <700000>; 1511*724ba675SRob Herring regulator-max-microvolt = <1400000>; 1512*724ba675SRob Herring regulator-min-microamp = <3500000>; 1513*724ba675SRob Herring regulator-max-microamp = <3500000>; 1514*724ba675SRob Herring regulator-always-on; 1515*724ba675SRob Herring regulator-boot-on; 1516*724ba675SRob Herring ams,ext-control = <2>; 1517*724ba675SRob Herring }; 1518*724ba675SRob Herring 1519*724ba675SRob Herring sd1 { 1520*724ba675SRob Herring regulator-name = "+VDD_CORE"; 1521*724ba675SRob Herring regulator-min-microvolt = <700000>; 1522*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1523*724ba675SRob Herring regulator-min-microamp = <2500000>; 1524*724ba675SRob Herring regulator-max-microamp = <2500000>; 1525*724ba675SRob Herring regulator-always-on; 1526*724ba675SRob Herring regulator-boot-on; 1527*724ba675SRob Herring ams,ext-control = <1>; 1528*724ba675SRob Herring }; 1529*724ba675SRob Herring 1530*724ba675SRob Herring vdd_1v35_lp0: sd2 { 1531*724ba675SRob Herring regulator-name = "+1.35V_LP0(sd2)"; 1532*724ba675SRob Herring regulator-min-microvolt = <1350000>; 1533*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1534*724ba675SRob Herring regulator-always-on; 1535*724ba675SRob Herring regulator-boot-on; 1536*724ba675SRob Herring }; 1537*724ba675SRob Herring 1538*724ba675SRob Herring sd3 { 1539*724ba675SRob Herring regulator-name = "+1.35V_LP0(sd3)"; 1540*724ba675SRob Herring regulator-min-microvolt = <1350000>; 1541*724ba675SRob Herring regulator-max-microvolt = <1350000>; 1542*724ba675SRob Herring regulator-always-on; 1543*724ba675SRob Herring regulator-boot-on; 1544*724ba675SRob Herring }; 1545*724ba675SRob Herring 1546*724ba675SRob Herring vdd_1v05_run: sd4 { 1547*724ba675SRob Herring regulator-name = "+1.05V_RUN"; 1548*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1549*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1550*724ba675SRob Herring }; 1551*724ba675SRob Herring 1552*724ba675SRob Herring vddio_1v8: sd5 { 1553*724ba675SRob Herring regulator-name = "+1.8V_VDDIO"; 1554*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1555*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1556*724ba675SRob Herring regulator-boot-on; 1557*724ba675SRob Herring regulator-always-on; 1558*724ba675SRob Herring }; 1559*724ba675SRob Herring 1560*724ba675SRob Herring vdd_gpu: sd6 { 1561*724ba675SRob Herring regulator-name = "+VDD_GPU_AP"; 1562*724ba675SRob Herring regulator-min-microvolt = <650000>; 1563*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1564*724ba675SRob Herring regulator-min-microamp = <3500000>; 1565*724ba675SRob Herring regulator-max-microamp = <3500000>; 1566*724ba675SRob Herring regulator-boot-on; 1567*724ba675SRob Herring regulator-always-on; 1568*724ba675SRob Herring }; 1569*724ba675SRob Herring 1570*724ba675SRob Herring avdd_1v05_run: ldo0 { 1571*724ba675SRob Herring regulator-name = "+1.05V_RUN_AVDD"; 1572*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1573*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1574*724ba675SRob Herring regulator-boot-on; 1575*724ba675SRob Herring regulator-always-on; 1576*724ba675SRob Herring ams,ext-control = <1>; 1577*724ba675SRob Herring }; 1578*724ba675SRob Herring 1579*724ba675SRob Herring ldo1 { 1580*724ba675SRob Herring regulator-name = "+1.8V_RUN_CAM"; 1581*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1582*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1583*724ba675SRob Herring }; 1584*724ba675SRob Herring 1585*724ba675SRob Herring ldo2 { 1586*724ba675SRob Herring regulator-name = "+1.2V_GEN_AVDD"; 1587*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1588*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1589*724ba675SRob Herring regulator-boot-on; 1590*724ba675SRob Herring regulator-always-on; 1591*724ba675SRob Herring }; 1592*724ba675SRob Herring 1593*724ba675SRob Herring ldo3 { 1594*724ba675SRob Herring regulator-name = "+1.05V_LP0_VDD_RTC"; 1595*724ba675SRob Herring regulator-min-microvolt = <1000000>; 1596*724ba675SRob Herring regulator-max-microvolt = <1000000>; 1597*724ba675SRob Herring regulator-boot-on; 1598*724ba675SRob Herring regulator-always-on; 1599*724ba675SRob Herring ams,enable-tracking; 1600*724ba675SRob Herring }; 1601*724ba675SRob Herring 1602*724ba675SRob Herring ldo4 { 1603*724ba675SRob Herring regulator-name = "+2.8V_RUN_CAM"; 1604*724ba675SRob Herring regulator-min-microvolt = <2800000>; 1605*724ba675SRob Herring regulator-max-microvolt = <2800000>; 1606*724ba675SRob Herring }; 1607*724ba675SRob Herring 1608*724ba675SRob Herring ldo5 { 1609*724ba675SRob Herring regulator-name = "+1.2V_RUN_CAM_FRONT"; 1610*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1611*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1612*724ba675SRob Herring }; 1613*724ba675SRob Herring 1614*724ba675SRob Herring vddio_sdmmc3: ldo6 { 1615*724ba675SRob Herring regulator-name = "+VDDIO_SDMMC3"; 1616*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1617*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1618*724ba675SRob Herring }; 1619*724ba675SRob Herring 1620*724ba675SRob Herring ldo7 { 1621*724ba675SRob Herring regulator-name = "+1.05V_RUN_CAM_REAR"; 1622*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1623*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1624*724ba675SRob Herring }; 1625*724ba675SRob Herring 1626*724ba675SRob Herring ldo9 { 1627*724ba675SRob Herring regulator-name = "+3.3V_RUN_TOUCH"; 1628*724ba675SRob Herring regulator-min-microvolt = <2800000>; 1629*724ba675SRob Herring regulator-max-microvolt = <2800000>; 1630*724ba675SRob Herring }; 1631*724ba675SRob Herring 1632*724ba675SRob Herring ldo10 { 1633*724ba675SRob Herring regulator-name = "+2.8V_RUN_CAM_AF"; 1634*724ba675SRob Herring regulator-min-microvolt = <2800000>; 1635*724ba675SRob Herring regulator-max-microvolt = <2800000>; 1636*724ba675SRob Herring }; 1637*724ba675SRob Herring 1638*724ba675SRob Herring ldo11 { 1639*724ba675SRob Herring regulator-name = "+1.8V_RUN_VPP_FUSE"; 1640*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1641*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1642*724ba675SRob Herring }; 1643*724ba675SRob Herring }; 1644*724ba675SRob Herring }; 1645*724ba675SRob Herring }; 1646*724ba675SRob Herring 1647*724ba675SRob Herring /* Expansion TS_SPI_* */ 1648*724ba675SRob Herring spi@7000d400 { 1649*724ba675SRob Herring status = "okay"; 1650*724ba675SRob Herring }; 1651*724ba675SRob Herring 1652*724ba675SRob Herring /* Internal SPI */ 1653*724ba675SRob Herring spi@7000da00 { 1654*724ba675SRob Herring status = "okay"; 1655*724ba675SRob Herring spi-max-frequency = <25000000>; 1656*724ba675SRob Herring 1657*724ba675SRob Herring flash@0 { 1658*724ba675SRob Herring compatible = "winbond,w25q32dw", "jedec,spi-nor"; 1659*724ba675SRob Herring reg = <0>; 1660*724ba675SRob Herring spi-max-frequency = <20000000>; 1661*724ba675SRob Herring }; 1662*724ba675SRob Herring }; 1663*724ba675SRob Herring 1664*724ba675SRob Herring pmc@7000e400 { 1665*724ba675SRob Herring nvidia,invert-interrupt; 1666*724ba675SRob Herring nvidia,suspend-mode = <1>; 1667*724ba675SRob Herring nvidia,cpu-pwr-good-time = <500>; 1668*724ba675SRob Herring nvidia,cpu-pwr-off-time = <300>; 1669*724ba675SRob Herring nvidia,core-pwr-good-time = <641 3845>; 1670*724ba675SRob Herring nvidia,core-pwr-off-time = <61036>; 1671*724ba675SRob Herring nvidia,core-power-req-active-high; 1672*724ba675SRob Herring nvidia,sys-clock-req-active-high; 1673*724ba675SRob Herring 1674*724ba675SRob Herring i2c-thermtrip { 1675*724ba675SRob Herring nvidia,i2c-controller-id = <4>; 1676*724ba675SRob Herring nvidia,bus-addr = <0x40>; 1677*724ba675SRob Herring nvidia,reg-addr = <0x36>; 1678*724ba675SRob Herring nvidia,reg-data = <0x2>; 1679*724ba675SRob Herring }; 1680*724ba675SRob Herring }; 1681*724ba675SRob Herring 1682*724ba675SRob Herring cec@70015000 { 1683*724ba675SRob Herring status = "okay"; 1684*724ba675SRob Herring }; 1685*724ba675SRob Herring 1686*724ba675SRob Herring /* Serial ATA */ 1687*724ba675SRob Herring sata@70020000 { 1688*724ba675SRob Herring status = "okay"; 1689*724ba675SRob Herring 1690*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1691*724ba675SRob Herring phy-names = "sata-0"; 1692*724ba675SRob Herring 1693*724ba675SRob Herring hvdd-supply = <&vdd_3v3_lp0>; 1694*724ba675SRob Herring vddio-supply = <&vdd_1v05_run>; 1695*724ba675SRob Herring avdd-supply = <&vdd_1v05_run>; 1696*724ba675SRob Herring 1697*724ba675SRob Herring target-5v-supply = <&vdd_5v0_sata>; 1698*724ba675SRob Herring target-12v-supply = <&vdd_12v0_sata>; 1699*724ba675SRob Herring }; 1700*724ba675SRob Herring 1701*724ba675SRob Herring hda@70030000 { 1702*724ba675SRob Herring status = "okay"; 1703*724ba675SRob Herring }; 1704*724ba675SRob Herring 1705*724ba675SRob Herring usb@70090000 { 1706*724ba675SRob Herring phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ 1707*724ba675SRob Herring <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ 1708*724ba675SRob Herring <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ 1709*724ba675SRob Herring <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ 1710*724ba675SRob Herring phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 1711*724ba675SRob Herring 1712*724ba675SRob Herring avddio-pex-supply = <&vdd_1v05_run>; 1713*724ba675SRob Herring dvddio-pex-supply = <&vdd_1v05_run>; 1714*724ba675SRob Herring avdd-usb-supply = <&vdd_3v3_lp0>; 1715*724ba675SRob Herring avdd-pll-utmip-supply = <&vddio_1v8>; 1716*724ba675SRob Herring avdd-pll-erefe-supply = <&avdd_1v05_run>; 1717*724ba675SRob Herring avdd-usb-ss-pll-supply = <&vdd_1v05_run>; 1718*724ba675SRob Herring hvdd-usb-ss-supply = <&vdd_3v3_lp0>; 1719*724ba675SRob Herring hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; 1720*724ba675SRob Herring 1721*724ba675SRob Herring status = "okay"; 1722*724ba675SRob Herring }; 1723*724ba675SRob Herring 1724*724ba675SRob Herring padctl@7009f000 { 1725*724ba675SRob Herring status = "okay"; 1726*724ba675SRob Herring 1727*724ba675SRob Herring avdd-pll-utmip-supply = <&vddio_1v8>; 1728*724ba675SRob Herring avdd-pll-erefe-supply = <&avdd_1v05_run>; 1729*724ba675SRob Herring avdd-pex-pll-supply = <&vdd_1v05_run>; 1730*724ba675SRob Herring hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; 1731*724ba675SRob Herring 1732*724ba675SRob Herring pads { 1733*724ba675SRob Herring usb2 { 1734*724ba675SRob Herring status = "okay"; 1735*724ba675SRob Herring 1736*724ba675SRob Herring lanes { 1737*724ba675SRob Herring usb2-0 { 1738*724ba675SRob Herring nvidia,function = "snps"; 1739*724ba675SRob Herring status = "okay"; 1740*724ba675SRob Herring }; 1741*724ba675SRob Herring 1742*724ba675SRob Herring usb2-1 { 1743*724ba675SRob Herring nvidia,function = "xusb"; 1744*724ba675SRob Herring status = "okay"; 1745*724ba675SRob Herring }; 1746*724ba675SRob Herring 1747*724ba675SRob Herring usb2-2 { 1748*724ba675SRob Herring nvidia,function = "xusb"; 1749*724ba675SRob Herring status = "okay"; 1750*724ba675SRob Herring }; 1751*724ba675SRob Herring }; 1752*724ba675SRob Herring }; 1753*724ba675SRob Herring 1754*724ba675SRob Herring pcie { 1755*724ba675SRob Herring status = "okay"; 1756*724ba675SRob Herring 1757*724ba675SRob Herring lanes { 1758*724ba675SRob Herring pcie-0 { 1759*724ba675SRob Herring nvidia,function = "usb3-ss"; 1760*724ba675SRob Herring status = "okay"; 1761*724ba675SRob Herring }; 1762*724ba675SRob Herring 1763*724ba675SRob Herring pcie-2 { 1764*724ba675SRob Herring nvidia,function = "pcie"; 1765*724ba675SRob Herring status = "okay"; 1766*724ba675SRob Herring }; 1767*724ba675SRob Herring 1768*724ba675SRob Herring pcie-4 { 1769*724ba675SRob Herring nvidia,function = "pcie"; 1770*724ba675SRob Herring status = "okay"; 1771*724ba675SRob Herring }; 1772*724ba675SRob Herring }; 1773*724ba675SRob Herring }; 1774*724ba675SRob Herring 1775*724ba675SRob Herring sata { 1776*724ba675SRob Herring status = "okay"; 1777*724ba675SRob Herring 1778*724ba675SRob Herring lanes { 1779*724ba675SRob Herring sata-0 { 1780*724ba675SRob Herring nvidia,function = "sata"; 1781*724ba675SRob Herring status = "okay"; 1782*724ba675SRob Herring }; 1783*724ba675SRob Herring }; 1784*724ba675SRob Herring }; 1785*724ba675SRob Herring }; 1786*724ba675SRob Herring 1787*724ba675SRob Herring ports { 1788*724ba675SRob Herring /* Micro A/B */ 1789*724ba675SRob Herring usb2-0 { 1790*724ba675SRob Herring status = "okay"; 1791*724ba675SRob Herring mode = "host"; 1792*724ba675SRob Herring }; 1793*724ba675SRob Herring 1794*724ba675SRob Herring /* Mini PCIe */ 1795*724ba675SRob Herring usb2-1 { 1796*724ba675SRob Herring status = "okay"; 1797*724ba675SRob Herring mode = "host"; 1798*724ba675SRob Herring }; 1799*724ba675SRob Herring 1800*724ba675SRob Herring /* USB3 */ 1801*724ba675SRob Herring usb2-2 { 1802*724ba675SRob Herring status = "okay"; 1803*724ba675SRob Herring mode = "host"; 1804*724ba675SRob Herring 1805*724ba675SRob Herring vbus-supply = <&vdd_usb3_vbus>; 1806*724ba675SRob Herring }; 1807*724ba675SRob Herring 1808*724ba675SRob Herring usb3-0 { 1809*724ba675SRob Herring nvidia,usb2-companion = <2>; 1810*724ba675SRob Herring status = "okay"; 1811*724ba675SRob Herring }; 1812*724ba675SRob Herring }; 1813*724ba675SRob Herring }; 1814*724ba675SRob Herring 1815*724ba675SRob Herring /* SD card */ 1816*724ba675SRob Herring mmc@700b0400 { 1817*724ba675SRob Herring status = "okay"; 1818*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1819*724ba675SRob Herring power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1820*724ba675SRob Herring wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; 1821*724ba675SRob Herring bus-width = <4>; 1822*724ba675SRob Herring vqmmc-supply = <&vddio_sdmmc3>; 1823*724ba675SRob Herring }; 1824*724ba675SRob Herring 1825*724ba675SRob Herring /* eMMC */ 1826*724ba675SRob Herring mmc@700b0600 { 1827*724ba675SRob Herring status = "okay"; 1828*724ba675SRob Herring bus-width = <8>; 1829*724ba675SRob Herring non-removable; 1830*724ba675SRob Herring }; 1831*724ba675SRob Herring 1832*724ba675SRob Herring /* CPU DFLL clock */ 1833*724ba675SRob Herring clock@70110000 { 1834*724ba675SRob Herring status = "okay"; 1835*724ba675SRob Herring vdd-cpu-supply = <&vdd_cpu>; 1836*724ba675SRob Herring nvidia,i2c-fs-rate = <400000>; 1837*724ba675SRob Herring }; 1838*724ba675SRob Herring 1839*724ba675SRob Herring ahub@70300000 { 1840*724ba675SRob Herring i2s@70301100 { 1841*724ba675SRob Herring status = "okay"; 1842*724ba675SRob Herring }; 1843*724ba675SRob Herring }; 1844*724ba675SRob Herring 1845*724ba675SRob Herring usb@7d000000 { 1846*724ba675SRob Herring compatible = "nvidia,tegra124-udc"; 1847*724ba675SRob Herring status = "okay"; 1848*724ba675SRob Herring dr_mode = "peripheral"; 1849*724ba675SRob Herring }; 1850*724ba675SRob Herring 1851*724ba675SRob Herring usb-phy@7d000000 { 1852*724ba675SRob Herring status = "okay"; 1853*724ba675SRob Herring }; 1854*724ba675SRob Herring 1855*724ba675SRob Herring /* mini-PCIe USB */ 1856*724ba675SRob Herring usb@7d004000 { 1857*724ba675SRob Herring status = "okay"; 1858*724ba675SRob Herring }; 1859*724ba675SRob Herring 1860*724ba675SRob Herring usb-phy@7d004000 { 1861*724ba675SRob Herring status = "okay"; 1862*724ba675SRob Herring }; 1863*724ba675SRob Herring 1864*724ba675SRob Herring /* USB A connector */ 1865*724ba675SRob Herring usb@7d008000 { 1866*724ba675SRob Herring status = "okay"; 1867*724ba675SRob Herring }; 1868*724ba675SRob Herring 1869*724ba675SRob Herring usb-phy@7d008000 { 1870*724ba675SRob Herring status = "okay"; 1871*724ba675SRob Herring vbus-supply = <&vdd_usb3_vbus>; 1872*724ba675SRob Herring }; 1873*724ba675SRob Herring 1874*724ba675SRob Herring clk32k_in: clock-32k { 1875*724ba675SRob Herring compatible = "fixed-clock"; 1876*724ba675SRob Herring clock-frequency = <32768>; 1877*724ba675SRob Herring #clock-cells = <0>; 1878*724ba675SRob Herring }; 1879*724ba675SRob Herring 1880*724ba675SRob Herring cpus { 1881*724ba675SRob Herring cpu@0 { 1882*724ba675SRob Herring vdd-cpu-supply = <&vdd_cpu>; 1883*724ba675SRob Herring }; 1884*724ba675SRob Herring }; 1885*724ba675SRob Herring 1886*724ba675SRob Herring gpio-keys { 1887*724ba675SRob Herring compatible = "gpio-keys"; 1888*724ba675SRob Herring 1889*724ba675SRob Herring key-power { 1890*724ba675SRob Herring label = "Power"; 1891*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1892*724ba675SRob Herring linux,code = <KEY_POWER>; 1893*724ba675SRob Herring debounce-interval = <10>; 1894*724ba675SRob Herring wakeup-source; 1895*724ba675SRob Herring }; 1896*724ba675SRob Herring }; 1897*724ba675SRob Herring 1898*724ba675SRob Herring vdd_mux: regulator-mux { 1899*724ba675SRob Herring compatible = "regulator-fixed"; 1900*724ba675SRob Herring regulator-name = "+VDD_MUX"; 1901*724ba675SRob Herring regulator-min-microvolt = <12000000>; 1902*724ba675SRob Herring regulator-max-microvolt = <12000000>; 1903*724ba675SRob Herring regulator-always-on; 1904*724ba675SRob Herring regulator-boot-on; 1905*724ba675SRob Herring }; 1906*724ba675SRob Herring 1907*724ba675SRob Herring vdd_5v0_sys: regulator-5v0sys { 1908*724ba675SRob Herring compatible = "regulator-fixed"; 1909*724ba675SRob Herring regulator-name = "+5V_SYS"; 1910*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1911*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1912*724ba675SRob Herring regulator-always-on; 1913*724ba675SRob Herring regulator-boot-on; 1914*724ba675SRob Herring vin-supply = <&vdd_mux>; 1915*724ba675SRob Herring }; 1916*724ba675SRob Herring 1917*724ba675SRob Herring vdd_3v3_sys: regulator-3v3sys { 1918*724ba675SRob Herring compatible = "regulator-fixed"; 1919*724ba675SRob Herring regulator-name = "+3.3V_SYS"; 1920*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1921*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1922*724ba675SRob Herring regulator-always-on; 1923*724ba675SRob Herring regulator-boot-on; 1924*724ba675SRob Herring vin-supply = <&vdd_mux>; 1925*724ba675SRob Herring }; 1926*724ba675SRob Herring 1927*724ba675SRob Herring vdd_3v3_run: regulator-3v3run { 1928*724ba675SRob Herring compatible = "regulator-fixed"; 1929*724ba675SRob Herring regulator-name = "+3.3V_RUN"; 1930*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1931*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1932*724ba675SRob Herring regulator-always-on; 1933*724ba675SRob Herring regulator-boot-on; 1934*724ba675SRob Herring gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 1935*724ba675SRob Herring enable-active-high; 1936*724ba675SRob Herring vin-supply = <&vdd_3v3_sys>; 1937*724ba675SRob Herring }; 1938*724ba675SRob Herring 1939*724ba675SRob Herring vdd_3v3_hdmi: regulator-3v3hdmi { 1940*724ba675SRob Herring compatible = "regulator-fixed"; 1941*724ba675SRob Herring regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; 1942*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1943*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1944*724ba675SRob Herring vin-supply = <&vdd_3v3_run>; 1945*724ba675SRob Herring }; 1946*724ba675SRob Herring 1947*724ba675SRob Herring vdd_usb1_vbus: regulator-usb1 { 1948*724ba675SRob Herring compatible = "regulator-fixed"; 1949*724ba675SRob Herring regulator-name = "+USB0_VBUS_SW"; 1950*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1951*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1952*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 1953*724ba675SRob Herring enable-active-high; 1954*724ba675SRob Herring gpio-open-drain; 1955*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1956*724ba675SRob Herring }; 1957*724ba675SRob Herring 1958*724ba675SRob Herring vdd_usb3_vbus: regulator-usb3 { 1959*724ba675SRob Herring compatible = "regulator-fixed"; 1960*724ba675SRob Herring regulator-name = "+5V_USB_HS"; 1961*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1962*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1963*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; 1964*724ba675SRob Herring enable-active-high; 1965*724ba675SRob Herring gpio-open-drain; 1966*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1967*724ba675SRob Herring }; 1968*724ba675SRob Herring 1969*724ba675SRob Herring vdd_3v3_lp0: regulator-lp0 { 1970*724ba675SRob Herring compatible = "regulator-fixed"; 1971*724ba675SRob Herring regulator-name = "+3.3V_LP0"; 1972*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1973*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1974*724ba675SRob Herring regulator-always-on; 1975*724ba675SRob Herring regulator-boot-on; 1976*724ba675SRob Herring gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 1977*724ba675SRob Herring enable-active-high; 1978*724ba675SRob Herring vin-supply = <&vdd_3v3_sys>; 1979*724ba675SRob Herring }; 1980*724ba675SRob Herring 1981*724ba675SRob Herring vdd_hdmi_pll: regulator-hdmipll { 1982*724ba675SRob Herring compatible = "regulator-fixed"; 1983*724ba675SRob Herring regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; 1984*724ba675SRob Herring regulator-min-microvolt = <1050000>; 1985*724ba675SRob Herring regulator-max-microvolt = <1050000>; 1986*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1987*724ba675SRob Herring vin-supply = <&vdd_1v05_run>; 1988*724ba675SRob Herring }; 1989*724ba675SRob Herring 1990*724ba675SRob Herring vdd_5v0_hdmi: regulator-hdmicon { 1991*724ba675SRob Herring compatible = "regulator-fixed"; 1992*724ba675SRob Herring regulator-name = "+5V_HDMI_CON"; 1993*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1994*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1995*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1996*724ba675SRob Herring enable-active-high; 1997*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1998*724ba675SRob Herring }; 1999*724ba675SRob Herring 2000*724ba675SRob Herring /* Molex power connector */ 2001*724ba675SRob Herring vdd_5v0_sata: regulator-5v0sata { 2002*724ba675SRob Herring compatible = "regulator-fixed"; 2003*724ba675SRob Herring regulator-name = "+5V_SATA"; 2004*724ba675SRob Herring regulator-min-microvolt = <5000000>; 2005*724ba675SRob Herring regulator-max-microvolt = <5000000>; 2006*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; 2007*724ba675SRob Herring enable-active-high; 2008*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 2009*724ba675SRob Herring }; 2010*724ba675SRob Herring 2011*724ba675SRob Herring vdd_12v0_sata: regulator-12v0sata { 2012*724ba675SRob Herring compatible = "regulator-fixed"; 2013*724ba675SRob Herring regulator-name = "+12V_SATA"; 2014*724ba675SRob Herring regulator-min-microvolt = <12000000>; 2015*724ba675SRob Herring regulator-max-microvolt = <12000000>; 2016*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; 2017*724ba675SRob Herring enable-active-high; 2018*724ba675SRob Herring vin-supply = <&vdd_mux>; 2019*724ba675SRob Herring }; 2020*724ba675SRob Herring 2021*724ba675SRob Herring sound { 2022*724ba675SRob Herring compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", 2023*724ba675SRob Herring "nvidia,tegra-audio-rt5640"; 2024*724ba675SRob Herring nvidia,model = "NVIDIA Tegra Jetson TK1"; 2025*724ba675SRob Herring 2026*724ba675SRob Herring nvidia,audio-routing = 2027*724ba675SRob Herring "Headphones", "HPOR", 2028*724ba675SRob Herring "Headphones", "HPOL", 2029*724ba675SRob Herring "Mic Jack", "MICBIAS1", 2030*724ba675SRob Herring "IN2P", "Mic Jack"; 2031*724ba675SRob Herring 2032*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 2033*724ba675SRob Herring nvidia,audio-codec = <&rt5639>; 2034*724ba675SRob Herring 2035*724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; 2036*724ba675SRob Herring 2037*724ba675SRob Herring clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 2038*724ba675SRob Herring <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2039*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2040*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 2041*724ba675SRob Herring 2042*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, 2043*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2044*724ba675SRob Herring 2045*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2046*724ba675SRob Herring <&tegra_car TEGRA124_CLK_EXTERN1>; 2047*724ba675SRob Herring }; 2048*724ba675SRob Herring 2049*724ba675SRob Herring thermal-zones { 2050*724ba675SRob Herring cpu-thermal { 2051*724ba675SRob Herring trips { 2052*724ba675SRob Herring cpu-shutdown-trip { 2053*724ba675SRob Herring temperature = <101000>; 2054*724ba675SRob Herring hysteresis = <0>; 2055*724ba675SRob Herring type = "critical"; 2056*724ba675SRob Herring }; 2057*724ba675SRob Herring }; 2058*724ba675SRob Herring }; 2059*724ba675SRob Herring 2060*724ba675SRob Herring mem-thermal { 2061*724ba675SRob Herring trips { 2062*724ba675SRob Herring mem-shutdown-trip { 2063*724ba675SRob Herring temperature = <101000>; 2064*724ba675SRob Herring hysteresis = <0>; 2065*724ba675SRob Herring type = "critical"; 2066*724ba675SRob Herring }; 2067*724ba675SRob Herring }; 2068*724ba675SRob Herring }; 2069*724ba675SRob Herring 2070*724ba675SRob Herring gpu-thermal { 2071*724ba675SRob Herring trips { 2072*724ba675SRob Herring gpu-shutdown-trip { 2073*724ba675SRob Herring temperature = <101000>; 2074*724ba675SRob Herring hysteresis = <0>; 2075*724ba675SRob Herring type = "critical"; 2076*724ba675SRob Herring }; 2077*724ba675SRob Herring }; 2078*724ba675SRob Herring }; 2079*724ba675SRob Herring }; 2080*724ba675SRob Herring}; 2081