xref: /linux/scripts/dtc/include-prefixes/arm/nvidia/tegra114-roth.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/dts-v1/;
3*724ba675SRob Herring
4*724ba675SRob Herring#include <dt-bindings/input/input.h>
5*724ba675SRob Herring#include "tegra114.dtsi"
6*724ba675SRob Herring
7*724ba675SRob Herring/ {
8*724ba675SRob Herring	model = "NVIDIA SHIELD";
9*724ba675SRob Herring	compatible = "nvidia,roth", "nvidia,tegra114";
10*724ba675SRob Herring
11*724ba675SRob Herring	chosen {
12*724ba675SRob Herring		/* SHIELD's bootloader's arguments need to be overridden */
13*724ba675SRob Herring		bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
14*724ba675SRob Herring		/* SHIELD's bootloader will place initrd at this address */
15*724ba675SRob Herring		linux,initrd-start = <0x82000000>;
16*724ba675SRob Herring		linux,initrd-end = <0x82800000>;
17*724ba675SRob Herring	};
18*724ba675SRob Herring
19*724ba675SRob Herring	aliases {
20*724ba675SRob Herring		serial0 = &uartd;
21*724ba675SRob Herring	};
22*724ba675SRob Herring
23*724ba675SRob Herring	firmware {
24*724ba675SRob Herring		trusted-foundations {
25*724ba675SRob Herring			compatible = "tlm,trusted-foundations";
26*724ba675SRob Herring			tlm,version-major = <2>;
27*724ba675SRob Herring			tlm,version-minor = <8>;
28*724ba675SRob Herring		};
29*724ba675SRob Herring	};
30*724ba675SRob Herring
31*724ba675SRob Herring	memory@80000000 {
32*724ba675SRob Herring		/* memory >= 0x79600000 is reserved for firmware usage */
33*724ba675SRob Herring		reg = <0x80000000 0x79600000>;
34*724ba675SRob Herring	};
35*724ba675SRob Herring
36*724ba675SRob Herring	host1x@50000000 {
37*724ba675SRob Herring		dsi@54300000 {
38*724ba675SRob Herring			status = "okay";
39*724ba675SRob Herring
40*724ba675SRob Herring			avdd-dsi-csi-supply = <&vdd_1v2_ap>;
41*724ba675SRob Herring
42*724ba675SRob Herring			panel@0 {
43*724ba675SRob Herring				compatible = "lg,lh500wx1-sd03";
44*724ba675SRob Herring				reg = <0>;
45*724ba675SRob Herring
46*724ba675SRob Herring				power-supply = <&vdd_lcd>;
47*724ba675SRob Herring				backlight = <&backlight>;
48*724ba675SRob Herring			};
49*724ba675SRob Herring		};
50*724ba675SRob Herring	};
51*724ba675SRob Herring
52*724ba675SRob Herring	pinmux@70000868 {
53*724ba675SRob Herring		pinctrl-names = "default";
54*724ba675SRob Herring		pinctrl-0 = <&state_default>;
55*724ba675SRob Herring
56*724ba675SRob Herring		state_default: pinmux {
57*724ba675SRob Herring			clk1_out_pw4 {
58*724ba675SRob Herring				nvidia,pins = "clk1_out_pw4";
59*724ba675SRob Herring				nvidia,function = "extperiph1";
60*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
62*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63*724ba675SRob Herring			};
64*724ba675SRob Herring			dap1_din_pn1 {
65*724ba675SRob Herring				nvidia,pins = "dap1_din_pn1";
66*724ba675SRob Herring				nvidia,function = "i2s0";
67*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
69*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
70*724ba675SRob Herring			};
71*724ba675SRob Herring			dap1_dout_pn2 {
72*724ba675SRob Herring				nvidia,pins = "dap1_dout_pn2",
73*724ba675SRob Herring						"dap1_fs_pn0",
74*724ba675SRob Herring						"dap1_sclk_pn3";
75*724ba675SRob Herring				nvidia,function = "i2s0";
76*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
78*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
79*724ba675SRob Herring			};
80*724ba675SRob Herring			dap2_din_pa4 {
81*724ba675SRob Herring				nvidia,pins = "dap2_din_pa4";
82*724ba675SRob Herring				nvidia,function = "i2s1";
83*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
85*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86*724ba675SRob Herring			};
87*724ba675SRob Herring			dap2_dout_pa5 {
88*724ba675SRob Herring				nvidia,pins = "dap2_dout_pa5",
89*724ba675SRob Herring						"dap2_fs_pa2",
90*724ba675SRob Herring						"dap2_sclk_pa3";
91*724ba675SRob Herring				nvidia,function = "i2s1";
92*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
94*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
95*724ba675SRob Herring			};
96*724ba675SRob Herring			dap4_din_pp5 {
97*724ba675SRob Herring				nvidia,pins = "dap4_din_pp5",
98*724ba675SRob Herring						"dap4_dout_pp6",
99*724ba675SRob Herring						"dap4_fs_pp4",
100*724ba675SRob Herring						"dap4_sclk_pp7";
101*724ba675SRob Herring				nvidia,function = "i2s3";
102*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
104*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
105*724ba675SRob Herring			};
106*724ba675SRob Herring			dvfs_pwm_px0 {
107*724ba675SRob Herring				nvidia,pins = "dvfs_pwm_px0",
108*724ba675SRob Herring						"dvfs_clk_px2";
109*724ba675SRob Herring				nvidia,function = "cldvfs";
110*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
112*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
113*724ba675SRob Herring			};
114*724ba675SRob Herring			ulpi_clk_py0 {
115*724ba675SRob Herring				nvidia,pins = "ulpi_clk_py0",
116*724ba675SRob Herring						"ulpi_data0_po1",
117*724ba675SRob Herring						"ulpi_data1_po2",
118*724ba675SRob Herring						"ulpi_data2_po3",
119*724ba675SRob Herring						"ulpi_data3_po4",
120*724ba675SRob Herring						"ulpi_data4_po5",
121*724ba675SRob Herring						"ulpi_data5_po6",
122*724ba675SRob Herring						"ulpi_data6_po7",
123*724ba675SRob Herring						"ulpi_data7_po0";
124*724ba675SRob Herring				nvidia,function = "ulpi";
125*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
127*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128*724ba675SRob Herring			};
129*724ba675SRob Herring			ulpi_dir_py1 {
130*724ba675SRob Herring				nvidia,pins = "ulpi_dir_py1",
131*724ba675SRob Herring						"ulpi_nxt_py2";
132*724ba675SRob Herring				nvidia,function = "ulpi";
133*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
134*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
135*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
136*724ba675SRob Herring			};
137*724ba675SRob Herring			ulpi_stp_py3 {
138*724ba675SRob Herring				nvidia,pins = "ulpi_stp_py3";
139*724ba675SRob Herring				nvidia,function = "ulpi";
140*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
142*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
143*724ba675SRob Herring			};
144*724ba675SRob Herring			cam_i2c_scl_pbb1 {
145*724ba675SRob Herring				nvidia,pins = "cam_i2c_scl_pbb1",
146*724ba675SRob Herring						"cam_i2c_sda_pbb2";
147*724ba675SRob Herring				nvidia,function = "i2c3";
148*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
150*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
151*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
152*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
153*724ba675SRob Herring			};
154*724ba675SRob Herring			cam_mclk_pcc0 {
155*724ba675SRob Herring				nvidia,pins = "cam_mclk_pcc0",
156*724ba675SRob Herring						"pbb0";
157*724ba675SRob Herring				nvidia,function = "vi_alt3";
158*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
160*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
161*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
162*724ba675SRob Herring			};
163*724ba675SRob Herring			pbb4 {
164*724ba675SRob Herring				nvidia,pins = "pbb4";
165*724ba675SRob Herring				nvidia,function = "vgp4";
166*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
170*724ba675SRob Herring			};
171*724ba675SRob Herring			gen2_i2c_scl_pt5 {
172*724ba675SRob Herring				nvidia,pins = "gen2_i2c_scl_pt5",
173*724ba675SRob Herring						"gen2_i2c_sda_pt6";
174*724ba675SRob Herring				nvidia,function = "i2c2";
175*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
177*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
179*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
180*724ba675SRob Herring			};
181*724ba675SRob Herring			gmi_a16_pj7 {
182*724ba675SRob Herring				nvidia,pins = "gmi_a16_pj7",
183*724ba675SRob Herring						"gmi_a19_pk7";
184*724ba675SRob Herring				nvidia,function = "uartd";
185*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
187*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188*724ba675SRob Herring			};
189*724ba675SRob Herring			gmi_a17_pb0 {
190*724ba675SRob Herring				nvidia,pins = "gmi_a17_pb0",
191*724ba675SRob Herring						"gmi_a18_pb1";
192*724ba675SRob Herring				nvidia,function = "uartd";
193*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
195*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
196*724ba675SRob Herring			};
197*724ba675SRob Herring			gmi_ad5_pg5 {
198*724ba675SRob Herring				nvidia,pins = "gmi_ad5_pg5",
199*724ba675SRob Herring						"gmi_wr_n_pi0";
200*724ba675SRob Herring				nvidia,function = "spi4";
201*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
203*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
204*724ba675SRob Herring			};
205*724ba675SRob Herring			gmi_ad6_pg6 {
206*724ba675SRob Herring				nvidia,pins = "gmi_ad6_pg6",
207*724ba675SRob Herring						"gmi_ad7_pg7";
208*724ba675SRob Herring				nvidia,function = "spi4";
209*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
210*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
211*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
212*724ba675SRob Herring			};
213*724ba675SRob Herring			gmi_ad12_ph4 {
214*724ba675SRob Herring				nvidia,pins = "gmi_ad12_ph4";
215*724ba675SRob Herring				nvidia,function = "rsvd4";
216*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
217*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
218*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219*724ba675SRob Herring			};
220*724ba675SRob Herring			gmi_cs6_n_pi13 {
221*724ba675SRob Herring				nvidia,pins = "gmi_cs6_n_pi3";
222*724ba675SRob Herring				nvidia,function = "nand";
223*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
225*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226*724ba675SRob Herring			};
227*724ba675SRob Herring			gmi_ad9_ph1 {
228*724ba675SRob Herring				nvidia,pins = "gmi_ad9_ph1";
229*724ba675SRob Herring				nvidia,function = "pwm1";
230*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
232*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233*724ba675SRob Herring			};
234*724ba675SRob Herring			gmi_cs1_n_pj2 {
235*724ba675SRob Herring				nvidia,pins = "gmi_cs1_n_pj2",
236*724ba675SRob Herring						"gmi_oe_n_pi1";
237*724ba675SRob Herring				nvidia,function = "soc";
238*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
240*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241*724ba675SRob Herring			};
242*724ba675SRob Herring			gmi_rst_n_pi4 {
243*724ba675SRob Herring				nvidia,pins = "gmi_rst_n_pi4";
244*724ba675SRob Herring				nvidia,function = "gmi";
245*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
246*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
247*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248*724ba675SRob Herring			};
249*724ba675SRob Herring			gmi_iordy_pi5 {
250*724ba675SRob Herring				nvidia,pins = "gmi_iordy_pi5";
251*724ba675SRob Herring				nvidia,function = "gmi";
252*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
254*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255*724ba675SRob Herring			};
256*724ba675SRob Herring			clk2_out_pw5 {
257*724ba675SRob Herring				nvidia,pins = "clk2_out_pw5";
258*724ba675SRob Herring				nvidia,function = "extperiph2";
259*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
261*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262*724ba675SRob Herring			};
263*724ba675SRob Herring			sdmmc1_clk_pz0 {
264*724ba675SRob Herring				nvidia,pins = "sdmmc1_clk_pz0";
265*724ba675SRob Herring				nvidia,function = "sdmmc1";
266*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
268*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269*724ba675SRob Herring			};
270*724ba675SRob Herring			sdmmc1_cmd_pz1 {
271*724ba675SRob Herring				nvidia,pins = "sdmmc1_cmd_pz1",
272*724ba675SRob Herring						"sdmmc1_dat0_py7",
273*724ba675SRob Herring						"sdmmc1_dat1_py6",
274*724ba675SRob Herring						"sdmmc1_dat2_py5",
275*724ba675SRob Herring						"sdmmc1_dat3_py4";
276*724ba675SRob Herring				nvidia,function = "sdmmc1";
277*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
278*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
279*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280*724ba675SRob Herring			};
281*724ba675SRob Herring			sdmmc3_clk_pa6 {
282*724ba675SRob Herring				nvidia,pins = "sdmmc3_clk_pa6";
283*724ba675SRob Herring				nvidia,function = "sdmmc3";
284*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
285*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
286*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
287*724ba675SRob Herring			};
288*724ba675SRob Herring			sdmmc3_cmd_pa7 {
289*724ba675SRob Herring				nvidia,pins = "sdmmc3_cmd_pa7",
290*724ba675SRob Herring						"sdmmc3_dat0_pb7",
291*724ba675SRob Herring						"sdmmc3_dat1_pb6",
292*724ba675SRob Herring						"sdmmc3_dat2_pb5",
293*724ba675SRob Herring						"sdmmc3_dat3_pb4",
294*724ba675SRob Herring						"sdmmc3_cd_n_pv2",
295*724ba675SRob Herring						"sdmmc3_clk_lb_out_pee4",
296*724ba675SRob Herring						"sdmmc3_clk_lb_in_pee5";
297*724ba675SRob Herring				nvidia,function = "sdmmc3";
298*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
299*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
300*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
301*724ba675SRob Herring			};
302*724ba675SRob Herring			kb_col4_pq4 {
303*724ba675SRob Herring				nvidia,pins = "kb_col4_pq4";
304*724ba675SRob Herring				nvidia,function = "sdmmc3";
305*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
306*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
307*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308*724ba675SRob Herring			};
309*724ba675SRob Herring			sdmmc4_clk_pcc4 {
310*724ba675SRob Herring				nvidia,pins = "sdmmc4_clk_pcc4";
311*724ba675SRob Herring				nvidia,function = "sdmmc4";
312*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
314*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315*724ba675SRob Herring			};
316*724ba675SRob Herring			sdmmc4_cmd_pt7 {
317*724ba675SRob Herring				nvidia,pins = "sdmmc4_cmd_pt7",
318*724ba675SRob Herring						"sdmmc4_dat0_paa0",
319*724ba675SRob Herring						"sdmmc4_dat1_paa1",
320*724ba675SRob Herring						"sdmmc4_dat2_paa2",
321*724ba675SRob Herring						"sdmmc4_dat3_paa3",
322*724ba675SRob Herring						"sdmmc4_dat4_paa4",
323*724ba675SRob Herring						"sdmmc4_dat5_paa5",
324*724ba675SRob Herring						"sdmmc4_dat6_paa6",
325*724ba675SRob Herring						"sdmmc4_dat7_paa7";
326*724ba675SRob Herring				nvidia,function = "sdmmc4";
327*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
328*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
329*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
330*724ba675SRob Herring			};
331*724ba675SRob Herring			clk_32k_out_pa0 {
332*724ba675SRob Herring				nvidia,pins = "clk_32k_out_pa0";
333*724ba675SRob Herring				nvidia,function = "blink";
334*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
335*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
336*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
337*724ba675SRob Herring			};
338*724ba675SRob Herring			kb_col0_pq0 {
339*724ba675SRob Herring				nvidia,pins = "kb_col0_pq0",
340*724ba675SRob Herring						"kb_col1_pq1",
341*724ba675SRob Herring						"kb_col2_pq2",
342*724ba675SRob Herring						"kb_row0_pr0",
343*724ba675SRob Herring						"kb_row1_pr1",
344*724ba675SRob Herring						"kb_row2_pr2",
345*724ba675SRob Herring						"kb_row8_ps0";
346*724ba675SRob Herring				nvidia,function = "kbc";
347*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
348*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
349*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350*724ba675SRob Herring			};
351*724ba675SRob Herring			kb_row7_pr7 {
352*724ba675SRob Herring				nvidia,pins = "kb_row7_pr7";
353*724ba675SRob Herring				nvidia,function = "rsvd2";
354*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
355*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
356*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
357*724ba675SRob Herring			};
358*724ba675SRob Herring			kb_row10_ps2 {
359*724ba675SRob Herring				nvidia,pins = "kb_row10_ps2";
360*724ba675SRob Herring				nvidia,function = "uarta";
361*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
363*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364*724ba675SRob Herring			};
365*724ba675SRob Herring			kb_row9_ps1 {
366*724ba675SRob Herring				nvidia,pins = "kb_row9_ps1";
367*724ba675SRob Herring				nvidia,function = "uarta";
368*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
370*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
371*724ba675SRob Herring			};
372*724ba675SRob Herring			pwr_i2c_scl_pz6 {
373*724ba675SRob Herring				nvidia,pins = "pwr_i2c_scl_pz6",
374*724ba675SRob Herring						"pwr_i2c_sda_pz7";
375*724ba675SRob Herring				nvidia,function = "i2cpwr";
376*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
378*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
380*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381*724ba675SRob Herring			};
382*724ba675SRob Herring			sys_clk_req_pz5 {
383*724ba675SRob Herring				nvidia,pins = "sys_clk_req_pz5";
384*724ba675SRob Herring				nvidia,function = "sysclk";
385*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
386*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
387*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
388*724ba675SRob Herring			};
389*724ba675SRob Herring			core_pwr_req {
390*724ba675SRob Herring				nvidia,pins = "core_pwr_req";
391*724ba675SRob Herring				nvidia,function = "pwron";
392*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
395*724ba675SRob Herring			};
396*724ba675SRob Herring			cpu_pwr_req {
397*724ba675SRob Herring				nvidia,pins = "cpu_pwr_req";
398*724ba675SRob Herring				nvidia,function = "cpu";
399*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
401*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402*724ba675SRob Herring			};
403*724ba675SRob Herring			pwr_int_n {
404*724ba675SRob Herring				nvidia,pins = "pwr_int_n";
405*724ba675SRob Herring				nvidia,function = "pmi";
406*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
408*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409*724ba675SRob Herring			};
410*724ba675SRob Herring			reset_out_n {
411*724ba675SRob Herring				nvidia,pins = "reset_out_n";
412*724ba675SRob Herring				nvidia,function = "reset_out_n";
413*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
415*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
416*724ba675SRob Herring			};
417*724ba675SRob Herring			clk3_out_pee0 {
418*724ba675SRob Herring				nvidia,pins = "clk3_out_pee0";
419*724ba675SRob Herring				nvidia,function = "extperiph3";
420*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
422*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
423*724ba675SRob Herring			};
424*724ba675SRob Herring			gen1_i2c_scl_pc4 {
425*724ba675SRob Herring				nvidia,pins = "gen1_i2c_scl_pc4",
426*724ba675SRob Herring						"gen1_i2c_sda_pc5";
427*724ba675SRob Herring				nvidia,function = "i2c1";
428*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
430*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
431*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
432*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
433*724ba675SRob Herring			};
434*724ba675SRob Herring			uart2_cts_n_pj5 {
435*724ba675SRob Herring				nvidia,pins = "uart2_cts_n_pj5";
436*724ba675SRob Herring				nvidia,function = "uartb";
437*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
439*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
440*724ba675SRob Herring			};
441*724ba675SRob Herring			uart2_rts_n_pj6 {
442*724ba675SRob Herring				nvidia,pins = "uart2_rts_n_pj6";
443*724ba675SRob Herring				nvidia,function = "uartb";
444*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
446*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
447*724ba675SRob Herring			};
448*724ba675SRob Herring			uart2_rxd_pc3 {
449*724ba675SRob Herring				nvidia,pins = "uart2_rxd_pc3";
450*724ba675SRob Herring				nvidia,function = "irda";
451*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
452*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
453*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
454*724ba675SRob Herring			};
455*724ba675SRob Herring			uart2_txd_pc2 {
456*724ba675SRob Herring				nvidia,pins = "uart2_txd_pc2";
457*724ba675SRob Herring				nvidia,function = "irda";
458*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
460*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
461*724ba675SRob Herring			};
462*724ba675SRob Herring			uart3_cts_n_pa1 {
463*724ba675SRob Herring				nvidia,pins = "uart3_cts_n_pa1",
464*724ba675SRob Herring						"uart3_rxd_pw7";
465*724ba675SRob Herring				nvidia,function = "uartc";
466*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
468*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469*724ba675SRob Herring			};
470*724ba675SRob Herring			uart3_rts_n_pc0 {
471*724ba675SRob Herring				nvidia,pins = "uart3_rts_n_pc0",
472*724ba675SRob Herring						"uart3_txd_pw6";
473*724ba675SRob Herring				nvidia,function = "uartc";
474*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
475*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
476*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477*724ba675SRob Herring			};
478*724ba675SRob Herring			owr {
479*724ba675SRob Herring				nvidia,pins = "owr";
480*724ba675SRob Herring				nvidia,function = "owr";
481*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
483*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484*724ba675SRob Herring			};
485*724ba675SRob Herring			hdmi_cec_pee3 {
486*724ba675SRob Herring				nvidia,pins = "hdmi_cec_pee3";
487*724ba675SRob Herring				nvidia,function = "cec";
488*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
489*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
490*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
492*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
493*724ba675SRob Herring			};
494*724ba675SRob Herring			ddc_scl_pv4 {
495*724ba675SRob Herring				nvidia,pins = "ddc_scl_pv4",
496*724ba675SRob Herring						"ddc_sda_pv5";
497*724ba675SRob Herring				nvidia,function = "i2c4";
498*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
499*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
500*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
501*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
502*724ba675SRob Herring				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
503*724ba675SRob Herring			};
504*724ba675SRob Herring			spdif_in_pk6 {
505*724ba675SRob Herring				nvidia,pins = "spdif_in_pk6";
506*724ba675SRob Herring				nvidia,function = "usb";
507*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
508*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
509*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
511*724ba675SRob Herring			};
512*724ba675SRob Herring			usb_vbus_en0_pn4 {
513*724ba675SRob Herring				nvidia,pins = "usb_vbus_en0_pn4";
514*724ba675SRob Herring				nvidia,function = "usb";
515*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
516*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
517*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
518*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
519*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
520*724ba675SRob Herring			};
521*724ba675SRob Herring			gpio_x6_aud_px6 {
522*724ba675SRob Herring				nvidia,pins = "gpio_x6_aud_px6";
523*724ba675SRob Herring				nvidia,function = "spi6";
524*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
525*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
526*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
527*724ba675SRob Herring			};
528*724ba675SRob Herring			gpio_x1_aud_px1 {
529*724ba675SRob Herring				nvidia,pins = "gpio_x1_aud_px1";
530*724ba675SRob Herring				nvidia,function = "rsvd2";
531*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
532*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
533*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
534*724ba675SRob Herring			};
535*724ba675SRob Herring			gpio_x7_aud_px7 {
536*724ba675SRob Herring				nvidia,pins = "gpio_x7_aud_px7";
537*724ba675SRob Herring				nvidia,function = "rsvd1";
538*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
539*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
540*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
541*724ba675SRob Herring			};
542*724ba675SRob Herring			gmi_adv_n_pk0 {
543*724ba675SRob Herring				nvidia,pins = "gmi_adv_n_pk0";
544*724ba675SRob Herring				nvidia,function = "gmi";
545*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
547*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
548*724ba675SRob Herring			};
549*724ba675SRob Herring			gmi_cs0_n_pj0 {
550*724ba675SRob Herring				nvidia,pins = "gmi_cs0_n_pj0";
551*724ba675SRob Herring				nvidia,function = "gmi";
552*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
553*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
554*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555*724ba675SRob Herring			};
556*724ba675SRob Herring			pu3 {
557*724ba675SRob Herring				nvidia,pins = "pu3";
558*724ba675SRob Herring				nvidia,function = "pwm0";
559*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
560*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
561*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
562*724ba675SRob Herring			};
563*724ba675SRob Herring			gpio_x4_aud_px4 {
564*724ba675SRob Herring				nvidia,pins = "gpio_x4_aud_px4",
565*724ba675SRob Herring						"gpio_x5_aud_px5";
566*724ba675SRob Herring				nvidia,function = "rsvd1";
567*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
568*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
569*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570*724ba675SRob Herring			};
571*724ba675SRob Herring			gpio_x3_aud_px3 {
572*724ba675SRob Herring				nvidia,pins = "gpio_x3_aud_px3";
573*724ba675SRob Herring				nvidia,function = "rsvd4";
574*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
575*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
576*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577*724ba675SRob Herring			};
578*724ba675SRob Herring			gpio_w2_aud_pw2 {
579*724ba675SRob Herring				nvidia,pins = "gpio_w2_aud_pw2";
580*724ba675SRob Herring				nvidia,function = "rsvd2";
581*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
582*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
583*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
584*724ba675SRob Herring			};
585*724ba675SRob Herring			gpio_w3_aud_pw3 {
586*724ba675SRob Herring				nvidia,pins = "gpio_w3_aud_pw3";
587*724ba675SRob Herring				nvidia,function = "spi6";
588*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
589*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
590*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
591*724ba675SRob Herring			};
592*724ba675SRob Herring			dap3_fs_pp0 {
593*724ba675SRob Herring				nvidia,pins = "dap3_fs_pp0",
594*724ba675SRob Herring						"dap3_din_pp1",
595*724ba675SRob Herring						"dap3_dout_pp2",
596*724ba675SRob Herring						"dap3_sclk_pp3";
597*724ba675SRob Herring				nvidia,function = "i2s2";
598*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
599*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
600*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
601*724ba675SRob Herring			};
602*724ba675SRob Herring			pv0 {
603*724ba675SRob Herring				nvidia,pins = "pv0";
604*724ba675SRob Herring				nvidia,function = "rsvd4";
605*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
607*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
608*724ba675SRob Herring			};
609*724ba675SRob Herring			pv1 {
610*724ba675SRob Herring				nvidia,pins = "pv1";
611*724ba675SRob Herring				nvidia,function = "rsvd1";
612*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
614*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615*724ba675SRob Herring			};
616*724ba675SRob Herring			pbb3 {
617*724ba675SRob Herring				nvidia,pins = "pbb3",
618*724ba675SRob Herring						"pbb5",
619*724ba675SRob Herring						"pbb6",
620*724ba675SRob Herring						"pbb7";
621*724ba675SRob Herring				nvidia,function = "rsvd4";
622*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
623*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
624*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
625*724ba675SRob Herring			};
626*724ba675SRob Herring			pcc1 {
627*724ba675SRob Herring				nvidia,pins = "pcc1",
628*724ba675SRob Herring						"pcc2";
629*724ba675SRob Herring				nvidia,function = "rsvd4";
630*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
631*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
632*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
633*724ba675SRob Herring			};
634*724ba675SRob Herring			gmi_ad0_pg0 {
635*724ba675SRob Herring				nvidia,pins = "gmi_ad0_pg0",
636*724ba675SRob Herring						"gmi_ad1_pg1";
637*724ba675SRob Herring				nvidia,function = "gmi";
638*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
639*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
640*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
641*724ba675SRob Herring			};
642*724ba675SRob Herring			gmi_ad10_ph2 {
643*724ba675SRob Herring				nvidia,pins = "gmi_ad10_ph2",
644*724ba675SRob Herring						"gmi_ad12_ph4",
645*724ba675SRob Herring						"gmi_ad15_ph7",
646*724ba675SRob Herring						"gmi_cs3_n_pk4";
647*724ba675SRob Herring				nvidia,function = "gmi";
648*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
649*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
650*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651*724ba675SRob Herring			};
652*724ba675SRob Herring			gmi_ad11_ph3 {
653*724ba675SRob Herring				nvidia,pins = "gmi_ad11_ph3",
654*724ba675SRob Herring						"gmi_ad13_ph5",
655*724ba675SRob Herring						"gmi_ad8_ph0",
656*724ba675SRob Herring						"gmi_clk_pk1",
657*724ba675SRob Herring						"gmi_cs2_n_pk3";
658*724ba675SRob Herring				nvidia,function = "gmi";
659*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
660*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
661*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
662*724ba675SRob Herring			};
663*724ba675SRob Herring			gmi_ad14_ph6 {
664*724ba675SRob Herring				nvidia,pins = "gmi_ad14_ph6",
665*724ba675SRob Herring						"gmi_cs0_n_pj0",
666*724ba675SRob Herring						"gmi_cs4_n_pk2",
667*724ba675SRob Herring						"gmi_cs7_n_pi6",
668*724ba675SRob Herring						"gmi_dqs_p_pj3",
669*724ba675SRob Herring						"gmi_wp_n_pc7";
670*724ba675SRob Herring				nvidia,function = "gmi";
671*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
672*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
673*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
674*724ba675SRob Herring			};
675*724ba675SRob Herring			gmi_ad2_pg2 {
676*724ba675SRob Herring				nvidia,pins = "gmi_ad2_pg2",
677*724ba675SRob Herring						"gmi_ad3_pg3";
678*724ba675SRob Herring				nvidia,function = "gmi";
679*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
680*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
681*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
682*724ba675SRob Herring			};
683*724ba675SRob Herring			sdmmc1_wp_n_pv3 {
684*724ba675SRob Herring				nvidia,pins = "sdmmc1_wp_n_pv3";
685*724ba675SRob Herring				nvidia,function = "spi4";
686*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
687*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
688*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689*724ba675SRob Herring			};
690*724ba675SRob Herring			clk2_req_pcc5 {
691*724ba675SRob Herring				nvidia,pins = "clk2_req_pcc5";
692*724ba675SRob Herring				nvidia,function = "rsvd4";
693*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
694*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
695*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
696*724ba675SRob Herring			};
697*724ba675SRob Herring			kb_col3_pq3 {
698*724ba675SRob Herring				nvidia,pins = "kb_col3_pq3";
699*724ba675SRob Herring				nvidia,function = "pwm2";
700*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
702*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703*724ba675SRob Herring			};
704*724ba675SRob Herring			kb_col5_pq5 {
705*724ba675SRob Herring				nvidia,pins = "kb_col5_pq5";
706*724ba675SRob Herring				nvidia,function = "kbc";
707*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
708*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
709*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710*724ba675SRob Herring			};
711*724ba675SRob Herring			kb_col6_pq6 {
712*724ba675SRob Herring				nvidia,pins = "kb_col6_pq6",
713*724ba675SRob Herring						"kb_col7_pq7";
714*724ba675SRob Herring				nvidia,function = "kbc";
715*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
716*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
717*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
718*724ba675SRob Herring			};
719*724ba675SRob Herring			kb_row3_pr3 {
720*724ba675SRob Herring				nvidia,pins = "kb_row3_pr3",
721*724ba675SRob Herring						"kb_row4_pr4",
722*724ba675SRob Herring						"kb_row6_pr6";
723*724ba675SRob Herring				nvidia,function = "kbc";
724*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
725*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
726*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
727*724ba675SRob Herring			};
728*724ba675SRob Herring			clk3_req_pee1 {
729*724ba675SRob Herring				nvidia,pins = "clk3_req_pee1";
730*724ba675SRob Herring				nvidia,function = "rsvd4";
731*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
732*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
733*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
734*724ba675SRob Herring			};
735*724ba675SRob Herring			pu2 {
736*724ba675SRob Herring				nvidia,pins = "pu2";
737*724ba675SRob Herring				nvidia,function = "rsvd1";
738*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
740*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741*724ba675SRob Herring			};
742*724ba675SRob Herring			hdmi_int_pn7 {
743*724ba675SRob Herring				nvidia,pins = "hdmi_int_pn7";
744*724ba675SRob Herring				nvidia,function = "rsvd1";
745*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
746*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
747*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
748*724ba675SRob Herring			};
749*724ba675SRob Herring
750*724ba675SRob Herring			drive_sdio1 {
751*724ba675SRob Herring				nvidia,pins = "drive_sdio1";
752*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
753*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
754*724ba675SRob Herring				nvidia,pull-down-strength = <36>;
755*724ba675SRob Herring				nvidia,pull-up-strength = <20>;
756*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
757*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
758*724ba675SRob Herring			};
759*724ba675SRob Herring			drive_sdio3 {
760*724ba675SRob Herring				nvidia,pins = "drive_sdio3";
761*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
762*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
763*724ba675SRob Herring				nvidia,pull-down-strength = <36>;
764*724ba675SRob Herring				nvidia,pull-up-strength = <20>;
765*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
766*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
767*724ba675SRob Herring			};
768*724ba675SRob Herring			drive_gma {
769*724ba675SRob Herring				nvidia,pins = "drive_gma";
770*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
771*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
772*724ba675SRob Herring				nvidia,pull-down-strength = <2>;
773*724ba675SRob Herring				nvidia,pull-up-strength = <2>;
774*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
775*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
776*724ba675SRob Herring			};
777*724ba675SRob Herring		};
778*724ba675SRob Herring	};
779*724ba675SRob Herring
780*724ba675SRob Herring	/* Usable on reworked devices only */
781*724ba675SRob Herring	serial@70006300 {
782*724ba675SRob Herring		status = "okay";
783*724ba675SRob Herring	};
784*724ba675SRob Herring
785*724ba675SRob Herring	pwm@7000a000 {
786*724ba675SRob Herring		status = "okay";
787*724ba675SRob Herring	};
788*724ba675SRob Herring
789*724ba675SRob Herring	i2c@7000d000 {
790*724ba675SRob Herring		status = "okay";
791*724ba675SRob Herring		clock-frequency = <400000>;
792*724ba675SRob Herring
793*724ba675SRob Herring		regulator@43 {
794*724ba675SRob Herring			compatible = "ti,tps51632";
795*724ba675SRob Herring			reg = <0x43>;
796*724ba675SRob Herring			regulator-name = "vdd-cpu";
797*724ba675SRob Herring			regulator-min-microvolt = <500000>;
798*724ba675SRob Herring			regulator-max-microvolt = <1520000>;
799*724ba675SRob Herring			regulator-always-on;
800*724ba675SRob Herring			regulator-boot-on;
801*724ba675SRob Herring		};
802*724ba675SRob Herring
803*724ba675SRob Herring		palmas: pmic@58 {
804*724ba675SRob Herring			compatible = "ti,tps65913", "ti,palmas";
805*724ba675SRob Herring			reg = <0x58>;
806*724ba675SRob Herring			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
807*724ba675SRob Herring
808*724ba675SRob Herring			#interrupt-cells = <2>;
809*724ba675SRob Herring			interrupt-controller;
810*724ba675SRob Herring
811*724ba675SRob Herring			ti,system-power-controller;
812*724ba675SRob Herring
813*724ba675SRob Herring			palmas_gpio: gpio {
814*724ba675SRob Herring				compatible = "ti,palmas-gpio";
815*724ba675SRob Herring				gpio-controller;
816*724ba675SRob Herring				#gpio-cells = <2>;
817*724ba675SRob Herring			};
818*724ba675SRob Herring
819*724ba675SRob Herring			pmic {
820*724ba675SRob Herring				compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
821*724ba675SRob Herring
822*724ba675SRob Herring				regulators {
823*724ba675SRob Herring					smps12 {
824*724ba675SRob Herring						regulator-name = "vdd-ddr";
825*724ba675SRob Herring						regulator-min-microvolt = <1200000>;
826*724ba675SRob Herring						regulator-max-microvolt = <1500000>;
827*724ba675SRob Herring						regulator-always-on;
828*724ba675SRob Herring						regulator-boot-on;
829*724ba675SRob Herring					};
830*724ba675SRob Herring
831*724ba675SRob Herring					vdd_1v8: smps3 {
832*724ba675SRob Herring						regulator-name = "vdd-1v8";
833*724ba675SRob Herring						regulator-min-microvolt = <1800000>;
834*724ba675SRob Herring						regulator-max-microvolt = <1800000>;
835*724ba675SRob Herring						regulator-boot-on;
836*724ba675SRob Herring					};
837*724ba675SRob Herring
838*724ba675SRob Herring					smps457 {
839*724ba675SRob Herring						regulator-name = "vdd-soc";
840*724ba675SRob Herring						regulator-min-microvolt = <900000>;
841*724ba675SRob Herring						regulator-max-microvolt = <1400000>;
842*724ba675SRob Herring						regulator-always-on;
843*724ba675SRob Herring						regulator-boot-on;
844*724ba675SRob Herring					};
845*724ba675SRob Herring
846*724ba675SRob Herring					smps8 {
847*724ba675SRob Herring						regulator-name = "avdd-pll-1v05";
848*724ba675SRob Herring						regulator-min-microvolt = <1050000>;
849*724ba675SRob Herring						regulator-max-microvolt = <1050000>;
850*724ba675SRob Herring						regulator-always-on;
851*724ba675SRob Herring						regulator-boot-on;
852*724ba675SRob Herring					};
853*724ba675SRob Herring
854*724ba675SRob Herring					smps9 {
855*724ba675SRob Herring						regulator-name = "vdd-2v85-emmc";
856*724ba675SRob Herring						regulator-min-microvolt = <2800000>;
857*724ba675SRob Herring						regulator-max-microvolt = <2800000>;
858*724ba675SRob Herring						regulator-always-on;
859*724ba675SRob Herring					};
860*724ba675SRob Herring
861*724ba675SRob Herring					smps10_out1 {
862*724ba675SRob Herring						regulator-name = "vdd-fan";
863*724ba675SRob Herring						regulator-min-microvolt = <5000000>;
864*724ba675SRob Herring						regulator-max-microvolt = <5000000>;
865*724ba675SRob Herring						regulator-always-on;
866*724ba675SRob Herring						regulator-boot-on;
867*724ba675SRob Herring					};
868*724ba675SRob Herring
869*724ba675SRob Herring					smps10_out2 {
870*724ba675SRob Herring						regulator-name = "vdd-5v0-sys";
871*724ba675SRob Herring						regulator-min-microvolt = <5000000>;
872*724ba675SRob Herring						regulator-max-microvolt = <5000000>;
873*724ba675SRob Herring						regulator-always-on;
874*724ba675SRob Herring						regulator-boot-on;
875*724ba675SRob Herring					};
876*724ba675SRob Herring
877*724ba675SRob Herring					ldo2 {
878*724ba675SRob Herring						regulator-name = "vdd-2v8-display";
879*724ba675SRob Herring						regulator-min-microvolt = <2800000>;
880*724ba675SRob Herring						regulator-max-microvolt = <2800000>;
881*724ba675SRob Herring						regulator-always-on;
882*724ba675SRob Herring						regulator-boot-on;
883*724ba675SRob Herring					};
884*724ba675SRob Herring
885*724ba675SRob Herring					vdd_1v2_ap: ldo3 {
886*724ba675SRob Herring						regulator-name = "avdd-1v2";
887*724ba675SRob Herring						regulator-min-microvolt = <1200000>;
888*724ba675SRob Herring						regulator-max-microvolt = <1200000>;
889*724ba675SRob Herring						regulator-always-on;
890*724ba675SRob Herring						regulator-boot-on;
891*724ba675SRob Herring					};
892*724ba675SRob Herring
893*724ba675SRob Herring					ldo4 {
894*724ba675SRob Herring						regulator-name = "vpp-fuse";
895*724ba675SRob Herring						regulator-min-microvolt = <1800000>;
896*724ba675SRob Herring						regulator-max-microvolt = <1800000>;
897*724ba675SRob Herring					};
898*724ba675SRob Herring
899*724ba675SRob Herring					ldo5 {
900*724ba675SRob Herring						regulator-name = "avdd-hdmi-pll";
901*724ba675SRob Herring						regulator-min-microvolt = <1200000>;
902*724ba675SRob Herring						regulator-max-microvolt = <1200000>;
903*724ba675SRob Herring					};
904*724ba675SRob Herring
905*724ba675SRob Herring					ldo6 {
906*724ba675SRob Herring						regulator-name = "vdd-sensor-2v8";
907*724ba675SRob Herring						regulator-min-microvolt = <2850000>;
908*724ba675SRob Herring						regulator-max-microvolt = <2850000>;
909*724ba675SRob Herring					};
910*724ba675SRob Herring
911*724ba675SRob Herring					ldo8 {
912*724ba675SRob Herring						regulator-name = "vdd-rtc";
913*724ba675SRob Herring						regulator-min-microvolt = <1100000>;
914*724ba675SRob Herring						regulator-max-microvolt = <1100000>;
915*724ba675SRob Herring						regulator-always-on;
916*724ba675SRob Herring						regulator-boot-on;
917*724ba675SRob Herring						ti,enable-ldo8-tracking;
918*724ba675SRob Herring					};
919*724ba675SRob Herring
920*724ba675SRob Herring					vddio_sdmmc3: ldo9 {
921*724ba675SRob Herring						regulator-name = "vddio-sdmmc3";
922*724ba675SRob Herring						regulator-min-microvolt = <1800000>;
923*724ba675SRob Herring						regulator-max-microvolt = <3300000>;
924*724ba675SRob Herring					};
925*724ba675SRob Herring
926*724ba675SRob Herring					ldousb {
927*724ba675SRob Herring						regulator-name = "avdd-usb-hdmi";
928*724ba675SRob Herring						regulator-min-microvolt = <3300000>;
929*724ba675SRob Herring						regulator-max-microvolt = <3300000>;
930*724ba675SRob Herring						regulator-always-on;
931*724ba675SRob Herring						regulator-boot-on;
932*724ba675SRob Herring					};
933*724ba675SRob Herring
934*724ba675SRob Herring					vdd_3v3_sys: regen1 {
935*724ba675SRob Herring						regulator-name = "rail-3v3";
936*724ba675SRob Herring						regulator-max-microvolt = <3300000>;
937*724ba675SRob Herring						regulator-always-on;
938*724ba675SRob Herring						regulator-boot-on;
939*724ba675SRob Herring					};
940*724ba675SRob Herring
941*724ba675SRob Herring					regen2 {
942*724ba675SRob Herring						regulator-name = "rail-5v0";
943*724ba675SRob Herring						regulator-max-microvolt = <5000000>;
944*724ba675SRob Herring						regulator-always-on;
945*724ba675SRob Herring						regulator-boot-on;
946*724ba675SRob Herring					};
947*724ba675SRob Herring
948*724ba675SRob Herring				};
949*724ba675SRob Herring			};
950*724ba675SRob Herring
951*724ba675SRob Herring			rtc {
952*724ba675SRob Herring				compatible = "ti,palmas-rtc";
953*724ba675SRob Herring				interrupt-parent = <&palmas>;
954*724ba675SRob Herring				interrupts = <8 0>;
955*724ba675SRob Herring			};
956*724ba675SRob Herring
957*724ba675SRob Herring		};
958*724ba675SRob Herring	};
959*724ba675SRob Herring
960*724ba675SRob Herring	pmc@7000e400 {
961*724ba675SRob Herring		nvidia,invert-interrupt;
962*724ba675SRob Herring	};
963*724ba675SRob Herring
964*724ba675SRob Herring	/* SD card */
965*724ba675SRob Herring	mmc@78000400 {
966*724ba675SRob Herring		status = "okay";
967*724ba675SRob Herring		bus-width = <4>;
968*724ba675SRob Herring		vqmmc-supply = <&vddio_sdmmc3>;
969*724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
970*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
971*724ba675SRob Herring	};
972*724ba675SRob Herring
973*724ba675SRob Herring	/* eMMC */
974*724ba675SRob Herring	mmc@78000600 {
975*724ba675SRob Herring		status = "okay";
976*724ba675SRob Herring		bus-width = <8>;
977*724ba675SRob Herring		non-removable;
978*724ba675SRob Herring	};
979*724ba675SRob Herring
980*724ba675SRob Herring	/* External USB port (must be powered) */
981*724ba675SRob Herring	usb@7d000000 {
982*724ba675SRob Herring		status = "okay";
983*724ba675SRob Herring	};
984*724ba675SRob Herring
985*724ba675SRob Herring	usb-phy@7d000000 {
986*724ba675SRob Herring		status = "okay";
987*724ba675SRob Herring		nvidia,xcvr-setup = <7>;
988*724ba675SRob Herring		nvidia,xcvr-lsfslew = <2>;
989*724ba675SRob Herring		nvidia,xcvr-lsrslew = <2>;
990*724ba675SRob Herring		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
991*724ba675SRob Herring		/* Should be changed to "otg" once we have vbus_supply */
992*724ba675SRob Herring		/* As of now, USB devices need to be powered externally */
993*724ba675SRob Herring		dr_mode = "host";
994*724ba675SRob Herring	};
995*724ba675SRob Herring
996*724ba675SRob Herring	/* SHIELD controller */
997*724ba675SRob Herring	usb@7d008000 {
998*724ba675SRob Herring		status = "okay";
999*724ba675SRob Herring	};
1000*724ba675SRob Herring
1001*724ba675SRob Herring	usb-phy@7d008000 {
1002*724ba675SRob Herring		status = "okay";
1003*724ba675SRob Herring		nvidia,xcvr-setup = <7>;
1004*724ba675SRob Herring		nvidia,xcvr-lsfslew = <2>;
1005*724ba675SRob Herring		nvidia,xcvr-lsrslew = <2>;
1006*724ba675SRob Herring	};
1007*724ba675SRob Herring
1008*724ba675SRob Herring	backlight: backlight {
1009*724ba675SRob Herring		compatible = "pwm-backlight";
1010*724ba675SRob Herring		pwms = <&pwm 1 40000>;
1011*724ba675SRob Herring
1012*724ba675SRob Herring		brightness-levels = <0 4 8 16 32 64 128 255>;
1013*724ba675SRob Herring		default-brightness-level = <6>;
1014*724ba675SRob Herring
1015*724ba675SRob Herring		power-supply = <&lcd_bl_en>;
1016*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1017*724ba675SRob Herring	};
1018*724ba675SRob Herring
1019*724ba675SRob Herring	clk32k_in: clock-32k {
1020*724ba675SRob Herring		compatible = "fixed-clock";
1021*724ba675SRob Herring		clock-frequency = <32768>;
1022*724ba675SRob Herring		#clock-cells = <0>;
1023*724ba675SRob Herring	};
1024*724ba675SRob Herring
1025*724ba675SRob Herring	gpio-keys {
1026*724ba675SRob Herring		compatible = "gpio-keys";
1027*724ba675SRob Herring
1028*724ba675SRob Herring		key-back {
1029*724ba675SRob Herring			label = "Back";
1030*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1031*724ba675SRob Herring			linux,code = <KEY_BACK>;
1032*724ba675SRob Herring		};
1033*724ba675SRob Herring
1034*724ba675SRob Herring		key-home {
1035*724ba675SRob Herring			label = "Home";
1036*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1037*724ba675SRob Herring			linux,code = <KEY_HOME>;
1038*724ba675SRob Herring		};
1039*724ba675SRob Herring
1040*724ba675SRob Herring		key-power {
1041*724ba675SRob Herring			label = "Power";
1042*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1043*724ba675SRob Herring			linux,code = <KEY_POWER>;
1044*724ba675SRob Herring			wakeup-source;
1045*724ba675SRob Herring		};
1046*724ba675SRob Herring	};
1047*724ba675SRob Herring
1048*724ba675SRob Herring	lcd_bl_en: regulator-lcden {
1049*724ba675SRob Herring		compatible = "regulator-fixed";
1050*724ba675SRob Herring		regulator-name = "lcd_bl_en";
1051*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1052*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1053*724ba675SRob Herring		regulator-boot-on;
1054*724ba675SRob Herring	};
1055*724ba675SRob Herring
1056*724ba675SRob Herring	vdd_lcd: regulator-lcd {
1057*724ba675SRob Herring		compatible = "regulator-fixed";
1058*724ba675SRob Herring		regulator-name = "vdd_lcd_1v8";
1059*724ba675SRob Herring		regulator-min-microvolt = <1800000>;
1060*724ba675SRob Herring		regulator-max-microvolt = <1800000>;
1061*724ba675SRob Herring		vin-supply = <&vdd_1v8>;
1062*724ba675SRob Herring		enable-active-high;
1063*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
1064*724ba675SRob Herring		regulator-boot-on;
1065*724ba675SRob Herring	};
1066*724ba675SRob Herring
1067*724ba675SRob Herring	regulator-1v8ts {
1068*724ba675SRob Herring		compatible = "regulator-fixed";
1069*724ba675SRob Herring		regulator-name = "vdd_1v8_ts";
1070*724ba675SRob Herring		regulator-min-microvolt = <1800000>;
1071*724ba675SRob Herring		regulator-max-microvolt = <1800000>;
1072*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
1073*724ba675SRob Herring		regulator-boot-on;
1074*724ba675SRob Herring	};
1075*724ba675SRob Herring
1076*724ba675SRob Herring	regulator-3v3ts {
1077*724ba675SRob Herring		compatible = "regulator-fixed";
1078*724ba675SRob Herring		regulator-name = "vdd_3v3_ts";
1079*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1080*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1081*724ba675SRob Herring		enable-active-high;
1082*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1083*724ba675SRob Herring		regulator-boot-on;
1084*724ba675SRob Herring	};
1085*724ba675SRob Herring
1086*724ba675SRob Herring	regulator-1v8com {
1087*724ba675SRob Herring		compatible = "regulator-fixed";
1088*724ba675SRob Herring		regulator-name = "vdd_1v8_com";
1089*724ba675SRob Herring		regulator-min-microvolt = <1800000>;
1090*724ba675SRob Herring		regulator-max-microvolt = <1800000>;
1091*724ba675SRob Herring		vin-supply = <&vdd_1v8>;
1092*724ba675SRob Herring		enable-active-high;
1093*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
1094*724ba675SRob Herring		regulator-boot-on;
1095*724ba675SRob Herring	};
1096*724ba675SRob Herring
1097*724ba675SRob Herring	regulator-3v3com {
1098*724ba675SRob Herring		compatible = "regulator-fixed";
1099*724ba675SRob Herring		regulator-name = "vdd_3v3_com";
1100*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1101*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1102*724ba675SRob Herring		vin-supply = <&vdd_3v3_sys>;
1103*724ba675SRob Herring		enable-active-high;
1104*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1105*724ba675SRob Herring		regulator-always-on;
1106*724ba675SRob Herring		regulator-boot-on;
1107*724ba675SRob Herring	};
1108*724ba675SRob Herring};
1109