1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * This dts file supports Dalmore A04. 4*724ba675SRob Herring * Other board revisions are not supported 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring 9*724ba675SRob Herring#include <dt-bindings/input/input.h> 10*724ba675SRob Herring#include "tegra114.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring model = "NVIDIA Tegra114 Dalmore evaluation board"; 14*724ba675SRob Herring compatible = "nvidia,dalmore", "nvidia,tegra114"; 15*724ba675SRob Herring 16*724ba675SRob Herring aliases { 17*724ba675SRob Herring rtc0 = "/i2c@7000d000/tps65913@58"; 18*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 19*724ba675SRob Herring serial0 = &uartd; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring chosen { 23*724ba675SRob Herring stdout-path = "serial0:115200n8"; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring memory@80000000 { 27*724ba675SRob Herring reg = <0x80000000 0x40000000>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring host1x@50000000 { 31*724ba675SRob Herring hdmi@54280000 { 32*724ba675SRob Herring status = "okay"; 33*724ba675SRob Herring 34*724ba675SRob Herring hdmi-supply = <&vdd_5v0_hdmi>; 35*724ba675SRob Herring vdd-supply = <&vdd_hdmi_reg>; 36*724ba675SRob Herring pll-supply = <&palmas_smps3_reg>; 37*724ba675SRob Herring 38*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 39*724ba675SRob Herring nvidia,hpd-gpio = 40*724ba675SRob Herring <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring dsi@54300000 { 44*724ba675SRob Herring status = "okay"; 45*724ba675SRob Herring 46*724ba675SRob Herring avdd-dsi-csi-supply = <&avdd_1v2_reg>; 47*724ba675SRob Herring 48*724ba675SRob Herring panel@0 { 49*724ba675SRob Herring compatible = "panasonic,vvx10f004b00"; 50*724ba675SRob Herring reg = <0>; 51*724ba675SRob Herring 52*724ba675SRob Herring power-supply = <&avdd_lcd_reg>; 53*724ba675SRob Herring backlight = <&backlight>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring }; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring pinmux@70000868 { 59*724ba675SRob Herring pinctrl-names = "default"; 60*724ba675SRob Herring pinctrl-0 = <&state_default>; 61*724ba675SRob Herring 62*724ba675SRob Herring state_default: pinmux { 63*724ba675SRob Herring clk1_out_pw4 { 64*724ba675SRob Herring nvidia,pins = "clk1_out_pw4"; 65*724ba675SRob Herring nvidia,function = "extperiph1"; 66*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 67*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 68*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring dap1_din_pn1 { 71*724ba675SRob Herring nvidia,pins = "dap1_din_pn1"; 72*724ba675SRob Herring nvidia,function = "i2s0"; 73*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 74*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 75*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring dap1_dout_pn2 { 78*724ba675SRob Herring nvidia,pins = "dap1_dout_pn2", 79*724ba675SRob Herring "dap1_fs_pn0", 80*724ba675SRob Herring "dap1_sclk_pn3"; 81*724ba675SRob Herring nvidia,function = "i2s0"; 82*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 83*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 84*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring dap2_din_pa4 { 87*724ba675SRob Herring nvidia,pins = "dap2_din_pa4"; 88*724ba675SRob Herring nvidia,function = "i2s1"; 89*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 90*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 91*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring dap2_dout_pa5 { 94*724ba675SRob Herring nvidia,pins = "dap2_dout_pa5", 95*724ba675SRob Herring "dap2_fs_pa2", 96*724ba675SRob Herring "dap2_sclk_pa3"; 97*724ba675SRob Herring nvidia,function = "i2s1"; 98*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 99*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 100*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring dap4_din_pp5 { 103*724ba675SRob Herring nvidia,pins = "dap4_din_pp5", 104*724ba675SRob Herring "dap4_dout_pp6", 105*724ba675SRob Herring "dap4_fs_pp4", 106*724ba675SRob Herring "dap4_sclk_pp7"; 107*724ba675SRob Herring nvidia,function = "i2s3"; 108*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 109*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 110*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring dvfs_pwm_px0 { 113*724ba675SRob Herring nvidia,pins = "dvfs_pwm_px0", 114*724ba675SRob Herring "dvfs_clk_px2"; 115*724ba675SRob Herring nvidia,function = "cldvfs"; 116*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 117*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 118*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring ulpi_clk_py0 { 121*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0", 122*724ba675SRob Herring "ulpi_data0_po1", 123*724ba675SRob Herring "ulpi_data1_po2", 124*724ba675SRob Herring "ulpi_data2_po3", 125*724ba675SRob Herring "ulpi_data3_po4", 126*724ba675SRob Herring "ulpi_data4_po5", 127*724ba675SRob Herring "ulpi_data5_po6", 128*724ba675SRob Herring "ulpi_data6_po7", 129*724ba675SRob Herring "ulpi_data7_po0"; 130*724ba675SRob Herring nvidia,function = "ulpi"; 131*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 132*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 133*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring ulpi_dir_py1 { 136*724ba675SRob Herring nvidia,pins = "ulpi_dir_py1", 137*724ba675SRob Herring "ulpi_nxt_py2"; 138*724ba675SRob Herring nvidia,function = "ulpi"; 139*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 141*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 142*724ba675SRob Herring }; 143*724ba675SRob Herring ulpi_stp_py3 { 144*724ba675SRob Herring nvidia,pins = "ulpi_stp_py3"; 145*724ba675SRob Herring nvidia,function = "ulpi"; 146*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 147*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 148*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 149*724ba675SRob Herring }; 150*724ba675SRob Herring cam_i2c_scl_pbb1 { 151*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1", 152*724ba675SRob Herring "cam_i2c_sda_pbb2"; 153*724ba675SRob Herring nvidia,function = "i2c3"; 154*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 155*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 156*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 157*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 158*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring cam_mclk_pcc0 { 161*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0", 162*724ba675SRob Herring "pbb0"; 163*724ba675SRob Herring nvidia,function = "vi_alt3"; 164*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 166*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 167*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 168*724ba675SRob Herring }; 169*724ba675SRob Herring gen2_i2c_scl_pt5 { 170*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5", 171*724ba675SRob Herring "gen2_i2c_sda_pt6"; 172*724ba675SRob Herring nvidia,function = "i2c2"; 173*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 174*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 175*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 176*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 177*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring gmi_a16_pj7 { 180*724ba675SRob Herring nvidia,pins = "gmi_a16_pj7"; 181*724ba675SRob Herring nvidia,function = "uartd"; 182*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 183*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 184*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 185*724ba675SRob Herring }; 186*724ba675SRob Herring gmi_a17_pb0 { 187*724ba675SRob Herring nvidia,pins = "gmi_a17_pb0", 188*724ba675SRob Herring "gmi_a18_pb1"; 189*724ba675SRob Herring nvidia,function = "uartd"; 190*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 191*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 192*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 193*724ba675SRob Herring }; 194*724ba675SRob Herring gmi_a19_pk7 { 195*724ba675SRob Herring nvidia,pins = "gmi_a19_pk7"; 196*724ba675SRob Herring nvidia,function = "uartd"; 197*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 199*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 200*724ba675SRob Herring }; 201*724ba675SRob Herring gmi_ad5_pg5 { 202*724ba675SRob Herring nvidia,pins = "gmi_ad5_pg5", 203*724ba675SRob Herring "gmi_cs6_n_pi3", 204*724ba675SRob Herring "gmi_wr_n_pi0"; 205*724ba675SRob Herring nvidia,function = "spi4"; 206*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 207*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 208*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 209*724ba675SRob Herring }; 210*724ba675SRob Herring gmi_ad6_pg6 { 211*724ba675SRob Herring nvidia,pins = "gmi_ad6_pg6", 212*724ba675SRob Herring "gmi_ad7_pg7"; 213*724ba675SRob Herring nvidia,function = "spi4"; 214*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 215*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 216*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 217*724ba675SRob Herring }; 218*724ba675SRob Herring gmi_ad12_ph4 { 219*724ba675SRob Herring nvidia,pins = "gmi_ad12_ph4"; 220*724ba675SRob Herring nvidia,function = "rsvd4"; 221*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 222*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 223*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 224*724ba675SRob Herring }; 225*724ba675SRob Herring gmi_ad9_ph1 { 226*724ba675SRob Herring nvidia,pins = "gmi_ad9_ph1"; 227*724ba675SRob Herring nvidia,function = "pwm1"; 228*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 229*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 230*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 231*724ba675SRob Herring }; 232*724ba675SRob Herring gmi_cs1_n_pj2 { 233*724ba675SRob Herring nvidia,pins = "gmi_cs1_n_pj2", 234*724ba675SRob Herring "gmi_oe_n_pi1"; 235*724ba675SRob Herring nvidia,function = "soc"; 236*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 238*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239*724ba675SRob Herring }; 240*724ba675SRob Herring clk2_out_pw5 { 241*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 242*724ba675SRob Herring nvidia,function = "extperiph2"; 243*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 244*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 245*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 246*724ba675SRob Herring }; 247*724ba675SRob Herring sdmmc1_clk_pz0 { 248*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 249*724ba675SRob Herring nvidia,function = "sdmmc1"; 250*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 252*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 253*724ba675SRob Herring }; 254*724ba675SRob Herring sdmmc1_cmd_pz1 { 255*724ba675SRob Herring nvidia,pins = "sdmmc1_cmd_pz1", 256*724ba675SRob Herring "sdmmc1_dat0_py7", 257*724ba675SRob Herring "sdmmc1_dat1_py6", 258*724ba675SRob Herring "sdmmc1_dat2_py5", 259*724ba675SRob Herring "sdmmc1_dat3_py4"; 260*724ba675SRob Herring nvidia,function = "sdmmc1"; 261*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 262*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 263*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 264*724ba675SRob Herring }; 265*724ba675SRob Herring sdmmc1_wp_n_pv3 { 266*724ba675SRob Herring nvidia,pins = "sdmmc1_wp_n_pv3"; 267*724ba675SRob Herring nvidia,function = "spi4"; 268*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 269*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring sdmmc3_clk_pa6 { 273*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 274*724ba675SRob Herring nvidia,function = "sdmmc3"; 275*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 276*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 277*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 278*724ba675SRob Herring }; 279*724ba675SRob Herring sdmmc3_cmd_pa7 { 280*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7", 281*724ba675SRob Herring "sdmmc3_dat0_pb7", 282*724ba675SRob Herring "sdmmc3_dat1_pb6", 283*724ba675SRob Herring "sdmmc3_dat2_pb5", 284*724ba675SRob Herring "sdmmc3_dat3_pb4", 285*724ba675SRob Herring "kb_col4_pq4", 286*724ba675SRob Herring "sdmmc3_clk_lb_out_pee4", 287*724ba675SRob Herring "sdmmc3_clk_lb_in_pee5"; 288*724ba675SRob Herring nvidia,function = "sdmmc3"; 289*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 290*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 291*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring sdmmc4_clk_pcc4 { 294*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 295*724ba675SRob Herring nvidia,function = "sdmmc4"; 296*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 297*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 298*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 299*724ba675SRob Herring }; 300*724ba675SRob Herring sdmmc4_cmd_pt7 { 301*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7", 302*724ba675SRob Herring "sdmmc4_dat0_paa0", 303*724ba675SRob Herring "sdmmc4_dat1_paa1", 304*724ba675SRob Herring "sdmmc4_dat2_paa2", 305*724ba675SRob Herring "sdmmc4_dat3_paa3", 306*724ba675SRob Herring "sdmmc4_dat4_paa4", 307*724ba675SRob Herring "sdmmc4_dat5_paa5", 308*724ba675SRob Herring "sdmmc4_dat6_paa6", 309*724ba675SRob Herring "sdmmc4_dat7_paa7"; 310*724ba675SRob Herring nvidia,function = "sdmmc4"; 311*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 312*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 313*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 314*724ba675SRob Herring }; 315*724ba675SRob Herring clk_32k_out_pa0 { 316*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 317*724ba675SRob Herring nvidia,function = "blink"; 318*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 319*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 320*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 321*724ba675SRob Herring }; 322*724ba675SRob Herring kb_col0_pq0 { 323*724ba675SRob Herring nvidia,pins = "kb_col0_pq0", 324*724ba675SRob Herring "kb_col1_pq1", 325*724ba675SRob Herring "kb_col2_pq2", 326*724ba675SRob Herring "kb_row0_pr0", 327*724ba675SRob Herring "kb_row1_pr1", 328*724ba675SRob Herring "kb_row2_pr2"; 329*724ba675SRob Herring nvidia,function = "kbc"; 330*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 331*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 332*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 333*724ba675SRob Herring }; 334*724ba675SRob Herring dap3_din_pp1 { 335*724ba675SRob Herring nvidia,pins = "dap3_din_pp1", 336*724ba675SRob Herring "dap3_sclk_pp3"; 337*724ba675SRob Herring nvidia,function = "displayb"; 338*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 339*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 340*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring pv0 { 343*724ba675SRob Herring nvidia,pins = "pv0"; 344*724ba675SRob Herring nvidia,function = "rsvd4"; 345*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 346*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 347*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 348*724ba675SRob Herring }; 349*724ba675SRob Herring kb_row7_pr7 { 350*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 351*724ba675SRob Herring nvidia,function = "rsvd2"; 352*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 353*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 354*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 355*724ba675SRob Herring }; 356*724ba675SRob Herring kb_row10_ps2 { 357*724ba675SRob Herring nvidia,pins = "kb_row10_ps2"; 358*724ba675SRob Herring nvidia,function = "uarta"; 359*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 360*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 361*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 362*724ba675SRob Herring }; 363*724ba675SRob Herring kb_row9_ps1 { 364*724ba675SRob Herring nvidia,pins = "kb_row9_ps1"; 365*724ba675SRob Herring nvidia,function = "uarta"; 366*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 367*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 368*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 369*724ba675SRob Herring }; 370*724ba675SRob Herring pwr_i2c_scl_pz6 { 371*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6", 372*724ba675SRob Herring "pwr_i2c_sda_pz7"; 373*724ba675SRob Herring nvidia,function = "i2cpwr"; 374*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 375*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 376*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 377*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 378*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 379*724ba675SRob Herring }; 380*724ba675SRob Herring sys_clk_req_pz5 { 381*724ba675SRob Herring nvidia,pins = "sys_clk_req_pz5"; 382*724ba675SRob Herring nvidia,function = "sysclk"; 383*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 385*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 386*724ba675SRob Herring }; 387*724ba675SRob Herring core_pwr_req { 388*724ba675SRob Herring nvidia,pins = "core_pwr_req"; 389*724ba675SRob Herring nvidia,function = "pwron"; 390*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 391*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 392*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 393*724ba675SRob Herring }; 394*724ba675SRob Herring cpu_pwr_req { 395*724ba675SRob Herring nvidia,pins = "cpu_pwr_req"; 396*724ba675SRob Herring nvidia,function = "cpu"; 397*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 398*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 399*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 400*724ba675SRob Herring }; 401*724ba675SRob Herring pwr_int_n { 402*724ba675SRob Herring nvidia,pins = "pwr_int_n"; 403*724ba675SRob Herring nvidia,function = "pmi"; 404*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 405*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 406*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 407*724ba675SRob Herring }; 408*724ba675SRob Herring reset_out_n { 409*724ba675SRob Herring nvidia,pins = "reset_out_n"; 410*724ba675SRob Herring nvidia,function = "reset_out_n"; 411*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 412*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 413*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 414*724ba675SRob Herring }; 415*724ba675SRob Herring clk3_out_pee0 { 416*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 417*724ba675SRob Herring nvidia,function = "extperiph3"; 418*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 419*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 420*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 421*724ba675SRob Herring }; 422*724ba675SRob Herring gen1_i2c_scl_pc4 { 423*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4", 424*724ba675SRob Herring "gen1_i2c_sda_pc5"; 425*724ba675SRob Herring nvidia,function = "i2c1"; 426*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 428*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 429*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 430*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 431*724ba675SRob Herring }; 432*724ba675SRob Herring uart2_cts_n_pj5 { 433*724ba675SRob Herring nvidia,pins = "uart2_cts_n_pj5"; 434*724ba675SRob Herring nvidia,function = "uartb"; 435*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 436*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 437*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 438*724ba675SRob Herring }; 439*724ba675SRob Herring uart2_rts_n_pj6 { 440*724ba675SRob Herring nvidia,pins = "uart2_rts_n_pj6"; 441*724ba675SRob Herring nvidia,function = "uartb"; 442*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 443*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 444*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 445*724ba675SRob Herring }; 446*724ba675SRob Herring uart2_rxd_pc3 { 447*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3"; 448*724ba675SRob Herring nvidia,function = "irda"; 449*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 450*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 451*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 452*724ba675SRob Herring }; 453*724ba675SRob Herring uart2_txd_pc2 { 454*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2"; 455*724ba675SRob Herring nvidia,function = "irda"; 456*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 457*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 458*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 459*724ba675SRob Herring }; 460*724ba675SRob Herring uart3_cts_n_pa1 { 461*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1", 462*724ba675SRob Herring "uart3_rxd_pw7"; 463*724ba675SRob Herring nvidia,function = "uartc"; 464*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 465*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 466*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 467*724ba675SRob Herring }; 468*724ba675SRob Herring uart3_rts_n_pc0 { 469*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0", 470*724ba675SRob Herring "uart3_txd_pw6"; 471*724ba675SRob Herring nvidia,function = "uartc"; 472*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 473*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 474*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 475*724ba675SRob Herring }; 476*724ba675SRob Herring owr { 477*724ba675SRob Herring nvidia,pins = "owr"; 478*724ba675SRob Herring nvidia,function = "owr"; 479*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 480*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 481*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring hdmi_cec_pee3 { 484*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 485*724ba675SRob Herring nvidia,function = "cec"; 486*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 487*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 488*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 490*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_DISABLE>; 491*724ba675SRob Herring }; 492*724ba675SRob Herring ddc_scl_pv4 { 493*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4", 494*724ba675SRob Herring "ddc_sda_pv5"; 495*724ba675SRob Herring nvidia,function = "i2c4"; 496*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 497*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 498*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 499*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 500*724ba675SRob Herring nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 501*724ba675SRob Herring }; 502*724ba675SRob Herring spdif_in_pk6 { 503*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 504*724ba675SRob Herring nvidia,function = "usb"; 505*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 506*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 507*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 508*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 509*724ba675SRob Herring }; 510*724ba675SRob Herring usb_vbus_en0_pn4 { 511*724ba675SRob Herring nvidia,pins = "usb_vbus_en0_pn4"; 512*724ba675SRob Herring nvidia,function = "usb"; 513*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 514*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 515*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 516*724ba675SRob Herring nvidia,lock = <TEGRA_PIN_DISABLE>; 517*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 518*724ba675SRob Herring }; 519*724ba675SRob Herring gpio_x6_aud_px6 { 520*724ba675SRob Herring nvidia,pins = "gpio_x6_aud_px6"; 521*724ba675SRob Herring nvidia,function = "spi6"; 522*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 523*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 524*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 525*724ba675SRob Herring }; 526*724ba675SRob Herring gpio_x4_aud_px4 { 527*724ba675SRob Herring nvidia,pins = "gpio_x4_aud_px4", 528*724ba675SRob Herring "gpio_x7_aud_px7"; 529*724ba675SRob Herring nvidia,function = "rsvd1"; 530*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 531*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 532*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 533*724ba675SRob Herring }; 534*724ba675SRob Herring gpio_x5_aud_px5 { 535*724ba675SRob Herring nvidia,pins = "gpio_x5_aud_px5"; 536*724ba675SRob Herring nvidia,function = "rsvd1"; 537*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 538*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 539*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 540*724ba675SRob Herring }; 541*724ba675SRob Herring gpio_w2_aud_pw2 { 542*724ba675SRob Herring nvidia,pins = "gpio_w2_aud_pw2"; 543*724ba675SRob Herring nvidia,function = "rsvd2"; 544*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 545*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 546*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 547*724ba675SRob Herring }; 548*724ba675SRob Herring gpio_w3_aud_pw3 { 549*724ba675SRob Herring nvidia,pins = "gpio_w3_aud_pw3"; 550*724ba675SRob Herring nvidia,function = "spi6"; 551*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 552*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 553*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 554*724ba675SRob Herring }; 555*724ba675SRob Herring gpio_x1_aud_px1 { 556*724ba675SRob Herring nvidia,pins = "gpio_x1_aud_px1"; 557*724ba675SRob Herring nvidia,function = "rsvd4"; 558*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 559*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 560*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 561*724ba675SRob Herring }; 562*724ba675SRob Herring gpio_x3_aud_px3 { 563*724ba675SRob Herring nvidia,pins = "gpio_x3_aud_px3"; 564*724ba675SRob Herring nvidia,function = "rsvd4"; 565*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 566*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 567*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 568*724ba675SRob Herring }; 569*724ba675SRob Herring dap3_fs_pp0 { 570*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0"; 571*724ba675SRob Herring nvidia,function = "i2s2"; 572*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 573*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 574*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 575*724ba675SRob Herring }; 576*724ba675SRob Herring dap3_dout_pp2 { 577*724ba675SRob Herring nvidia,pins = "dap3_dout_pp2"; 578*724ba675SRob Herring nvidia,function = "i2s2"; 579*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 580*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 581*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 582*724ba675SRob Herring }; 583*724ba675SRob Herring pv1 { 584*724ba675SRob Herring nvidia,pins = "pv1"; 585*724ba675SRob Herring nvidia,function = "rsvd1"; 586*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 587*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 588*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 589*724ba675SRob Herring }; 590*724ba675SRob Herring pbb3 { 591*724ba675SRob Herring nvidia,pins = "pbb3", 592*724ba675SRob Herring "pbb5", 593*724ba675SRob Herring "pbb6", 594*724ba675SRob Herring "pbb7"; 595*724ba675SRob Herring nvidia,function = "rsvd4"; 596*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 597*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 598*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 599*724ba675SRob Herring }; 600*724ba675SRob Herring pcc1 { 601*724ba675SRob Herring nvidia,pins = "pcc1", 602*724ba675SRob Herring "pcc2"; 603*724ba675SRob Herring nvidia,function = "rsvd4"; 604*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 605*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 606*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 607*724ba675SRob Herring }; 608*724ba675SRob Herring gmi_ad0_pg0 { 609*724ba675SRob Herring nvidia,pins = "gmi_ad0_pg0", 610*724ba675SRob Herring "gmi_ad1_pg1"; 611*724ba675SRob Herring nvidia,function = "gmi"; 612*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 614*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 615*724ba675SRob Herring }; 616*724ba675SRob Herring gmi_ad10_ph2 { 617*724ba675SRob Herring nvidia,pins = "gmi_ad10_ph2", 618*724ba675SRob Herring "gmi_ad11_ph3", 619*724ba675SRob Herring "gmi_ad13_ph5", 620*724ba675SRob Herring "gmi_ad8_ph0", 621*724ba675SRob Herring "gmi_clk_pk1"; 622*724ba675SRob Herring nvidia,function = "gmi"; 623*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 624*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 625*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 626*724ba675SRob Herring }; 627*724ba675SRob Herring gmi_ad2_pg2 { 628*724ba675SRob Herring nvidia,pins = "gmi_ad2_pg2", 629*724ba675SRob Herring "gmi_ad3_pg3"; 630*724ba675SRob Herring nvidia,function = "gmi"; 631*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 632*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 633*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 634*724ba675SRob Herring }; 635*724ba675SRob Herring gmi_adv_n_pk0 { 636*724ba675SRob Herring nvidia,pins = "gmi_adv_n_pk0", 637*724ba675SRob Herring "gmi_cs0_n_pj0", 638*724ba675SRob Herring "gmi_cs2_n_pk3", 639*724ba675SRob Herring "gmi_cs4_n_pk2", 640*724ba675SRob Herring "gmi_cs7_n_pi6", 641*724ba675SRob Herring "gmi_dqs_p_pj3", 642*724ba675SRob Herring "gmi_iordy_pi5", 643*724ba675SRob Herring "gmi_wp_n_pc7"; 644*724ba675SRob Herring nvidia,function = "gmi"; 645*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 646*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 647*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648*724ba675SRob Herring }; 649*724ba675SRob Herring gmi_cs3_n_pk4 { 650*724ba675SRob Herring nvidia,pins = "gmi_cs3_n_pk4"; 651*724ba675SRob Herring nvidia,function = "gmi"; 652*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 653*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 654*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 655*724ba675SRob Herring }; 656*724ba675SRob Herring clk2_req_pcc5 { 657*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 658*724ba675SRob Herring nvidia,function = "rsvd4"; 659*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 661*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 662*724ba675SRob Herring }; 663*724ba675SRob Herring kb_col3_pq3 { 664*724ba675SRob Herring nvidia,pins = "kb_col3_pq3", 665*724ba675SRob Herring "kb_col6_pq6", 666*724ba675SRob Herring "kb_col7_pq7"; 667*724ba675SRob Herring nvidia,function = "kbc"; 668*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 669*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 670*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 671*724ba675SRob Herring }; 672*724ba675SRob Herring kb_col5_pq5 { 673*724ba675SRob Herring nvidia,pins = "kb_col5_pq5"; 674*724ba675SRob Herring nvidia,function = "kbc"; 675*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 676*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 677*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 678*724ba675SRob Herring }; 679*724ba675SRob Herring kb_row3_pr3 { 680*724ba675SRob Herring nvidia,pins = "kb_row3_pr3", 681*724ba675SRob Herring "kb_row4_pr4", 682*724ba675SRob Herring "kb_row6_pr6", 683*724ba675SRob Herring "kb_row8_ps0"; 684*724ba675SRob Herring nvidia,function = "kbc"; 685*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 686*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 687*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 688*724ba675SRob Herring }; 689*724ba675SRob Herring clk3_req_pee1 { 690*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 691*724ba675SRob Herring nvidia,function = "rsvd4"; 692*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 693*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 694*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 695*724ba675SRob Herring }; 696*724ba675SRob Herring pu4 { 697*724ba675SRob Herring nvidia,pins = "pu4"; 698*724ba675SRob Herring nvidia,function = "displayb"; 699*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 700*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 701*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 702*724ba675SRob Herring }; 703*724ba675SRob Herring pu5 { 704*724ba675SRob Herring nvidia,pins = "pu5", 705*724ba675SRob Herring "pu6"; 706*724ba675SRob Herring nvidia,function = "displayb"; 707*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 708*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 709*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 710*724ba675SRob Herring }; 711*724ba675SRob Herring hdmi_int_pn7 { 712*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 713*724ba675SRob Herring nvidia,function = "rsvd1"; 714*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 715*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 716*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 717*724ba675SRob Herring }; 718*724ba675SRob Herring clk1_req_pee2 { 719*724ba675SRob Herring nvidia,pins = "clk1_req_pee2", 720*724ba675SRob Herring "usb_vbus_en1_pn5"; 721*724ba675SRob Herring nvidia,function = "rsvd4"; 722*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 723*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 724*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 725*724ba675SRob Herring }; 726*724ba675SRob Herring 727*724ba675SRob Herring drive_sdio1 { 728*724ba675SRob Herring nvidia,pins = "drive_sdio1"; 729*724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 730*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 731*724ba675SRob Herring nvidia,pull-down-strength = <36>; 732*724ba675SRob Herring nvidia,pull-up-strength = <20>; 733*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 734*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 735*724ba675SRob Herring }; 736*724ba675SRob Herring drive_sdio3 { 737*724ba675SRob Herring nvidia,pins = "drive_sdio3"; 738*724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 739*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 740*724ba675SRob Herring nvidia,pull-down-strength = <22>; 741*724ba675SRob Herring nvidia,pull-up-strength = <36>; 742*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 743*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 744*724ba675SRob Herring }; 745*724ba675SRob Herring drive_gma { 746*724ba675SRob Herring nvidia,pins = "drive_gma"; 747*724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 748*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 749*724ba675SRob Herring nvidia,pull-down-strength = <2>; 750*724ba675SRob Herring nvidia,pull-up-strength = <1>; 751*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 752*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 753*724ba675SRob Herring }; 754*724ba675SRob Herring }; 755*724ba675SRob Herring }; 756*724ba675SRob Herring 757*724ba675SRob Herring serial@70006300 { 758*724ba675SRob Herring status = "okay"; 759*724ba675SRob Herring }; 760*724ba675SRob Herring 761*724ba675SRob Herring pwm@7000a000 { 762*724ba675SRob Herring status = "okay"; 763*724ba675SRob Herring }; 764*724ba675SRob Herring 765*724ba675SRob Herring i2c@7000c000 { 766*724ba675SRob Herring status = "okay"; 767*724ba675SRob Herring clock-frequency = <100000>; 768*724ba675SRob Herring 769*724ba675SRob Herring battery: smart-battery@b { 770*724ba675SRob Herring compatible = "ti,bq20z45", "sbs,sbs-battery"; 771*724ba675SRob Herring reg = <0xb>; 772*724ba675SRob Herring sbs,i2c-retry-count = <2>; 773*724ba675SRob Herring sbs,poll-retry-count = <100>; 774*724ba675SRob Herring power-supplies = <&charger>; 775*724ba675SRob Herring }; 776*724ba675SRob Herring 777*724ba675SRob Herring rt5640: rt5640@1c { 778*724ba675SRob Herring compatible = "realtek,rt5640"; 779*724ba675SRob Herring reg = <0x1c>; 780*724ba675SRob Herring interrupt-parent = <&gpio>; 781*724ba675SRob Herring interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>; 782*724ba675SRob Herring realtek,ldo1-en-gpios = 783*724ba675SRob Herring <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring temperature-sensor@4c { 787*724ba675SRob Herring compatible = "onnn,nct1008"; 788*724ba675SRob Herring reg = <0x4c>; 789*724ba675SRob Herring vcc-supply = <&palmas_ldo6_reg>; 790*724ba675SRob Herring interrupt-parent = <&gpio>; 791*724ba675SRob Herring interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_EDGE_FALLING>; 792*724ba675SRob Herring }; 793*724ba675SRob Herring }; 794*724ba675SRob Herring 795*724ba675SRob Herring hdmi_ddc: i2c@7000c700 { 796*724ba675SRob Herring status = "okay"; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring i2c@7000d000 { 800*724ba675SRob Herring status = "okay"; 801*724ba675SRob Herring clock-frequency = <400000>; 802*724ba675SRob Herring 803*724ba675SRob Herring tps51632@43 { 804*724ba675SRob Herring compatible = "ti,tps51632"; 805*724ba675SRob Herring reg = <0x43>; 806*724ba675SRob Herring regulator-name = "vdd-cpu"; 807*724ba675SRob Herring regulator-min-microvolt = <500000>; 808*724ba675SRob Herring regulator-max-microvolt = <1520000>; 809*724ba675SRob Herring regulator-boot-on; 810*724ba675SRob Herring regulator-always-on; 811*724ba675SRob Herring }; 812*724ba675SRob Herring 813*724ba675SRob Herring tps65090@48 { 814*724ba675SRob Herring compatible = "ti,tps65090"; 815*724ba675SRob Herring reg = <0x48>; 816*724ba675SRob Herring interrupt-parent = <&gpio>; 817*724ba675SRob Herring interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; 818*724ba675SRob Herring 819*724ba675SRob Herring vsys1-supply = <&vdd_ac_bat_reg>; 820*724ba675SRob Herring vsys2-supply = <&vdd_ac_bat_reg>; 821*724ba675SRob Herring vsys3-supply = <&vdd_ac_bat_reg>; 822*724ba675SRob Herring infet1-supply = <&vdd_ac_bat_reg>; 823*724ba675SRob Herring infet2-supply = <&vdd_ac_bat_reg>; 824*724ba675SRob Herring infet3-supply = <&tps65090_dcdc2_reg>; 825*724ba675SRob Herring infet4-supply = <&tps65090_dcdc2_reg>; 826*724ba675SRob Herring infet5-supply = <&tps65090_dcdc2_reg>; 827*724ba675SRob Herring infet6-supply = <&tps65090_dcdc2_reg>; 828*724ba675SRob Herring infet7-supply = <&tps65090_dcdc2_reg>; 829*724ba675SRob Herring vsys-l1-supply = <&vdd_ac_bat_reg>; 830*724ba675SRob Herring vsys-l2-supply = <&vdd_ac_bat_reg>; 831*724ba675SRob Herring 832*724ba675SRob Herring charger: charger { 833*724ba675SRob Herring compatible = "ti,tps65090-charger"; 834*724ba675SRob Herring ti,enable-low-current-chrg; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring regulators { 838*724ba675SRob Herring tps65090_dcdc1_reg: dcdc1 { 839*724ba675SRob Herring regulator-name = "vdd-sys-5v0"; 840*724ba675SRob Herring regulator-always-on; 841*724ba675SRob Herring regulator-boot-on; 842*724ba675SRob Herring }; 843*724ba675SRob Herring 844*724ba675SRob Herring tps65090_dcdc2_reg: dcdc2 { 845*724ba675SRob Herring regulator-name = "vdd-sys-3v3"; 846*724ba675SRob Herring regulator-always-on; 847*724ba675SRob Herring regulator-boot-on; 848*724ba675SRob Herring }; 849*724ba675SRob Herring 850*724ba675SRob Herring tps65090_dcdc3_reg: dcdc3 { 851*724ba675SRob Herring regulator-name = "vdd-ao"; 852*724ba675SRob Herring regulator-always-on; 853*724ba675SRob Herring regulator-boot-on; 854*724ba675SRob Herring }; 855*724ba675SRob Herring 856*724ba675SRob Herring vdd_bl_reg: fet1 { 857*724ba675SRob Herring regulator-name = "vdd-lcd-bl"; 858*724ba675SRob Herring }; 859*724ba675SRob Herring 860*724ba675SRob Herring fet3 { 861*724ba675SRob Herring regulator-name = "vdd-modem-3v3"; 862*724ba675SRob Herring }; 863*724ba675SRob Herring 864*724ba675SRob Herring avdd_lcd_reg: fet4 { 865*724ba675SRob Herring regulator-name = "avdd-lcd"; 866*724ba675SRob Herring }; 867*724ba675SRob Herring 868*724ba675SRob Herring fet5 { 869*724ba675SRob Herring regulator-name = "vdd-lvds"; 870*724ba675SRob Herring }; 871*724ba675SRob Herring 872*724ba675SRob Herring fet6 { 873*724ba675SRob Herring regulator-name = "vdd-sd-slot"; 874*724ba675SRob Herring regulator-always-on; 875*724ba675SRob Herring regulator-boot-on; 876*724ba675SRob Herring }; 877*724ba675SRob Herring 878*724ba675SRob Herring fet7 { 879*724ba675SRob Herring regulator-name = "vdd-com-3v3"; 880*724ba675SRob Herring }; 881*724ba675SRob Herring 882*724ba675SRob Herring ldo1 { 883*724ba675SRob Herring regulator-name = "vdd-sby-5v0"; 884*724ba675SRob Herring regulator-always-on; 885*724ba675SRob Herring regulator-boot-on; 886*724ba675SRob Herring }; 887*724ba675SRob Herring 888*724ba675SRob Herring ldo2 { 889*724ba675SRob Herring regulator-name = "vdd-sby-3v3"; 890*724ba675SRob Herring regulator-always-on; 891*724ba675SRob Herring regulator-boot-on; 892*724ba675SRob Herring }; 893*724ba675SRob Herring }; 894*724ba675SRob Herring }; 895*724ba675SRob Herring 896*724ba675SRob Herring palmas: tps65913@58 { 897*724ba675SRob Herring compatible = "ti,tps65913", "ti,palmas"; 898*724ba675SRob Herring reg = <0x58>; 899*724ba675SRob Herring interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 900*724ba675SRob Herring 901*724ba675SRob Herring #interrupt-cells = <2>; 902*724ba675SRob Herring interrupt-controller; 903*724ba675SRob Herring 904*724ba675SRob Herring ti,system-power-controller; 905*724ba675SRob Herring 906*724ba675SRob Herring palmas_gpio: gpio { 907*724ba675SRob Herring compatible = "ti,palmas-gpio"; 908*724ba675SRob Herring gpio-controller; 909*724ba675SRob Herring #gpio-cells = <2>; 910*724ba675SRob Herring }; 911*724ba675SRob Herring 912*724ba675SRob Herring pinmux { 913*724ba675SRob Herring compatible = "ti,tps65913-pinctrl"; 914*724ba675SRob Herring pinctrl-names = "default"; 915*724ba675SRob Herring pinctrl-0 = <&palmas_default>; 916*724ba675SRob Herring 917*724ba675SRob Herring palmas_default: pinmux { 918*724ba675SRob Herring pin_gpio6 { 919*724ba675SRob Herring pins = "gpio6"; 920*724ba675SRob Herring function = "gpio"; 921*724ba675SRob Herring }; 922*724ba675SRob Herring }; 923*724ba675SRob Herring }; 924*724ba675SRob Herring 925*724ba675SRob Herring pmic { 926*724ba675SRob Herring compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 927*724ba675SRob Herring smps1-in-supply = <&tps65090_dcdc3_reg>; 928*724ba675SRob Herring smps3-in-supply = <&tps65090_dcdc3_reg>; 929*724ba675SRob Herring smps4-in-supply = <&tps65090_dcdc2_reg>; 930*724ba675SRob Herring smps7-in-supply = <&tps65090_dcdc2_reg>; 931*724ba675SRob Herring smps8-in-supply = <&tps65090_dcdc2_reg>; 932*724ba675SRob Herring smps9-in-supply = <&tps65090_dcdc2_reg>; 933*724ba675SRob Herring ldo1-in-supply = <&tps65090_dcdc2_reg>; 934*724ba675SRob Herring ldo2-in-supply = <&tps65090_dcdc2_reg>; 935*724ba675SRob Herring ldo3-in-supply = <&palmas_smps3_reg>; 936*724ba675SRob Herring ldo4-in-supply = <&tps65090_dcdc2_reg>; 937*724ba675SRob Herring ldo5-in-supply = <&vdd_ac_bat_reg>; 938*724ba675SRob Herring ldo6-in-supply = <&tps65090_dcdc2_reg>; 939*724ba675SRob Herring ldo7-in-supply = <&tps65090_dcdc2_reg>; 940*724ba675SRob Herring ldo8-in-supply = <&tps65090_dcdc3_reg>; 941*724ba675SRob Herring ldo9-in-supply = <&palmas_smps9_reg>; 942*724ba675SRob Herring ldoln-in-supply = <&tps65090_dcdc1_reg>; 943*724ba675SRob Herring ldousb-in-supply = <&tps65090_dcdc1_reg>; 944*724ba675SRob Herring 945*724ba675SRob Herring regulators { 946*724ba675SRob Herring smps12 { 947*724ba675SRob Herring regulator-name = "vddio-ddr"; 948*724ba675SRob Herring regulator-min-microvolt = <1350000>; 949*724ba675SRob Herring regulator-max-microvolt = <1350000>; 950*724ba675SRob Herring regulator-always-on; 951*724ba675SRob Herring regulator-boot-on; 952*724ba675SRob Herring }; 953*724ba675SRob Herring 954*724ba675SRob Herring palmas_smps3_reg: smps3 { 955*724ba675SRob Herring regulator-name = "vddio-1v8"; 956*724ba675SRob Herring regulator-min-microvolt = <1800000>; 957*724ba675SRob Herring regulator-max-microvolt = <1800000>; 958*724ba675SRob Herring regulator-always-on; 959*724ba675SRob Herring regulator-boot-on; 960*724ba675SRob Herring }; 961*724ba675SRob Herring 962*724ba675SRob Herring smps45 { 963*724ba675SRob Herring regulator-name = "vdd-core"; 964*724ba675SRob Herring regulator-min-microvolt = <900000>; 965*724ba675SRob Herring regulator-max-microvolt = <1400000>; 966*724ba675SRob Herring regulator-always-on; 967*724ba675SRob Herring regulator-boot-on; 968*724ba675SRob Herring }; 969*724ba675SRob Herring 970*724ba675SRob Herring smps457 { 971*724ba675SRob Herring regulator-name = "vdd-core"; 972*724ba675SRob Herring regulator-min-microvolt = <900000>; 973*724ba675SRob Herring regulator-max-microvolt = <1400000>; 974*724ba675SRob Herring regulator-always-on; 975*724ba675SRob Herring regulator-boot-on; 976*724ba675SRob Herring }; 977*724ba675SRob Herring 978*724ba675SRob Herring smps8 { 979*724ba675SRob Herring regulator-name = "avdd-pll"; 980*724ba675SRob Herring regulator-min-microvolt = <1050000>; 981*724ba675SRob Herring regulator-max-microvolt = <1050000>; 982*724ba675SRob Herring regulator-always-on; 983*724ba675SRob Herring regulator-boot-on; 984*724ba675SRob Herring }; 985*724ba675SRob Herring 986*724ba675SRob Herring palmas_smps9_reg: smps9 { 987*724ba675SRob Herring regulator-name = "sdhci-vdd-sd-slot"; 988*724ba675SRob Herring regulator-min-microvolt = <2800000>; 989*724ba675SRob Herring regulator-max-microvolt = <2800000>; 990*724ba675SRob Herring regulator-always-on; 991*724ba675SRob Herring }; 992*724ba675SRob Herring 993*724ba675SRob Herring ldo1 { 994*724ba675SRob Herring regulator-name = "avdd-cam1"; 995*724ba675SRob Herring regulator-min-microvolt = <2800000>; 996*724ba675SRob Herring regulator-max-microvolt = <2800000>; 997*724ba675SRob Herring }; 998*724ba675SRob Herring 999*724ba675SRob Herring ldo2 { 1000*724ba675SRob Herring regulator-name = "avdd-cam2"; 1001*724ba675SRob Herring regulator-min-microvolt = <2800000>; 1002*724ba675SRob Herring regulator-max-microvolt = <2800000>; 1003*724ba675SRob Herring }; 1004*724ba675SRob Herring 1005*724ba675SRob Herring avdd_1v2_reg: ldo3 { 1006*724ba675SRob Herring regulator-name = "avdd-dsi-csi"; 1007*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1008*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1009*724ba675SRob Herring }; 1010*724ba675SRob Herring 1011*724ba675SRob Herring ldo4 { 1012*724ba675SRob Herring regulator-name = "vpp-fuse"; 1013*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1014*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1015*724ba675SRob Herring }; 1016*724ba675SRob Herring 1017*724ba675SRob Herring palmas_ldo6_reg: ldo6 { 1018*724ba675SRob Herring regulator-name = "vdd-sensor-2v85"; 1019*724ba675SRob Herring regulator-min-microvolt = <2850000>; 1020*724ba675SRob Herring regulator-max-microvolt = <2850000>; 1021*724ba675SRob Herring }; 1022*724ba675SRob Herring 1023*724ba675SRob Herring ldo7 { 1024*724ba675SRob Herring regulator-name = "vdd-af-cam1"; 1025*724ba675SRob Herring regulator-min-microvolt = <2800000>; 1026*724ba675SRob Herring regulator-max-microvolt = <2800000>; 1027*724ba675SRob Herring }; 1028*724ba675SRob Herring 1029*724ba675SRob Herring ldo8 { 1030*724ba675SRob Herring regulator-name = "vdd-rtc"; 1031*724ba675SRob Herring regulator-min-microvolt = <900000>; 1032*724ba675SRob Herring regulator-max-microvolt = <900000>; 1033*724ba675SRob Herring regulator-always-on; 1034*724ba675SRob Herring regulator-boot-on; 1035*724ba675SRob Herring ti,enable-ldo8-tracking; 1036*724ba675SRob Herring }; 1037*724ba675SRob Herring 1038*724ba675SRob Herring ldo9 { 1039*724ba675SRob Herring regulator-name = "vddio-sdmmc-2"; 1040*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1041*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1042*724ba675SRob Herring regulator-always-on; 1043*724ba675SRob Herring regulator-boot-on; 1044*724ba675SRob Herring }; 1045*724ba675SRob Herring 1046*724ba675SRob Herring ldoln { 1047*724ba675SRob Herring regulator-name = "hvdd-usb"; 1048*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1049*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1050*724ba675SRob Herring }; 1051*724ba675SRob Herring 1052*724ba675SRob Herring ldousb { 1053*724ba675SRob Herring regulator-name = "avdd-usb"; 1054*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1055*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1056*724ba675SRob Herring regulator-always-on; 1057*724ba675SRob Herring regulator-boot-on; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring 1060*724ba675SRob Herring regen1 { 1061*724ba675SRob Herring regulator-name = "rail-3v3"; 1062*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1063*724ba675SRob Herring regulator-always-on; 1064*724ba675SRob Herring regulator-boot-on; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring 1067*724ba675SRob Herring regen2 { 1068*724ba675SRob Herring regulator-name = "rail-5v0"; 1069*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1070*724ba675SRob Herring regulator-always-on; 1071*724ba675SRob Herring regulator-boot-on; 1072*724ba675SRob Herring }; 1073*724ba675SRob Herring }; 1074*724ba675SRob Herring }; 1075*724ba675SRob Herring 1076*724ba675SRob Herring rtc { 1077*724ba675SRob Herring compatible = "ti,palmas-rtc"; 1078*724ba675SRob Herring interrupt-parent = <&palmas>; 1079*724ba675SRob Herring interrupts = <8 0>; 1080*724ba675SRob Herring }; 1081*724ba675SRob Herring }; 1082*724ba675SRob Herring }; 1083*724ba675SRob Herring 1084*724ba675SRob Herring spi@7000da00 { 1085*724ba675SRob Herring status = "okay"; 1086*724ba675SRob Herring spi-max-frequency = <25000000>; 1087*724ba675SRob Herring 1088*724ba675SRob Herring flash@0 { 1089*724ba675SRob Herring compatible = "winbond,w25q32dw", "jedec,spi-nor"; 1090*724ba675SRob Herring reg = <0>; 1091*724ba675SRob Herring spi-max-frequency = <20000000>; 1092*724ba675SRob Herring }; 1093*724ba675SRob Herring }; 1094*724ba675SRob Herring 1095*724ba675SRob Herring pmc@7000e400 { 1096*724ba675SRob Herring nvidia,invert-interrupt; 1097*724ba675SRob Herring nvidia,suspend-mode = <1>; 1098*724ba675SRob Herring nvidia,cpu-pwr-good-time = <500>; 1099*724ba675SRob Herring nvidia,cpu-pwr-off-time = <300>; 1100*724ba675SRob Herring nvidia,core-pwr-good-time = <641 3845>; 1101*724ba675SRob Herring nvidia,core-pwr-off-time = <61036>; 1102*724ba675SRob Herring nvidia,core-power-req-active-high; 1103*724ba675SRob Herring nvidia,sys-clock-req-active-high; 1104*724ba675SRob Herring }; 1105*724ba675SRob Herring 1106*724ba675SRob Herring ahub@70080000 { 1107*724ba675SRob Herring i2s@70080400 { 1108*724ba675SRob Herring status = "okay"; 1109*724ba675SRob Herring }; 1110*724ba675SRob Herring }; 1111*724ba675SRob Herring 1112*724ba675SRob Herring mmc@78000400 { 1113*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1114*724ba675SRob Herring wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; 1115*724ba675SRob Herring bus-width = <4>; 1116*724ba675SRob Herring status = "okay"; 1117*724ba675SRob Herring }; 1118*724ba675SRob Herring 1119*724ba675SRob Herring mmc@78000600 { 1120*724ba675SRob Herring bus-width = <8>; 1121*724ba675SRob Herring status = "okay"; 1122*724ba675SRob Herring non-removable; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring 1125*724ba675SRob Herring usb@7d000000 { 1126*724ba675SRob Herring compatible = "nvidia,tegra114-udc"; 1127*724ba675SRob Herring status = "okay"; 1128*724ba675SRob Herring dr_mode = "peripheral"; 1129*724ba675SRob Herring }; 1130*724ba675SRob Herring 1131*724ba675SRob Herring usb-phy@7d000000 { 1132*724ba675SRob Herring status = "okay"; 1133*724ba675SRob Herring }; 1134*724ba675SRob Herring 1135*724ba675SRob Herring usb@7d008000 { 1136*724ba675SRob Herring status = "okay"; 1137*724ba675SRob Herring }; 1138*724ba675SRob Herring 1139*724ba675SRob Herring usb-phy@7d008000 { 1140*724ba675SRob Herring status = "okay"; 1141*724ba675SRob Herring vbus-supply = <&usb3_vbus_reg>; 1142*724ba675SRob Herring }; 1143*724ba675SRob Herring 1144*724ba675SRob Herring backlight: backlight { 1145*724ba675SRob Herring compatible = "pwm-backlight"; 1146*724ba675SRob Herring 1147*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1148*724ba675SRob Herring power-supply = <&vdd_bl_reg>; 1149*724ba675SRob Herring pwms = <&pwm 1 1000000>; 1150*724ba675SRob Herring 1151*724ba675SRob Herring brightness-levels = <0 4 8 16 32 64 128 255>; 1152*724ba675SRob Herring default-brightness-level = <6>; 1153*724ba675SRob Herring }; 1154*724ba675SRob Herring 1155*724ba675SRob Herring clk32k_in: clock-32k { 1156*724ba675SRob Herring compatible = "fixed-clock"; 1157*724ba675SRob Herring clock-frequency = <32768>; 1158*724ba675SRob Herring #clock-cells = <0>; 1159*724ba675SRob Herring }; 1160*724ba675SRob Herring 1161*724ba675SRob Herring gpio-keys { 1162*724ba675SRob Herring compatible = "gpio-keys"; 1163*724ba675SRob Herring 1164*724ba675SRob Herring key-home { 1165*724ba675SRob Herring label = "Home"; 1166*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 1167*724ba675SRob Herring linux,code = <KEY_HOME>; 1168*724ba675SRob Herring }; 1169*724ba675SRob Herring 1170*724ba675SRob Herring key-power { 1171*724ba675SRob Herring label = "Power"; 1172*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1173*724ba675SRob Herring linux,code = <KEY_POWER>; 1174*724ba675SRob Herring wakeup-source; 1175*724ba675SRob Herring }; 1176*724ba675SRob Herring 1177*724ba675SRob Herring key-volume-down { 1178*724ba675SRob Herring label = "Volume Down"; 1179*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1180*724ba675SRob Herring linux,code = <KEY_VOLUMEDOWN>; 1181*724ba675SRob Herring }; 1182*724ba675SRob Herring 1183*724ba675SRob Herring key-volume-up { 1184*724ba675SRob Herring label = "Volume Up"; 1185*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1186*724ba675SRob Herring linux,code = <KEY_VOLUMEUP>; 1187*724ba675SRob Herring }; 1188*724ba675SRob Herring }; 1189*724ba675SRob Herring 1190*724ba675SRob Herring vdd_ac_bat_reg: regulator-acbat { 1191*724ba675SRob Herring compatible = "regulator-fixed"; 1192*724ba675SRob Herring regulator-name = "vdd_ac_bat"; 1193*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1194*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1195*724ba675SRob Herring regulator-always-on; 1196*724ba675SRob Herring }; 1197*724ba675SRob Herring 1198*724ba675SRob Herring dvdd_ts_reg: regulator-ts { 1199*724ba675SRob Herring compatible = "regulator-fixed"; 1200*724ba675SRob Herring regulator-name = "dvdd_ts"; 1201*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1202*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1203*724ba675SRob Herring enable-active-high; 1204*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; 1205*724ba675SRob Herring }; 1206*724ba675SRob Herring 1207*724ba675SRob Herring usb1_vbus_reg: regulator-usb1 { 1208*724ba675SRob Herring compatible = "regulator-fixed"; 1209*724ba675SRob Herring regulator-name = "usb1_vbus"; 1210*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1211*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1212*724ba675SRob Herring enable-active-high; 1213*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 1214*724ba675SRob Herring gpio-open-drain; 1215*724ba675SRob Herring vin-supply = <&tps65090_dcdc1_reg>; 1216*724ba675SRob Herring }; 1217*724ba675SRob Herring 1218*724ba675SRob Herring usb3_vbus_reg: regulator-usb3 { 1219*724ba675SRob Herring compatible = "regulator-fixed"; 1220*724ba675SRob Herring regulator-name = "usb2_vbus"; 1221*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1222*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1223*724ba675SRob Herring enable-active-high; 1224*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1225*724ba675SRob Herring gpio-open-drain; 1226*724ba675SRob Herring vin-supply = <&tps65090_dcdc1_reg>; 1227*724ba675SRob Herring }; 1228*724ba675SRob Herring 1229*724ba675SRob Herring vdd_hdmi_reg: regulator-hdmi { 1230*724ba675SRob Herring compatible = "regulator-fixed"; 1231*724ba675SRob Herring regulator-name = "vdd_hdmi_5v0"; 1232*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1233*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1234*724ba675SRob Herring vin-supply = <&tps65090_dcdc1_reg>; 1235*724ba675SRob Herring }; 1236*724ba675SRob Herring 1237*724ba675SRob Herring vdd_cam_1v8_reg: regulator-cam { 1238*724ba675SRob Herring compatible = "regulator-fixed"; 1239*724ba675SRob Herring regulator-name = "vdd_cam_1v8_reg"; 1240*724ba675SRob Herring regulator-min-microvolt = <1800000>; 1241*724ba675SRob Herring regulator-max-microvolt = <1800000>; 1242*724ba675SRob Herring enable-active-high; 1243*724ba675SRob Herring gpio = <&palmas_gpio 6 0>; 1244*724ba675SRob Herring }; 1245*724ba675SRob Herring 1246*724ba675SRob Herring vdd_5v0_hdmi: regulator-hdmicon { 1247*724ba675SRob Herring compatible = "regulator-fixed"; 1248*724ba675SRob Herring regulator-name = "VDD_5V0_HDMI_CON"; 1249*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1250*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1251*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1252*724ba675SRob Herring enable-active-high; 1253*724ba675SRob Herring vin-supply = <&tps65090_dcdc1_reg>; 1254*724ba675SRob Herring }; 1255*724ba675SRob Herring 1256*724ba675SRob Herring sound { 1257*724ba675SRob Herring compatible = "nvidia,tegra-audio-rt5640-dalmore", 1258*724ba675SRob Herring "nvidia,tegra-audio-rt5640"; 1259*724ba675SRob Herring nvidia,model = "NVIDIA Tegra Dalmore"; 1260*724ba675SRob Herring 1261*724ba675SRob Herring nvidia,audio-routing = 1262*724ba675SRob Herring "Headphones", "HPOR", 1263*724ba675SRob Herring "Headphones", "HPOL", 1264*724ba675SRob Herring "Speakers", "SPORP", 1265*724ba675SRob Herring "Speakers", "SPORN", 1266*724ba675SRob Herring "Speakers", "SPOLP", 1267*724ba675SRob Herring "Speakers", "SPOLN", 1268*724ba675SRob Herring "Mic Jack", "MICBIAS1", 1269*724ba675SRob Herring "IN2P", "Mic Jack"; 1270*724ba675SRob Herring 1271*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 1272*724ba675SRob Herring nvidia,audio-codec = <&rt5640>; 1273*724ba675SRob Herring 1274*724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; 1275*724ba675SRob Herring 1276*724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_PLL_A>, 1277*724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1278*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1279*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 1280*724ba675SRob Herring 1281*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, 1282*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1283*724ba675SRob Herring 1284*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1285*724ba675SRob Herring <&tegra_car TEGRA114_CLK_EXTERN1>; 1286*724ba675SRob Herring }; 1287*724ba675SRob Herring}; 1288