1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com 3*724ba675SRob Herring// Copyright 2018 Google, Inc. 4*724ba675SRob Herring 5*724ba675SRob Herring#include "nuvoton-common-npcm7xx.dtsi" 6*724ba675SRob Herring 7*724ba675SRob Herring/ { 8*724ba675SRob Herring #address-cells = <1>; 9*724ba675SRob Herring #size-cells = <1>; 10*724ba675SRob Herring interrupt-parent = <&gic>; 11*724ba675SRob Herring 12*724ba675SRob Herring cpus { 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <0>; 15*724ba675SRob Herring enable-method = "nuvoton,npcm750-smp"; 16*724ba675SRob Herring 17*724ba675SRob Herring cpu@0 { 18*724ba675SRob Herring device_type = "cpu"; 19*724ba675SRob Herring compatible = "arm,cortex-a9"; 20*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_CPU>; 21*724ba675SRob Herring clock-names = "clk_cpu"; 22*724ba675SRob Herring reg = <0>; 23*724ba675SRob Herring next-level-cache = <&l2>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring cpu@1 { 27*724ba675SRob Herring device_type = "cpu"; 28*724ba675SRob Herring compatible = "arm,cortex-a9"; 29*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_CPU>; 30*724ba675SRob Herring clock-names = "clk_cpu"; 31*724ba675SRob Herring reg = <1>; 32*724ba675SRob Herring next-level-cache = <&l2>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring soc { 37*724ba675SRob Herring timer@3fe600 { 38*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 39*724ba675SRob Herring reg = <0x3fe600 0x20>; 40*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 41*724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 42*724ba675SRob Herring clocks = <&clk NPCM7XX_CLK_AHB>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring }; 45*724ba675SRob Herring 46*724ba675SRob Herring ahb { 47*724ba675SRob Herring gmac1: eth@f0804000 { 48*724ba675SRob Herring device_type = "network"; 49*724ba675SRob Herring compatible = "snps,dwmac"; 50*724ba675SRob Herring reg = <0xf0804000 0x2000>; 51*724ba675SRob Herring interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 52*724ba675SRob Herring interrupt-names = "macirq"; 53*724ba675SRob Herring ethernet = <1>; 54*724ba675SRob Herring clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; 55*724ba675SRob Herring clock-names = "stmmaceth", "clk_gmac"; 56*724ba675SRob Herring pinctrl-names = "default"; 57*724ba675SRob Herring pinctrl-0 = <&rg2_pins 58*724ba675SRob Herring &rg2mdio_pins>; 59*724ba675SRob Herring status = "disabled"; 60*724ba675SRob Herring }; 61*724ba675SRob Herring }; 62*724ba675SRob Herring}; 63