xref: /linux/scripts/dtc/include-prefixes/arm/microchip/lan966x.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
6*724ba675SRob Herring *
7*724ba675SRob Herring * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
8*724ba675SRob Herring *
9*724ba675SRob Herring */
10*724ba675SRob Herring
11*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h>
12*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h>
13*724ba675SRob Herring#include <dt-bindings/mfd/atmel-flexcom.h>
14*724ba675SRob Herring#include <dt-bindings/dma/at91.h>
15*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h>
16*724ba675SRob Herring#include <dt-bindings/clock/microchip,lan966x.h>
17*724ba675SRob Herring
18*724ba675SRob Herring/ {
19*724ba675SRob Herring	model = "Microchip LAN966 family SoC";
20*724ba675SRob Herring	compatible = "microchip,lan966";
21*724ba675SRob Herring	interrupt-parent = <&gic>;
22*724ba675SRob Herring	#address-cells = <1>;
23*724ba675SRob Herring	#size-cells = <1>;
24*724ba675SRob Herring
25*724ba675SRob Herring	cpus {
26*724ba675SRob Herring		#address-cells = <1>;
27*724ba675SRob Herring		#size-cells = <0>;
28*724ba675SRob Herring
29*724ba675SRob Herring		cpu@0 {
30*724ba675SRob Herring			device_type = "cpu";
31*724ba675SRob Herring			compatible = "arm,cortex-a7";
32*724ba675SRob Herring			clock-frequency = <600000000>;
33*724ba675SRob Herring			reg = <0x0>;
34*724ba675SRob Herring		};
35*724ba675SRob Herring	};
36*724ba675SRob Herring
37*724ba675SRob Herring	clocks {
38*724ba675SRob Herring		sys_clk: sys_clk {
39*724ba675SRob Herring			compatible = "fixed-clock";
40*724ba675SRob Herring			#clock-cells = <0>;
41*724ba675SRob Herring			clock-frequency = <165625000>;
42*724ba675SRob Herring		};
43*724ba675SRob Herring
44*724ba675SRob Herring		cpu_clk: cpu_clk {
45*724ba675SRob Herring			compatible = "fixed-clock";
46*724ba675SRob Herring			#clock-cells = <0>;
47*724ba675SRob Herring			clock-frequency = <600000000>;
48*724ba675SRob Herring		};
49*724ba675SRob Herring
50*724ba675SRob Herring		ddr_clk: ddr_clk {
51*724ba675SRob Herring			compatible = "fixed-clock";
52*724ba675SRob Herring			#clock-cells = <0>;
53*724ba675SRob Herring			clock-frequency = <300000000>;
54*724ba675SRob Herring		};
55*724ba675SRob Herring
56*724ba675SRob Herring		nic_clk: nic_clk {
57*724ba675SRob Herring			compatible = "fixed-clock";
58*724ba675SRob Herring			#clock-cells = <0>;
59*724ba675SRob Herring			clock-frequency = <200000000>;
60*724ba675SRob Herring		};
61*724ba675SRob Herring	};
62*724ba675SRob Herring
63*724ba675SRob Herring	clks: clock-controller@e00c00a8 {
64*724ba675SRob Herring		compatible = "microchip,lan966x-gck";
65*724ba675SRob Herring		#clock-cells = <1>;
66*724ba675SRob Herring		clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
67*724ba675SRob Herring		clock-names = "cpu", "ddr", "sys";
68*724ba675SRob Herring		reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
69*724ba675SRob Herring	};
70*724ba675SRob Herring
71*724ba675SRob Herring	timer {
72*724ba675SRob Herring		compatible = "arm,armv7-timer";
73*724ba675SRob Herring		interrupt-parent = <&gic>;
74*724ba675SRob Herring		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75*724ba675SRob Herring			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
76*724ba675SRob Herring			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
77*724ba675SRob Herring			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
78*724ba675SRob Herring		clock-frequency = <37500000>;
79*724ba675SRob Herring	};
80*724ba675SRob Herring
81*724ba675SRob Herring	soc {
82*724ba675SRob Herring		compatible = "simple-bus";
83*724ba675SRob Herring		#address-cells = <1>;
84*724ba675SRob Herring		#size-cells = <1>;
85*724ba675SRob Herring		ranges;
86*724ba675SRob Herring
87*724ba675SRob Herring		udc: usb@200000 {
88*724ba675SRob Herring			compatible = "microchip,lan9662-udc",
89*724ba675SRob Herring				     "atmel,sama5d3-udc";
90*724ba675SRob Herring			reg = <0x00200000 0x80000>,
91*724ba675SRob Herring			      <0xe0808000 0x400>;
92*724ba675SRob Herring			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
93*724ba675SRob Herring			clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
94*724ba675SRob Herring			clock-names = "pclk", "hclk";
95*724ba675SRob Herring			status = "disabled";
96*724ba675SRob Herring		};
97*724ba675SRob Herring
98*724ba675SRob Herring		switch: switch@e0000000 {
99*724ba675SRob Herring			compatible = "microchip,lan966x-switch";
100*724ba675SRob Herring			reg = <0xe0000000 0x0100000>,
101*724ba675SRob Herring			      <0xe2000000 0x0800000>;
102*724ba675SRob Herring			reg-names = "cpu", "gcb";
103*724ba675SRob Herring			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
104*724ba675SRob Herring				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
105*724ba675SRob Herring				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
106*724ba675SRob Herring				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
107*724ba675SRob Herring				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
108*724ba675SRob Herring			interrupt-names = "xtr", "fdma", "ana", "ptp",
109*724ba675SRob Herring					  "ptp-ext";
110*724ba675SRob Herring			resets = <&reset 0>;
111*724ba675SRob Herring			reset-names = "switch";
112*724ba675SRob Herring			status = "disabled";
113*724ba675SRob Herring
114*724ba675SRob Herring			ethernet-ports {
115*724ba675SRob Herring				#address-cells = <1>;
116*724ba675SRob Herring				#size-cells = <0>;
117*724ba675SRob Herring
118*724ba675SRob Herring				port0: port@0 {
119*724ba675SRob Herring					reg = <0>;
120*724ba675SRob Herring					status = "disabled";
121*724ba675SRob Herring				};
122*724ba675SRob Herring
123*724ba675SRob Herring				port1: port@1 {
124*724ba675SRob Herring					reg = <1>;
125*724ba675SRob Herring					status = "disabled";
126*724ba675SRob Herring				};
127*724ba675SRob Herring
128*724ba675SRob Herring				port2: port@2 {
129*724ba675SRob Herring					reg = <2>;
130*724ba675SRob Herring					status = "disabled";
131*724ba675SRob Herring				};
132*724ba675SRob Herring
133*724ba675SRob Herring				port3: port@3 {
134*724ba675SRob Herring					reg = <3>;
135*724ba675SRob Herring					status = "disabled";
136*724ba675SRob Herring				};
137*724ba675SRob Herring
138*724ba675SRob Herring				port4: port@4 {
139*724ba675SRob Herring					reg = <4>;
140*724ba675SRob Herring					status = "disabled";
141*724ba675SRob Herring				};
142*724ba675SRob Herring
143*724ba675SRob Herring				port5: port@5 {
144*724ba675SRob Herring					reg = <5>;
145*724ba675SRob Herring					status = "disabled";
146*724ba675SRob Herring				};
147*724ba675SRob Herring
148*724ba675SRob Herring				port6: port@6 {
149*724ba675SRob Herring					reg = <6>;
150*724ba675SRob Herring					status = "disabled";
151*724ba675SRob Herring				};
152*724ba675SRob Herring
153*724ba675SRob Herring				port7: port@7 {
154*724ba675SRob Herring					reg = <7>;
155*724ba675SRob Herring					status = "disabled";
156*724ba675SRob Herring				};
157*724ba675SRob Herring			};
158*724ba675SRob Herring		};
159*724ba675SRob Herring
160*724ba675SRob Herring		otp: otp@e0021000 {
161*724ba675SRob Herring			compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc";
162*724ba675SRob Herring			reg = <0xe0021000 0x300>;
163*724ba675SRob Herring		};
164*724ba675SRob Herring
165*724ba675SRob Herring		flx0: flexcom@e0040000 {
166*724ba675SRob Herring			compatible = "atmel,sama5d2-flexcom";
167*724ba675SRob Herring			reg = <0xe0040000 0x100>;
168*724ba675SRob Herring			clocks = <&clks GCK_ID_FLEXCOM0>;
169*724ba675SRob Herring			#address-cells = <1>;
170*724ba675SRob Herring			#size-cells = <1>;
171*724ba675SRob Herring			ranges = <0x0 0xe0040000 0x800>;
172*724ba675SRob Herring			status = "disabled";
173*724ba675SRob Herring
174*724ba675SRob Herring			usart0: serial@200 {
175*724ba675SRob Herring				compatible = "atmel,at91sam9260-usart";
176*724ba675SRob Herring				reg = <0x200 0x200>;
177*724ba675SRob Herring				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
178*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
179*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
180*724ba675SRob Herring				dma-names = "tx", "rx";
181*724ba675SRob Herring				clocks = <&nic_clk>;
182*724ba675SRob Herring				clock-names = "usart";
183*724ba675SRob Herring				atmel,fifo-size = <32>;
184*724ba675SRob Herring				status = "disabled";
185*724ba675SRob Herring			};
186*724ba675SRob Herring
187*724ba675SRob Herring			spi0: spi@400 {
188*724ba675SRob Herring				compatible = "atmel,at91rm9200-spi";
189*724ba675SRob Herring				reg = <0x400 0x200>;
190*724ba675SRob Herring				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
191*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
192*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
193*724ba675SRob Herring				dma-names = "tx", "rx";
194*724ba675SRob Herring				clocks = <&nic_clk>;
195*724ba675SRob Herring				clock-names = "spi_clk";
196*724ba675SRob Herring				atmel,fifo-size = <32>;
197*724ba675SRob Herring				#address-cells = <1>;
198*724ba675SRob Herring				#size-cells = <0>;
199*724ba675SRob Herring				status = "disabled";
200*724ba675SRob Herring			};
201*724ba675SRob Herring
202*724ba675SRob Herring			i2c0: i2c@600 {
203*724ba675SRob Herring				compatible = "microchip,sam9x60-i2c";
204*724ba675SRob Herring				reg = <0x600 0x200>;
205*724ba675SRob Herring				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
206*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
207*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
208*724ba675SRob Herring				dma-names = "tx", "rx";
209*724ba675SRob Herring				clocks = <&nic_clk>;
210*724ba675SRob Herring				#address-cells = <1>;
211*724ba675SRob Herring				#size-cells = <0>;
212*724ba675SRob Herring				status = "disabled";
213*724ba675SRob Herring			};
214*724ba675SRob Herring		};
215*724ba675SRob Herring
216*724ba675SRob Herring		flx1: flexcom@e0044000 {
217*724ba675SRob Herring			compatible = "atmel,sama5d2-flexcom";
218*724ba675SRob Herring			reg = <0xe0044000 0x100>;
219*724ba675SRob Herring			clocks = <&clks GCK_ID_FLEXCOM1>;
220*724ba675SRob Herring			#address-cells = <1>;
221*724ba675SRob Herring			#size-cells = <1>;
222*724ba675SRob Herring			ranges = <0x0 0xe0044000 0x800>;
223*724ba675SRob Herring			status = "disabled";
224*724ba675SRob Herring
225*724ba675SRob Herring			usart1: serial@200 {
226*724ba675SRob Herring				compatible = "atmel,at91sam9260-usart";
227*724ba675SRob Herring				reg = <0x200 0x200>;
228*724ba675SRob Herring				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
229*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
230*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
231*724ba675SRob Herring				dma-names = "tx", "rx";
232*724ba675SRob Herring				clocks = <&nic_clk>;
233*724ba675SRob Herring				clock-names = "usart";
234*724ba675SRob Herring				atmel,fifo-size = <32>;
235*724ba675SRob Herring				status = "disabled";
236*724ba675SRob Herring			};
237*724ba675SRob Herring
238*724ba675SRob Herring			spi1: spi@400 {
239*724ba675SRob Herring				compatible = "atmel,at91rm9200-spi";
240*724ba675SRob Herring				reg = <0x400 0x200>;
241*724ba675SRob Herring				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
242*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
243*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
244*724ba675SRob Herring				dma-names = "tx", "rx";
245*724ba675SRob Herring				clocks = <&nic_clk>;
246*724ba675SRob Herring				clock-names = "spi_clk";
247*724ba675SRob Herring				atmel,fifo-size = <32>;
248*724ba675SRob Herring				#address-cells = <1>;
249*724ba675SRob Herring				#size-cells = <0>;
250*724ba675SRob Herring				status = "disabled";
251*724ba675SRob Herring			};
252*724ba675SRob Herring
253*724ba675SRob Herring			i2c1: i2c@600 {
254*724ba675SRob Herring				compatible = "microchip,sam9x60-i2c";
255*724ba675SRob Herring				reg = <0x600 0x200>;
256*724ba675SRob Herring				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
257*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
258*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
259*724ba675SRob Herring				dma-names = "tx", "rx";
260*724ba675SRob Herring				clocks = <&nic_clk>;
261*724ba675SRob Herring				#address-cells = <1>;
262*724ba675SRob Herring				#size-cells = <0>;
263*724ba675SRob Herring				status = "disabled";
264*724ba675SRob Herring			};
265*724ba675SRob Herring		};
266*724ba675SRob Herring
267*724ba675SRob Herring		trng: rng@e0048000 {
268*724ba675SRob Herring			compatible = "atmel,at91sam9g45-trng";
269*724ba675SRob Herring			reg = <0xe0048000 0x100>;
270*724ba675SRob Herring			clocks = <&nic_clk>;
271*724ba675SRob Herring		};
272*724ba675SRob Herring
273*724ba675SRob Herring		aes: crypto@e004c000 {
274*724ba675SRob Herring			compatible = "atmel,at91sam9g46-aes";
275*724ba675SRob Herring			reg = <0xe004c000 0x100>;
276*724ba675SRob Herring			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
277*724ba675SRob Herring			dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
278*724ba675SRob Herring			       <&dma0 AT91_XDMAC_DT_PERID(13)>;
279*724ba675SRob Herring			dma-names = "tx", "rx";
280*724ba675SRob Herring			clocks = <&nic_clk>;
281*724ba675SRob Herring			clock-names = "aes_clk";
282*724ba675SRob Herring		};
283*724ba675SRob Herring
284*724ba675SRob Herring		flx2: flexcom@e0060000 {
285*724ba675SRob Herring			compatible = "atmel,sama5d2-flexcom";
286*724ba675SRob Herring			reg = <0xe0060000 0x100>;
287*724ba675SRob Herring			clocks = <&clks GCK_ID_FLEXCOM2>;
288*724ba675SRob Herring			#address-cells = <1>;
289*724ba675SRob Herring			#size-cells = <1>;
290*724ba675SRob Herring			ranges = <0x0 0xe0060000 0x800>;
291*724ba675SRob Herring			status = "disabled";
292*724ba675SRob Herring
293*724ba675SRob Herring			usart2: serial@200 {
294*724ba675SRob Herring				compatible = "atmel,at91sam9260-usart";
295*724ba675SRob Herring				reg = <0x200 0x200>;
296*724ba675SRob Herring				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
297*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
298*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
299*724ba675SRob Herring				dma-names = "tx", "rx";
300*724ba675SRob Herring				clocks = <&nic_clk>;
301*724ba675SRob Herring				clock-names = "usart";
302*724ba675SRob Herring				atmel,fifo-size = <32>;
303*724ba675SRob Herring				status = "disabled";
304*724ba675SRob Herring			};
305*724ba675SRob Herring
306*724ba675SRob Herring			spi2: spi@400 {
307*724ba675SRob Herring				compatible = "atmel,at91rm9200-spi";
308*724ba675SRob Herring				reg = <0x400 0x200>;
309*724ba675SRob Herring				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
310*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
311*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
312*724ba675SRob Herring				dma-names = "tx", "rx";
313*724ba675SRob Herring				clocks = <&nic_clk>;
314*724ba675SRob Herring				clock-names = "spi_clk";
315*724ba675SRob Herring				atmel,fifo-size = <32>;
316*724ba675SRob Herring				#address-cells = <1>;
317*724ba675SRob Herring				#size-cells = <0>;
318*724ba675SRob Herring				status = "disabled";
319*724ba675SRob Herring			};
320*724ba675SRob Herring
321*724ba675SRob Herring			i2c2: i2c@600 {
322*724ba675SRob Herring				compatible = "microchip,sam9x60-i2c";
323*724ba675SRob Herring				reg = <0x600 0x200>;
324*724ba675SRob Herring				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
325*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
326*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
327*724ba675SRob Herring				dma-names = "tx", "rx";
328*724ba675SRob Herring				clocks = <&nic_clk>;
329*724ba675SRob Herring				#address-cells = <1>;
330*724ba675SRob Herring				#size-cells = <0>;
331*724ba675SRob Herring				status = "disabled";
332*724ba675SRob Herring			};
333*724ba675SRob Herring		};
334*724ba675SRob Herring
335*724ba675SRob Herring		flx3: flexcom@e0064000 {
336*724ba675SRob Herring			compatible = "atmel,sama5d2-flexcom";
337*724ba675SRob Herring			reg = <0xe0064000 0x100>;
338*724ba675SRob Herring			clocks = <&clks GCK_ID_FLEXCOM3>;
339*724ba675SRob Herring			#address-cells = <1>;
340*724ba675SRob Herring			#size-cells = <1>;
341*724ba675SRob Herring			ranges = <0x0 0xe0064000 0x800>;
342*724ba675SRob Herring			status = "disabled";
343*724ba675SRob Herring
344*724ba675SRob Herring			usart3: serial@200 {
345*724ba675SRob Herring				compatible = "atmel,at91sam9260-usart";
346*724ba675SRob Herring				reg = <0x200 0x200>;
347*724ba675SRob Herring				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
348*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
349*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
350*724ba675SRob Herring				dma-names = "tx", "rx";
351*724ba675SRob Herring				clocks = <&nic_clk>;
352*724ba675SRob Herring				clock-names = "usart";
353*724ba675SRob Herring				atmel,fifo-size = <32>;
354*724ba675SRob Herring				status = "disabled";
355*724ba675SRob Herring			};
356*724ba675SRob Herring
357*724ba675SRob Herring			spi3: spi@400 {
358*724ba675SRob Herring				compatible = "atmel,at91rm9200-spi";
359*724ba675SRob Herring				reg = <0x400 0x200>;
360*724ba675SRob Herring				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
361*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
362*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
363*724ba675SRob Herring				dma-names = "tx", "rx";
364*724ba675SRob Herring				clocks = <&nic_clk>;
365*724ba675SRob Herring				clock-names = "spi_clk";
366*724ba675SRob Herring				atmel,fifo-size = <32>;
367*724ba675SRob Herring				#address-cells = <1>;
368*724ba675SRob Herring				#size-cells = <0>;
369*724ba675SRob Herring				status = "disabled";
370*724ba675SRob Herring			};
371*724ba675SRob Herring
372*724ba675SRob Herring			i2c3: i2c@600 {
373*724ba675SRob Herring				compatible = "microchip,sam9x60-i2c";
374*724ba675SRob Herring				reg = <0x600 0x200>;
375*724ba675SRob Herring				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
376*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
377*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
378*724ba675SRob Herring				dma-names = "tx", "rx";
379*724ba675SRob Herring				clocks = <&nic_clk>;
380*724ba675SRob Herring				#address-cells = <1>;
381*724ba675SRob Herring				#size-cells = <0>;
382*724ba675SRob Herring				status = "disabled";
383*724ba675SRob Herring			};
384*724ba675SRob Herring		};
385*724ba675SRob Herring
386*724ba675SRob Herring		dma0: dma-controller@e0068000 {
387*724ba675SRob Herring			compatible = "microchip,sama7g5-dma";
388*724ba675SRob Herring			reg = <0xe0068000 0x1000>;
389*724ba675SRob Herring			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
390*724ba675SRob Herring			#dma-cells = <1>;
391*724ba675SRob Herring			clocks = <&nic_clk>;
392*724ba675SRob Herring			clock-names = "dma_clk";
393*724ba675SRob Herring		};
394*724ba675SRob Herring
395*724ba675SRob Herring		sha: crypto@e006c000 {
396*724ba675SRob Herring			compatible = "atmel,at91sam9g46-sha";
397*724ba675SRob Herring			reg = <0xe006c000 0xec>;
398*724ba675SRob Herring			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
399*724ba675SRob Herring			dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
400*724ba675SRob Herring			dma-names = "tx";
401*724ba675SRob Herring			clocks = <&nic_clk>;
402*724ba675SRob Herring			clock-names = "sha_clk";
403*724ba675SRob Herring		};
404*724ba675SRob Herring
405*724ba675SRob Herring		flx4: flexcom@e0070000 {
406*724ba675SRob Herring			compatible = "atmel,sama5d2-flexcom";
407*724ba675SRob Herring			reg = <0xe0070000 0x100>;
408*724ba675SRob Herring			clocks = <&clks GCK_ID_FLEXCOM4>;
409*724ba675SRob Herring			#address-cells = <1>;
410*724ba675SRob Herring			#size-cells = <1>;
411*724ba675SRob Herring			ranges = <0x0 0xe0070000 0x800>;
412*724ba675SRob Herring			status = "disabled";
413*724ba675SRob Herring
414*724ba675SRob Herring			usart4: serial@200 {
415*724ba675SRob Herring				compatible = "atmel,at91sam9260-usart";
416*724ba675SRob Herring				reg = <0x200 0x200>;
417*724ba675SRob Herring				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
418*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
419*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
420*724ba675SRob Herring				dma-names = "tx", "rx";
421*724ba675SRob Herring				clocks = <&nic_clk>;
422*724ba675SRob Herring				clock-names = "usart";
423*724ba675SRob Herring				atmel,fifo-size = <32>;
424*724ba675SRob Herring				status = "disabled";
425*724ba675SRob Herring			};
426*724ba675SRob Herring
427*724ba675SRob Herring			spi4: spi@400 {
428*724ba675SRob Herring				compatible = "atmel,at91rm9200-spi";
429*724ba675SRob Herring				reg = <0x400 0x200>;
430*724ba675SRob Herring				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
431*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
432*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
433*724ba675SRob Herring				dma-names = "tx", "rx";
434*724ba675SRob Herring				clocks = <&nic_clk>;
435*724ba675SRob Herring				clock-names = "spi_clk";
436*724ba675SRob Herring				atmel,fifo-size = <32>;
437*724ba675SRob Herring				#address-cells = <1>;
438*724ba675SRob Herring				#size-cells = <0>;
439*724ba675SRob Herring				status = "disabled";
440*724ba675SRob Herring			};
441*724ba675SRob Herring
442*724ba675SRob Herring			i2c4: i2c@600 {
443*724ba675SRob Herring				compatible = "microchip,sam9x60-i2c";
444*724ba675SRob Herring				reg = <0x600 0x200>;
445*724ba675SRob Herring				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446*724ba675SRob Herring				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
447*724ba675SRob Herring				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
448*724ba675SRob Herring				dma-names = "tx", "rx";
449*724ba675SRob Herring				clocks = <&nic_clk>;
450*724ba675SRob Herring				#address-cells = <1>;
451*724ba675SRob Herring				#size-cells = <0>;
452*724ba675SRob Herring				status = "disabled";
453*724ba675SRob Herring			};
454*724ba675SRob Herring		};
455*724ba675SRob Herring
456*724ba675SRob Herring		timer0: timer@e008c000 {
457*724ba675SRob Herring			compatible = "snps,dw-apb-timer";
458*724ba675SRob Herring			reg = <0xe008c000 0x400>;
459*724ba675SRob Herring			clocks = <&nic_clk>;
460*724ba675SRob Herring			clock-names = "timer";
461*724ba675SRob Herring			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
462*724ba675SRob Herring		};
463*724ba675SRob Herring
464*724ba675SRob Herring		watchdog: watchdog@e0090000 {
465*724ba675SRob Herring			compatible = "snps,dw-wdt";
466*724ba675SRob Herring			reg = <0xe0090000 0x1000>;
467*724ba675SRob Herring			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
468*724ba675SRob Herring			clocks = <&nic_clk>;
469*724ba675SRob Herring			status = "disabled";
470*724ba675SRob Herring		};
471*724ba675SRob Herring
472*724ba675SRob Herring		cpu_ctrl: syscon@e00c0000 {
473*724ba675SRob Herring			compatible = "microchip,lan966x-cpu-syscon", "syscon";
474*724ba675SRob Herring			reg = <0xe00c0000 0x350>;
475*724ba675SRob Herring		};
476*724ba675SRob Herring
477*724ba675SRob Herring		can0: can@e081c000 {
478*724ba675SRob Herring			compatible = "bosch,m_can";
479*724ba675SRob Herring			reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
480*724ba675SRob Herring			reg-names = "m_can", "message_ram";
481*724ba675SRob Herring			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
482*724ba675SRob Herring				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
483*724ba675SRob Herring			interrupt-names = "int0", "int1";
484*724ba675SRob Herring			clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
485*724ba675SRob Herring			clock-names = "hclk", "cclk";
486*724ba675SRob Herring			assigned-clocks = <&clks GCK_ID_MCAN0>;
487*724ba675SRob Herring			assigned-clock-rates = <40000000>;
488*724ba675SRob Herring			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
489*724ba675SRob Herring			status = "disabled";
490*724ba675SRob Herring		};
491*724ba675SRob Herring
492*724ba675SRob Herring		can1: can@e0820000 {
493*724ba675SRob Herring			compatible = "bosch,m_can";
494*724ba675SRob Herring			reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
495*724ba675SRob Herring			reg-names = "m_can", "message_ram";
496*724ba675SRob Herring			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
497*724ba675SRob Herring				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
498*724ba675SRob Herring			interrupt-names = "int0", "int1";
499*724ba675SRob Herring			clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
500*724ba675SRob Herring			clock-names = "hclk", "cclk";
501*724ba675SRob Herring			assigned-clocks = <&clks GCK_ID_MCAN1>;
502*724ba675SRob Herring			assigned-clock-rates = <40000000>;
503*724ba675SRob Herring			bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
504*724ba675SRob Herring			status = "disabled";
505*724ba675SRob Herring		};
506*724ba675SRob Herring
507*724ba675SRob Herring		reset: reset-controller@e200400c {
508*724ba675SRob Herring			compatible = "microchip,lan966x-switch-reset";
509*724ba675SRob Herring			reg = <0xe200400c 0x4>;
510*724ba675SRob Herring			reg-names = "gcb";
511*724ba675SRob Herring			#reset-cells = <1>;
512*724ba675SRob Herring			cpu-syscon = <&cpu_ctrl>;
513*724ba675SRob Herring		};
514*724ba675SRob Herring
515*724ba675SRob Herring		gpio: pinctrl@e2004064 {
516*724ba675SRob Herring			compatible = "microchip,lan966x-pinctrl";
517*724ba675SRob Herring			reg = <0xe2004064 0xb4>,
518*724ba675SRob Herring			    <0xe2010024 0x138>;
519*724ba675SRob Herring			resets = <&reset 0>;
520*724ba675SRob Herring			reset-names = "switch";
521*724ba675SRob Herring			gpio-controller;
522*724ba675SRob Herring			#gpio-cells = <2>;
523*724ba675SRob Herring			gpio-ranges = <&gpio 0 0 78>;
524*724ba675SRob Herring			interrupt-controller;
525*724ba675SRob Herring			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
526*724ba675SRob Herring			#interrupt-cells = <2>;
527*724ba675SRob Herring		};
528*724ba675SRob Herring
529*724ba675SRob Herring		mdio0: mdio@e2004118 {
530*724ba675SRob Herring			compatible = "microchip,lan966x-miim";
531*724ba675SRob Herring			#address-cells = <1>;
532*724ba675SRob Herring			#size-cells = <0>;
533*724ba675SRob Herring			reg = <0xe2004118 0x24>;
534*724ba675SRob Herring			clocks = <&sys_clk>;
535*724ba675SRob Herring			status = "disabled";
536*724ba675SRob Herring		};
537*724ba675SRob Herring
538*724ba675SRob Herring		mdio1: mdio@e200413c {
539*724ba675SRob Herring			compatible = "microchip,lan966x-miim";
540*724ba675SRob Herring			#address-cells = <1>;
541*724ba675SRob Herring			#size-cells = <0>;
542*724ba675SRob Herring			reg = <0xe200413c 0x24>,
543*724ba675SRob Herring			      <0xe2010020 0x4>;
544*724ba675SRob Herring			clocks = <&sys_clk>;
545*724ba675SRob Herring			status = "disabled";
546*724ba675SRob Herring
547*724ba675SRob Herring			phy0: ethernet-phy@1 {
548*724ba675SRob Herring				reg = <1>;
549*724ba675SRob Herring				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
550*724ba675SRob Herring				status = "disabled";
551*724ba675SRob Herring			};
552*724ba675SRob Herring
553*724ba675SRob Herring			phy1: ethernet-phy@2 {
554*724ba675SRob Herring				reg = <2>;
555*724ba675SRob Herring				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
556*724ba675SRob Herring				status = "disabled";
557*724ba675SRob Herring			};
558*724ba675SRob Herring		};
559*724ba675SRob Herring
560*724ba675SRob Herring		sgpio: gpio@e2004190 {
561*724ba675SRob Herring			compatible = "microchip,sparx5-sgpio";
562*724ba675SRob Herring			reg = <0xe2004190 0x118>;
563*724ba675SRob Herring			clocks = <&sys_clk>;
564*724ba675SRob Herring			resets = <&reset 0>;
565*724ba675SRob Herring			reset-names = "switch";
566*724ba675SRob Herring			#address-cells = <1>;
567*724ba675SRob Herring			#size-cells = <0>;
568*724ba675SRob Herring			status = "disabled";
569*724ba675SRob Herring
570*724ba675SRob Herring			sgpio_in: gpio@0 {
571*724ba675SRob Herring				compatible = "microchip,sparx5-sgpio-bank";
572*724ba675SRob Herring				reg = <0>;
573*724ba675SRob Herring				gpio-controller;
574*724ba675SRob Herring				#gpio-cells = <3>;
575*724ba675SRob Herring				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
576*724ba675SRob Herring				interrupt-controller;
577*724ba675SRob Herring				#interrupt-cells = <3>;
578*724ba675SRob Herring			};
579*724ba675SRob Herring
580*724ba675SRob Herring			sgpio_out: gpio@1 {
581*724ba675SRob Herring				compatible = "microchip,sparx5-sgpio-bank";
582*724ba675SRob Herring				reg = <1>;
583*724ba675SRob Herring				gpio-controller;
584*724ba675SRob Herring				#gpio-cells = <3>;
585*724ba675SRob Herring			};
586*724ba675SRob Herring		};
587*724ba675SRob Herring
588*724ba675SRob Herring		hwmon: hwmon@e2010180 {
589*724ba675SRob Herring			compatible = "microchip,lan9668-hwmon";
590*724ba675SRob Herring			reg = <0xe2010180 0xc>,
591*724ba675SRob Herring			      <0xe20042a8 0xc>;
592*724ba675SRob Herring			reg-names = "pvt", "fan";
593*724ba675SRob Herring			clocks = <&sys_clk>;
594*724ba675SRob Herring		};
595*724ba675SRob Herring
596*724ba675SRob Herring		serdes: serdes@e202c000 {
597*724ba675SRob Herring			compatible = "microchip,lan966x-serdes";
598*724ba675SRob Herring			reg = <0xe202c000 0x9c>,
599*724ba675SRob Herring			      <0xe2004010 0x4>;
600*724ba675SRob Herring			#phy-cells = <2>;
601*724ba675SRob Herring			status = "disabled";
602*724ba675SRob Herring		};
603*724ba675SRob Herring
604*724ba675SRob Herring		gic: interrupt-controller@e8c11000 {
605*724ba675SRob Herring			compatible = "arm,gic-400", "arm,cortex-a7-gic";
606*724ba675SRob Herring			#interrupt-cells = <3>;
607*724ba675SRob Herring			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
608*724ba675SRob Herring			interrupt-controller;
609*724ba675SRob Herring			reg = <0xe8c11000 0x1000>,
610*724ba675SRob Herring			      <0xe8c12000 0x2000>,
611*724ba675SRob Herring			      <0xe8c14000 0x2000>,
612*724ba675SRob Herring			      <0xe8c16000 0x2000>;
613*724ba675SRob Herring		};
614*724ba675SRob Herring	};
615*724ba675SRob Herring};
616