1*38a9dac2SMax Shevchenko// SPDX-License-Identifier: GPL-2.0 2*38a9dac2SMax Shevchenko/* 3*38a9dac2SMax Shevchenko * Copyright (c) 2025 Max Shevchenko <wctrl@proton.me> 4*38a9dac2SMax Shevchenko */ 5*38a9dac2SMax Shevchenko 6*38a9dac2SMax Shevchenko#include <dt-bindings/interrupt-controller/irq.h> 7*38a9dac2SMax Shevchenko#include <dt-bindings/interrupt-controller/arm-gic.h> 8*38a9dac2SMax Shevchenko 9*38a9dac2SMax Shevchenko/ { 10*38a9dac2SMax Shevchenko #address-cells = <1>; 11*38a9dac2SMax Shevchenko #size-cells = <1>; 12*38a9dac2SMax Shevchenko interrupt-parent = <&sysirq>; 13*38a9dac2SMax Shevchenko 14*38a9dac2SMax Shevchenko cpus { 15*38a9dac2SMax Shevchenko #address-cells = <1>; 16*38a9dac2SMax Shevchenko #size-cells = <0>; 17*38a9dac2SMax Shevchenko enable-method = "mediatek,mt6589-smp"; 18*38a9dac2SMax Shevchenko 19*38a9dac2SMax Shevchenko cpu@0 { 20*38a9dac2SMax Shevchenko device_type = "cpu"; 21*38a9dac2SMax Shevchenko compatible = "arm,cortex-a7"; 22*38a9dac2SMax Shevchenko reg = <0x0>; 23*38a9dac2SMax Shevchenko }; 24*38a9dac2SMax Shevchenko cpu@1 { 25*38a9dac2SMax Shevchenko device_type = "cpu"; 26*38a9dac2SMax Shevchenko compatible = "arm,cortex-a7"; 27*38a9dac2SMax Shevchenko reg = <0x1>; 28*38a9dac2SMax Shevchenko }; 29*38a9dac2SMax Shevchenko }; 30*38a9dac2SMax Shevchenko 31*38a9dac2SMax Shevchenko uart_clk: dummy26m { 32*38a9dac2SMax Shevchenko compatible = "fixed-clock"; 33*38a9dac2SMax Shevchenko clock-frequency = <26000000>; 34*38a9dac2SMax Shevchenko #clock-cells = <0>; 35*38a9dac2SMax Shevchenko }; 36*38a9dac2SMax Shevchenko 37*38a9dac2SMax Shevchenko system_clk: dummy13m { 38*38a9dac2SMax Shevchenko compatible = "fixed-clock"; 39*38a9dac2SMax Shevchenko clock-frequency = <13000000>; 40*38a9dac2SMax Shevchenko #clock-cells = <0>; 41*38a9dac2SMax Shevchenko }; 42*38a9dac2SMax Shevchenko 43*38a9dac2SMax Shevchenko rtc_clk: dummy32k { 44*38a9dac2SMax Shevchenko compatible = "fixed-clock"; 45*38a9dac2SMax Shevchenko clock-frequency = <32000>; 46*38a9dac2SMax Shevchenko #clock-cells = <0>; 47*38a9dac2SMax Shevchenko }; 48*38a9dac2SMax Shevchenko 49*38a9dac2SMax Shevchenko soc { 50*38a9dac2SMax Shevchenko #address-cells = <1>; 51*38a9dac2SMax Shevchenko #size-cells = <1>; 52*38a9dac2SMax Shevchenko compatible = "simple-bus"; 53*38a9dac2SMax Shevchenko ranges; 54*38a9dac2SMax Shevchenko 55*38a9dac2SMax Shevchenko watchdog: watchdog@10007000 { 56*38a9dac2SMax Shevchenko compatible = "mediatek,mt6572-wdt", "mediatek,mt6589-wdt"; 57*38a9dac2SMax Shevchenko reg = <0x10007000 0x100>; 58*38a9dac2SMax Shevchenko interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 59*38a9dac2SMax Shevchenko timeout-sec = <15>; 60*38a9dac2SMax Shevchenko #reset-cells = <1>; 61*38a9dac2SMax Shevchenko }; 62*38a9dac2SMax Shevchenko 63*38a9dac2SMax Shevchenko timer: timer@10008000 { 64*38a9dac2SMax Shevchenko compatible = "mediatek,mt6572-timer", "mediatek,mt6577-timer"; 65*38a9dac2SMax Shevchenko reg = <0x10008000 0x80>; 66*38a9dac2SMax Shevchenko interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 67*38a9dac2SMax Shevchenko clocks = <&system_clk>, <&rtc_clk>; 68*38a9dac2SMax Shevchenko clock-names = "system-clk", "rtc-clk"; 69*38a9dac2SMax Shevchenko }; 70*38a9dac2SMax Shevchenko 71*38a9dac2SMax Shevchenko sysirq: interrupt-controller@10200100 { 72*38a9dac2SMax Shevchenko compatible = "mediatek,mt6572-sysirq", "mediatek,mt6577-sysirq"; 73*38a9dac2SMax Shevchenko reg = <0x10200100 0x1c>; 74*38a9dac2SMax Shevchenko interrupt-controller; 75*38a9dac2SMax Shevchenko #interrupt-cells = <3>; 76*38a9dac2SMax Shevchenko interrupt-parent = <&gic>; 77*38a9dac2SMax Shevchenko }; 78*38a9dac2SMax Shevchenko 79*38a9dac2SMax Shevchenko gic: interrupt-controller@10211000 { 80*38a9dac2SMax Shevchenko compatible = "arm,cortex-a7-gic"; 81*38a9dac2SMax Shevchenko reg = <0x10211000 0x1000>, 82*38a9dac2SMax Shevchenko <0x10212000 0x2000>, 83*38a9dac2SMax Shevchenko <0x10214000 0x2000>, 84*38a9dac2SMax Shevchenko <0x10216000 0x2000>; 85*38a9dac2SMax Shevchenko interrupt-controller; 86*38a9dac2SMax Shevchenko #interrupt-cells = <3>; 87*38a9dac2SMax Shevchenko interrupt-parent = <&gic>; 88*38a9dac2SMax Shevchenko }; 89*38a9dac2SMax Shevchenko 90*38a9dac2SMax Shevchenko uart0: serial@11005000 { 91*38a9dac2SMax Shevchenko compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart"; 92*38a9dac2SMax Shevchenko reg = <0x11005000 0x400>; 93*38a9dac2SMax Shevchenko interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 94*38a9dac2SMax Shevchenko clocks = <&uart_clk>; 95*38a9dac2SMax Shevchenko clock-names = "baud"; 96*38a9dac2SMax Shevchenko status = "disabled"; 97*38a9dac2SMax Shevchenko }; 98*38a9dac2SMax Shevchenko 99*38a9dac2SMax Shevchenko uart1: serial@11006000 { 100*38a9dac2SMax Shevchenko compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart"; 101*38a9dac2SMax Shevchenko reg = <0x11006000 0x400>; 102*38a9dac2SMax Shevchenko interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; 103*38a9dac2SMax Shevchenko clocks = <&uart_clk>; 104*38a9dac2SMax Shevchenko clock-names = "baud"; 105*38a9dac2SMax Shevchenko status = "disabled"; 106*38a9dac2SMax Shevchenko }; 107*38a9dac2SMax Shevchenko }; 108*38a9dac2SMax Shevchenko}; 109