1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/ { 3*724ba675SRob Herring mbus@f1000000 { 4*724ba675SRob Herring pciec: pcie@82000000 { 5*724ba675SRob Herring compatible = "marvell,kirkwood-pcie"; 6*724ba675SRob Herring status = "disabled"; 7*724ba675SRob Herring device_type = "pci"; 8*724ba675SRob Herring 9*724ba675SRob Herring #address-cells = <3>; 10*724ba675SRob Herring #size-cells = <2>; 11*724ba675SRob Herring 12*724ba675SRob Herring bus-range = <0x00 0xff>; 13*724ba675SRob Herring 14*724ba675SRob Herring ranges = 15*724ba675SRob Herring <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16*724ba675SRob Herring 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17*724ba675SRob Herring 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18*724ba675SRob Herring 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19*724ba675SRob Herring 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20*724ba675SRob Herring 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21*724ba675SRob Herring 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 22*724ba675SRob Herring 23*724ba675SRob Herring pcie0: pcie@1,0 { 24*724ba675SRob Herring device_type = "pci"; 25*724ba675SRob Herring assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 26*724ba675SRob Herring reg = <0x0800 0 0 0 0>; 27*724ba675SRob Herring #address-cells = <3>; 28*724ba675SRob Herring #size-cells = <2>; 29*724ba675SRob Herring #interrupt-cells = <1>; 30*724ba675SRob Herring ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 31*724ba675SRob Herring 0x81000000 0 0 0x81000000 0x1 0 1 0>; 32*724ba675SRob Herring bus-range = <0x00 0xff>; 33*724ba675SRob Herring interrupt-names = "intx", "error"; 34*724ba675SRob Herring interrupts = <9>, <44>; 35*724ba675SRob Herring interrupt-map-mask = <0 0 0 7>; 36*724ba675SRob Herring interrupt-map = <0 0 0 1 &pcie0_intc 0>, 37*724ba675SRob Herring <0 0 0 2 &pcie0_intc 1>, 38*724ba675SRob Herring <0 0 0 3 &pcie0_intc 2>, 39*724ba675SRob Herring <0 0 0 4 &pcie0_intc 3>; 40*724ba675SRob Herring marvell,pcie-port = <0>; 41*724ba675SRob Herring marvell,pcie-lane = <0>; 42*724ba675SRob Herring clocks = <&gate_clk 2>; 43*724ba675SRob Herring status = "disabled"; 44*724ba675SRob Herring 45*724ba675SRob Herring pcie0_intc: interrupt-controller { 46*724ba675SRob Herring interrupt-controller; 47*724ba675SRob Herring #interrupt-cells = <1>; 48*724ba675SRob Herring }; 49*724ba675SRob Herring }; 50*724ba675SRob Herring 51*724ba675SRob Herring pcie1: pcie@2,0 { 52*724ba675SRob Herring device_type = "pci"; 53*724ba675SRob Herring assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; 54*724ba675SRob Herring reg = <0x1000 0 0 0 0>; 55*724ba675SRob Herring #address-cells = <3>; 56*724ba675SRob Herring #size-cells = <2>; 57*724ba675SRob Herring #interrupt-cells = <1>; 58*724ba675SRob Herring ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 59*724ba675SRob Herring 0x81000000 0 0 0x81000000 0x2 0 1 0>; 60*724ba675SRob Herring bus-range = <0x00 0xff>; 61*724ba675SRob Herring interrupt-names = "intx", "error"; 62*724ba675SRob Herring interrupts = <10>, <45>; 63*724ba675SRob Herring interrupt-map-mask = <0 0 0 7>; 64*724ba675SRob Herring interrupt-map = <0 0 0 1 &pcie1_intc 0>, 65*724ba675SRob Herring <0 0 0 2 &pcie1_intc 1>, 66*724ba675SRob Herring <0 0 0 3 &pcie1_intc 2>, 67*724ba675SRob Herring <0 0 0 4 &pcie1_intc 3>; 68*724ba675SRob Herring marvell,pcie-port = <1>; 69*724ba675SRob Herring marvell,pcie-lane = <0>; 70*724ba675SRob Herring clocks = <&gate_clk 18>; 71*724ba675SRob Herring status = "disabled"; 72*724ba675SRob Herring 73*724ba675SRob Herring pcie1_intc: interrupt-controller { 74*724ba675SRob Herring interrupt-controller; 75*724ba675SRob Herring #interrupt-cells = <1>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring }; 78*724ba675SRob Herring }; 79*724ba675SRob Herring }; 80*724ba675SRob Herring ocp@f1000000 { 81*724ba675SRob Herring 82*724ba675SRob Herring pinctrl: pin-controller@10000 { 83*724ba675SRob Herring compatible = "marvell,88f6282-pinctrl"; 84*724ba675SRob Herring 85*724ba675SRob Herring pmx_sata0: pmx-sata0 { 86*724ba675SRob Herring marvell,pins = "mpp5", "mpp21", "mpp23"; 87*724ba675SRob Herring marvell,function = "sata0"; 88*724ba675SRob Herring }; 89*724ba675SRob Herring pmx_sata1: pmx-sata1 { 90*724ba675SRob Herring marvell,pins = "mpp4", "mpp20", "mpp22"; 91*724ba675SRob Herring marvell,function = "sata1"; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring /* 95*724ba675SRob Herring * Default I2C1 pinctrl setting on mpp36/mpp37, 96*724ba675SRob Herring * overwrite marvell,pins on board level if required. 97*724ba675SRob Herring */ 98*724ba675SRob Herring pmx_twsi1: pmx-twsi1 { 99*724ba675SRob Herring marvell,pins = "mpp36", "mpp37"; 100*724ba675SRob Herring marvell,function = "twsi1"; 101*724ba675SRob Herring }; 102*724ba675SRob Herring 103*724ba675SRob Herring pmx_sdio: pmx-sdio { 104*724ba675SRob Herring marvell,pins = "mpp12", "mpp13", "mpp14", 105*724ba675SRob Herring "mpp15", "mpp16", "mpp17"; 106*724ba675SRob Herring marvell,function = "sdio"; 107*724ba675SRob Herring }; 108*724ba675SRob Herring }; 109*724ba675SRob Herring 110*724ba675SRob Herring thermal: thermal@10078 { 111*724ba675SRob Herring compatible = "marvell,kirkwood-thermal"; 112*724ba675SRob Herring reg = <0x10078 0x4>; 113*724ba675SRob Herring status = "okay"; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring rtc: rtc@10300 { 117*724ba675SRob Herring compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 118*724ba675SRob Herring reg = <0x10300 0x20>; 119*724ba675SRob Herring interrupts = <53>; 120*724ba675SRob Herring clocks = <&gate_clk 7>; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring i2c1: i2c@11100 { 124*724ba675SRob Herring compatible = "marvell,mv64xxx-i2c"; 125*724ba675SRob Herring reg = <0x11100 0x20>; 126*724ba675SRob Herring #address-cells = <1>; 127*724ba675SRob Herring #size-cells = <0>; 128*724ba675SRob Herring interrupts = <32>; 129*724ba675SRob Herring clock-frequency = <100000>; 130*724ba675SRob Herring clocks = <&gate_clk 7>; 131*724ba675SRob Herring pinctrl-0 = <&pmx_twsi1>; 132*724ba675SRob Herring pinctrl-names = "default"; 133*724ba675SRob Herring status = "disabled"; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring sata: sata@80000 { 137*724ba675SRob Herring compatible = "marvell,orion-sata"; 138*724ba675SRob Herring reg = <0x80000 0x5000>; 139*724ba675SRob Herring interrupts = <21>; 140*724ba675SRob Herring clocks = <&gate_clk 14>, <&gate_clk 15>; 141*724ba675SRob Herring clock-names = "0", "1"; 142*724ba675SRob Herring phys = <&sata_phy0>, <&sata_phy1>; 143*724ba675SRob Herring phy-names = "port0", "port1"; 144*724ba675SRob Herring status = "disabled"; 145*724ba675SRob Herring }; 146*724ba675SRob Herring 147*724ba675SRob Herring sdio: mvsdio@90000 { 148*724ba675SRob Herring compatible = "marvell,orion-sdio"; 149*724ba675SRob Herring reg = <0x90000 0x200>; 150*724ba675SRob Herring interrupts = <28>; 151*724ba675SRob Herring clocks = <&gate_clk 4>; 152*724ba675SRob Herring pinctrl-0 = <&pmx_sdio>; 153*724ba675SRob Herring pinctrl-names = "default"; 154*724ba675SRob Herring bus-width = <4>; 155*724ba675SRob Herring cap-sdio-irq; 156*724ba675SRob Herring cap-sd-highspeed; 157*724ba675SRob Herring cap-mmc-highspeed; 158*724ba675SRob Herring status = "disabled"; 159*724ba675SRob Herring }; 160*724ba675SRob Herring }; 161*724ba675SRob Herring}; 162