1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree file for Marvell Armada XP Matrix board 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013 Marvell 6*724ba675SRob Herring * 7*724ba675SRob Herring * Lior Amsalem <alior@marvell.com> 8*724ba675SRob Herring */ 9*724ba675SRob Herring 10*724ba675SRob Herring/dts-v1/; 11*724ba675SRob Herring#include "armada-xp-mv78460.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "Marvell Armada XP Matrix Board"; 15*724ba675SRob Herring compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 16*724ba675SRob Herring 17*724ba675SRob Herring chosen { 18*724ba675SRob Herring stdout-path = "serial0:115200n8"; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring memory@0 { 22*724ba675SRob Herring device_type = "memory"; 23*724ba675SRob Herring /* 24*724ba675SRob Herring * This board has 4 GB of RAM, but the last 256 MB of 25*724ba675SRob Herring * RAM are not usable due to the overlap with the MBus 26*724ba675SRob Herring * Window address range 27*724ba675SRob Herring */ 28*724ba675SRob Herring reg = <0 0x00000000 0 0xf0000000>; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring soc { 32*724ba675SRob Herring ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 33*724ba675SRob Herring MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 34*724ba675SRob Herring MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 35*724ba675SRob Herring MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; 36*724ba675SRob Herring 37*724ba675SRob Herring internal-regs { 38*724ba675SRob Herring serial@12000 { 39*724ba675SRob Herring status = "okay"; 40*724ba675SRob Herring }; 41*724ba675SRob Herring serial@12100 { 42*724ba675SRob Herring status = "okay"; 43*724ba675SRob Herring }; 44*724ba675SRob Herring serial@12200 { 45*724ba675SRob Herring status = "okay"; 46*724ba675SRob Herring }; 47*724ba675SRob Herring serial@12300 { 48*724ba675SRob Herring status = "okay"; 49*724ba675SRob Herring }; 50*724ba675SRob Herring 51*724ba675SRob Herring sata@a0000 { 52*724ba675SRob Herring nr-ports = <2>; 53*724ba675SRob Herring status = "okay"; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring ethernet@30000 { 57*724ba675SRob Herring status = "okay"; 58*724ba675SRob Herring phy-mode = "sgmii"; 59*724ba675SRob Herring fixed-link { 60*724ba675SRob Herring speed = <1000>; 61*724ba675SRob Herring full-duplex; 62*724ba675SRob Herring }; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring usb@50000 { 66*724ba675SRob Herring status = "okay"; 67*724ba675SRob Herring }; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring}; 71*724ba675SRob Herring 72*724ba675SRob Herring&pciec { 73*724ba675SRob Herring status = "okay"; 74*724ba675SRob Herring 75*724ba675SRob Herring pcie@1,0 { 76*724ba675SRob Herring /* Port 0, Lane 0 */ 77*724ba675SRob Herring status = "okay"; 78*724ba675SRob Herring }; 79*724ba675SRob Herring}; 80