xref: /linux/scripts/dtc/include-prefixes/arm/marvell/armada-388-clearfog.dts (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2724ba675SRob Herring/*
3724ba675SRob Herring * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4724ba675SRob Herring *
5724ba675SRob Herring *  Copyright (C) 2015 Russell King
6724ba675SRob Herring */
7724ba675SRob Herring
8724ba675SRob Herring/dts-v1/;
9724ba675SRob Herring#include "armada-388-clearfog.dtsi"
10724ba675SRob Herring
11724ba675SRob Herring/ {
12724ba675SRob Herring	model = "SolidRun Clearfog A1";
13*7268e0ddSJosua Mayer	compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
14*7268e0ddSJosua Mayer		     "marvell,armada388", "marvell,armada385",
15*7268e0ddSJosua Mayer		     "marvell,armada380";
16724ba675SRob Herring
17724ba675SRob Herring	soc {
18724ba675SRob Herring		internal-regs {
19724ba675SRob Herring			usb3@f0000 {
20724ba675SRob Herring				/* CON2, nearest CPU, USB2 only. */
21724ba675SRob Herring				status = "okay";
22724ba675SRob Herring			};
23724ba675SRob Herring		};
24724ba675SRob Herring
25724ba675SRob Herring		pcie {
26724ba675SRob Herring			pcie@3,0 {
27724ba675SRob Herring				/* Port 2, Lane 0. CON2, nearest CPU. */
28724ba675SRob Herring				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
29724ba675SRob Herring				status = "okay";
30724ba675SRob Herring			};
31724ba675SRob Herring		};
32724ba675SRob Herring	};
33724ba675SRob Herring
34724ba675SRob Herring	gpio-keys {
35724ba675SRob Herring		compatible = "gpio-keys";
36724ba675SRob Herring		pinctrl-0 = <&rear_button_pins>;
37724ba675SRob Herring		pinctrl-names = "default";
38724ba675SRob Herring
39724ba675SRob Herring		button-0 {
40724ba675SRob Herring			/* The rear SW3 button */
41724ba675SRob Herring			label = "Rear Button";
42724ba675SRob Herring			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
43724ba675SRob Herring			linux,can-disable;
44724ba675SRob Herring			linux,code = <BTN_0>;
45724ba675SRob Herring		};
46724ba675SRob Herring	};
47724ba675SRob Herring};
48724ba675SRob Herring
49724ba675SRob Herring&eth1 {
50724ba675SRob Herring	/* ethernet@30000 */
51724ba675SRob Herring	phy-mode = "1000base-x";
52724ba675SRob Herring
53724ba675SRob Herring	fixed-link {
54724ba675SRob Herring		speed = <1000>;
55724ba675SRob Herring		full-duplex;
56724ba675SRob Herring	};
57724ba675SRob Herring};
58724ba675SRob Herring
59724ba675SRob Herring&expander0 {
60724ba675SRob Herring	/*
61724ba675SRob Herring	 * PCA9655 GPIO expander:
62724ba675SRob Herring	 *  0-CON3 CLKREQ#
63724ba675SRob Herring	 *  1-CON3 PERST#
64724ba675SRob Herring	 *  2-CON2 PERST#
65724ba675SRob Herring	 *  3-CON3 W_DISABLE
66724ba675SRob Herring	 *  4-CON2 CLKREQ#
67724ba675SRob Herring	 *  5-USB3 overcurrent
68724ba675SRob Herring	 *  6-USB3 power
69724ba675SRob Herring	 *  7-CON2 W_DISABLE
70724ba675SRob Herring	 *  8-JP4 P1
71724ba675SRob Herring	 *  9-JP4 P4
72724ba675SRob Herring	 * 10-JP4 P5
73724ba675SRob Herring	 * 11-m.2 DEVSLP
74724ba675SRob Herring	 * 12-SFP_LOS
75724ba675SRob Herring	 * 13-SFP_TX_FAULT
76724ba675SRob Herring	 * 14-SFP_TX_DISABLE
77724ba675SRob Herring	 * 15-SFP_MOD_DEF0
78724ba675SRob Herring	 */
79724ba675SRob Herring	pcie2-0-clkreq-hog {
80724ba675SRob Herring		gpio-hog;
81724ba675SRob Herring		gpios = <4 GPIO_ACTIVE_LOW>;
82724ba675SRob Herring		input;
83724ba675SRob Herring		line-name = "pcie2.0-clkreq";
84724ba675SRob Herring	};
85724ba675SRob Herring	pcie2-0-w-disable-hog {
86724ba675SRob Herring		gpio-hog;
87724ba675SRob Herring		gpios = <7 GPIO_ACTIVE_LOW>;
88724ba675SRob Herring		output-low;
89724ba675SRob Herring		line-name = "pcie2.0-w-disable";
90724ba675SRob Herring	};
91724ba675SRob Herring};
92724ba675SRob Herring
93724ba675SRob Herring&mdio {
94724ba675SRob Herring	status = "okay";
95724ba675SRob Herring
966e75ac5aSLinus Walleij	ethernet-switch@4 {
97724ba675SRob Herring		compatible = "marvell,mv88e6085";
98724ba675SRob Herring		reg = <4>;
99724ba675SRob Herring		pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
100724ba675SRob Herring		pinctrl-names = "default";
101724ba675SRob Herring
1026e75ac5aSLinus Walleij		ethernet-ports {
103724ba675SRob Herring			#address-cells = <1>;
104724ba675SRob Herring			#size-cells = <0>;
105724ba675SRob Herring
1066e75ac5aSLinus Walleij			ethernet-port@0 {
107724ba675SRob Herring				reg = <0>;
108724ba675SRob Herring				label = "lan5";
109724ba675SRob Herring			};
110724ba675SRob Herring
1116e75ac5aSLinus Walleij			ethernet-port@1 {
112724ba675SRob Herring				reg = <1>;
113724ba675SRob Herring				label = "lan4";
114724ba675SRob Herring			};
115724ba675SRob Herring
1166e75ac5aSLinus Walleij			ethernet-port@2 {
117724ba675SRob Herring				reg = <2>;
118724ba675SRob Herring				label = "lan3";
119724ba675SRob Herring			};
120724ba675SRob Herring
1216e75ac5aSLinus Walleij			ethernet-port@3 {
122724ba675SRob Herring				reg = <3>;
123724ba675SRob Herring				label = "lan2";
124724ba675SRob Herring			};
125724ba675SRob Herring
1266e75ac5aSLinus Walleij			ethernet-port@4 {
127724ba675SRob Herring				reg = <4>;
128724ba675SRob Herring				label = "lan1";
129724ba675SRob Herring			};
130724ba675SRob Herring
1316e75ac5aSLinus Walleij			ethernet-port@5 {
132724ba675SRob Herring				reg = <5>;
133724ba675SRob Herring				ethernet = <&eth1>;
134724ba675SRob Herring				phy-mode = "1000base-x";
135724ba675SRob Herring
136724ba675SRob Herring				fixed-link {
137724ba675SRob Herring					speed = <1000>;
138724ba675SRob Herring					full-duplex;
139724ba675SRob Herring				};
140724ba675SRob Herring			};
141724ba675SRob Herring
1426e75ac5aSLinus Walleij			ethernet-port@6 {
143724ba675SRob Herring				/* 88E1512 external phy */
144724ba675SRob Herring				reg = <6>;
145724ba675SRob Herring				label = "lan6";
146724ba675SRob Herring				phy-mode = "rgmii-id";
147724ba675SRob Herring
148724ba675SRob Herring				fixed-link {
149724ba675SRob Herring					speed = <1000>;
150724ba675SRob Herring					full-duplex;
151724ba675SRob Herring				};
152724ba675SRob Herring			};
153724ba675SRob Herring		};
154724ba675SRob Herring	};
155724ba675SRob Herring};
156724ba675SRob Herring
157724ba675SRob Herring&pinctrl {
158724ba675SRob Herring	clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
159724ba675SRob Herring		marvell,pins = "mpp46";
160724ba675SRob Herring		marvell,function = "ref";
161724ba675SRob Herring	};
162724ba675SRob Herring	clearfog_dsa0_pins: clearfog-dsa0-pins {
163724ba675SRob Herring		marvell,pins = "mpp23", "mpp41";
164724ba675SRob Herring		marvell,function = "gpio";
165724ba675SRob Herring	};
166724ba675SRob Herring	clearfog_spi1_cs_pins: spi1-cs-pins {
167724ba675SRob Herring		marvell,pins = "mpp55";
168724ba675SRob Herring		marvell,function = "spi1";
169724ba675SRob Herring	};
170724ba675SRob Herring	rear_button_pins: rear-button-pins {
171724ba675SRob Herring		marvell,pins = "mpp34";
172724ba675SRob Herring		marvell,function = "gpio";
173724ba675SRob Herring	};
174724ba675SRob Herring};
175724ba675SRob Herring
176724ba675SRob Herring&spi1 {
177724ba675SRob Herring	/*
178724ba675SRob Herring	 * Add SPI CS pins for clearfog:
179724ba675SRob Herring	 * CS0: W25Q32
180724ba675SRob Herring	 * CS1:
181724ba675SRob Herring	 * CS2: mikrobus
182724ba675SRob Herring	 */
183724ba675SRob Herring	pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
184724ba675SRob Herring};
185