xref: /linux/scripts/dtc/include-prefixes/arm/marvell/armada-385-turris-omnia.dts (revision cfa65ef7c84adafcbd1f9c7ba349812e1692d0a2) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	aliases {
27		ethernet0 = &eth0;
28		ethernet1 = &eth1;
29		ethernet2 = &eth2;
30	};
31
32	memory {
33		device_type = "memory";
34		reg = <0x00000000 0x40000000>; /* 1024 MB */
35	};
36
37	soc {
38		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
39			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
40			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
41			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
42			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
43
44		internal-regs {
45
46			/* USB part of the PCIe2/USB 2.0 port */
47			usb@58000 {
48				status = "okay";
49			};
50
51			sata@a8000 {
52				status = "okay";
53			};
54
55			sdhci@d8000 {
56				pinctrl-names = "default";
57				pinctrl-0 = <&sdhci_pins>;
58				status = "okay";
59
60				bus-width = <8>;
61				no-1-8-v;
62				non-removable;
63			};
64
65			usb3@f0000 {
66				status = "okay";
67			};
68
69			usb3@f8000 {
70				status = "okay";
71			};
72		};
73
74		pcie {
75			status = "okay";
76
77			pcie@1,0 {
78				/* Port 0, Lane 0 */
79				status = "okay";
80				slot-power-limit-milliwatt = <10000>;
81			};
82
83			pcie@2,0 {
84				/* Port 1, Lane 0 */
85				status = "okay";
86				slot-power-limit-milliwatt = <10000>;
87			};
88
89			pcie@3,0 {
90				/* Port 2, Lane 0 */
91				status = "okay";
92				slot-power-limit-milliwatt = <10000>;
93			};
94		};
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&sfp_i2c>;
100		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
101		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
102		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
103		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
105		maximum-power-milliwatt = <3000>;
106
107		/*
108		 * For now this has to be enabled at boot time by U-Boot when
109		 * a SFP module is present. Read more in the comment in the
110		 * eth2 node below.
111		 */
112		status = "disabled";
113	};
114
115	sound {
116		compatible = "simple-audio-card";
117		simple-audio-card,name = "SPDIF";
118		simple-audio-card,format = "i2s";
119
120		simple-audio-card,cpu {
121			sound-dai = <&audio_controller 1>;
122		};
123
124		simple-audio-card,codec {
125			sound-dai = <&spdif_out>;
126		};
127	};
128
129	spdif_out: spdif-out {
130		#sound-dai-cells = <0>;
131		compatible = "linux,spdif-dit";
132	};
133};
134
135&audio_controller {
136	/* Pin header U16, GPIO51 in SPDIFO mode */
137	pinctrl-0 = <&spdif_pins>;
138	pinctrl-names = "default";
139	spdif-mode;
140	status = "okay";
141};
142
143&bm {
144	status = "okay";
145};
146
147&bm_bppi {
148	status = "okay";
149};
150
151/* Connected to 88E6176 switch, port 6 */
152&eth0 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&ge0_rgmii_pins>;
155	status = "okay";
156	phy-mode = "rgmii";
157	buffer-manager = <&bm>;
158	bm,pool-long = <0>;
159	bm,pool-short = <3>;
160
161	fixed-link {
162		speed = <1000>;
163		full-duplex;
164	};
165};
166
167/* Connected to 88E6176 switch, port 5 */
168&eth1 {
169	pinctrl-names = "default";
170	pinctrl-0 = <&ge1_rgmii_pins>;
171	status = "okay";
172	phy-mode = "rgmii";
173	buffer-manager = <&bm>;
174	bm,pool-long = <1>;
175	bm,pool-short = <3>;
176
177	fixed-link {
178		speed = <1000>;
179		full-duplex;
180	};
181};
182
183/* WAN port */
184&eth2 {
185	/*
186	 * eth2 is connected via a multiplexor to both the SFP cage and to
187	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
188	 * a SFP module is present, as determined by the mode-def0 GPIO.
189	 *
190	 * Until kernel supports this configuration properly, in case SFP module
191	 * is present, U-Boot has to enable the sfp node above, remove phy
192	 * handle and add managed = "in-band-status" property.
193	 */
194	status = "okay";
195	phy-mode = "sgmii";
196	phy-handle = <&phy1>;
197	phys = <&comphy5 2>;
198	sfp = <&sfp>;
199	buffer-manager = <&bm>;
200	bm,pool-long = <2>;
201	bm,pool-short = <3>;
202	label = "wan";
203};
204
205&i2c0 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&i2c0_pins>;
208	status = "okay";
209
210	i2cmux@70 {
211		compatible = "nxp,pca9547";
212		#address-cells = <1>;
213		#size-cells = <0>;
214		reg = <0x70>;
215
216		i2c@0 {
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0>;
220
221			mcu: system-controller@2a {
222				compatible = "cznic,turris-omnia-mcu";
223				reg = <0x2a>;
224
225				pinctrl-names = "default";
226				pinctrl-0 = <&mcu_pins>;
227
228				interrupt-parent = <&gpio1>;
229				interrupts = <11 IRQ_TYPE_NONE>;
230
231				gpio-controller;
232				#gpio-cells = <3>;
233
234				interrupt-controller;
235				#interrupt-cells = <2>;
236			};
237
238			led-controller@2b {
239				compatible = "cznic,turris-omnia-leds";
240				reg = <0x2b>;
241				#address-cells = <1>;
242				#size-cells = <0>;
243				status = "okay";
244
245				/*
246				 * LEDs are controlled by MCU (STM32F0) at
247				 * address 0x2b.
248				 *
249				 * LED functions are not stable yet:
250				 * - there are 3 LEDs connected via MCU to PCIe
251				 *   ports. One of these ports supports mSATA.
252				 *   There is no mSATA nor PCIe function.
253				 *   For now we use LED_FUNCTION_WLAN, since
254				 *   in most cases users have wifi cards in
255				 *   these slots
256				 * - there are 2 LEDs dedicated for user: A and
257				 *   B. Again there is no such function defined.
258				 *   For now we use LED_FUNCTION_INDICATOR
259				 */
260
261				multi-led@0 {
262					reg = <0x0>;
263					color = <LED_COLOR_ID_RGB>;
264					function = LED_FUNCTION_INDICATOR;
265					function-enumerator = <2>;
266				};
267
268				multi-led@1 {
269					reg = <0x1>;
270					color = <LED_COLOR_ID_RGB>;
271					function = LED_FUNCTION_INDICATOR;
272					function-enumerator = <1>;
273				};
274
275				multi-led@2 {
276					reg = <0x2>;
277					color = <LED_COLOR_ID_RGB>;
278					function = LED_FUNCTION_WLAN;
279					function-enumerator = <3>;
280				};
281
282				multi-led@3 {
283					reg = <0x3>;
284					color = <LED_COLOR_ID_RGB>;
285					function = LED_FUNCTION_WLAN;
286					function-enumerator = <2>;
287				};
288
289				multi-led@4 {
290					reg = <0x4>;
291					color = <LED_COLOR_ID_RGB>;
292					function = LED_FUNCTION_WLAN;
293					function-enumerator = <1>;
294				};
295
296				multi-led@5 {
297					reg = <0x5>;
298					color = <LED_COLOR_ID_RGB>;
299					function = LED_FUNCTION_WAN;
300				};
301
302				multi-led@6 {
303					reg = <0x6>;
304					color = <LED_COLOR_ID_RGB>;
305					function = LED_FUNCTION_LAN;
306					function-enumerator = <4>;
307				};
308
309				multi-led@7 {
310					reg = <0x7>;
311					color = <LED_COLOR_ID_RGB>;
312					function = LED_FUNCTION_LAN;
313					function-enumerator = <3>;
314				};
315
316				multi-led@8 {
317					reg = <0x8>;
318					color = <LED_COLOR_ID_RGB>;
319					function = LED_FUNCTION_LAN;
320					function-enumerator = <2>;
321				};
322
323				multi-led@9 {
324					reg = <0x9>;
325					color = <LED_COLOR_ID_RGB>;
326					function = LED_FUNCTION_LAN;
327					function-enumerator = <1>;
328				};
329
330				multi-led@a {
331					reg = <0xa>;
332					color = <LED_COLOR_ID_RGB>;
333					function = LED_FUNCTION_LAN;
334					function-enumerator = <0>;
335				};
336
337				multi-led@b {
338					reg = <0xb>;
339					color = <LED_COLOR_ID_RGB>;
340					function = LED_FUNCTION_POWER;
341				};
342			};
343
344			eeprom@54 {
345				compatible = "atmel,24c64";
346				reg = <0x54>;
347
348				/* The EEPROM contains data for bootloader.
349				 * Contents:
350				 * 	struct omnia_eeprom {
351				 * 		u32 magic; (=0x0341a034 in LE)
352				 *		u32 ramsize; (in GiB)
353				 * 		char regdomain[4];
354				 * 		u32 crc32;
355				 * 	};
356				 */
357			};
358		};
359
360		i2c@1 {
361			#address-cells = <1>;
362			#size-cells = <0>;
363			reg = <1>;
364
365			/* routed to PCIe0/mSATA connector (CN7A) */
366		};
367
368		i2c@2 {
369			#address-cells = <1>;
370			#size-cells = <0>;
371			reg = <2>;
372
373			/* routed to PCIe1/USB2 connector (CN61A) */
374		};
375
376		i2c@3 {
377			#address-cells = <1>;
378			#size-cells = <0>;
379			reg = <3>;
380
381			/* routed to PCIe2 connector (CN62A) */
382		};
383
384		sfp_i2c: i2c@4 {
385			#address-cells = <1>;
386			#size-cells = <0>;
387			reg = <4>;
388
389			/* routed to SFP+ */
390		};
391
392		i2c@5 {
393			#address-cells = <1>;
394			#size-cells = <0>;
395			reg = <5>;
396
397			/* ATSHA204A-MAHDA-T crypto module */
398			crypto@64 {
399				compatible = "atmel,atsha204a";
400				reg = <0x64>;
401			};
402		};
403
404		i2c@6 {
405			#address-cells = <1>;
406			#size-cells = <0>;
407			reg = <6>;
408
409			/* exposed on pin header */
410		};
411
412		i2c@7 {
413			#address-cells = <1>;
414			#size-cells = <0>;
415			reg = <7>;
416
417			pcawan: gpio@71 {
418				/*
419				 * GPIO expander for SFP+ signals and
420				 * and phy irq
421				 */
422				compatible = "nxp,pca9538";
423				reg = <0x71>;
424
425				pinctrl-names = "default";
426				pinctrl-0 = <&pcawan_pins>;
427
428				interrupt-parent = <&gpio1>;
429				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
430
431				gpio-controller;
432				#gpio-cells = <2>;
433			};
434		};
435	};
436};
437
438&mdio {
439	pinctrl-names = "default";
440	pinctrl-0 = <&mdio_pins>;
441	status = "okay";
442
443	phy1: ethernet-phy@1 {
444		compatible = "ethernet-phy-ieee802.3-c22";
445		reg = <1>;
446		marvell,reg-init = <3 18 0 0x4985>,
447				   <3 16 0xfff0 0x0001>;
448
449		/* irq is connected to &pcawan pin 7 */
450	};
451
452	/* Switch MV88E6176 at address 0x10 */
453	ethernet-switch@10 {
454		pinctrl-names = "default";
455		pinctrl-0 = <&swint_pins>;
456		compatible = "marvell,mv88e6085";
457
458		dsa,member = <0 0>;
459		reg = <0x10>;
460
461		interrupt-parent = <&gpio1>;
462		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
463
464		ethernet-ports {
465			#address-cells = <1>;
466			#size-cells = <0>;
467
468			ethernet-port@0 {
469				reg = <0>;
470				label = "lan0";
471			};
472
473			ethernet-port@1 {
474				reg = <1>;
475				label = "lan1";
476			};
477
478			ethernet-port@2 {
479				reg = <2>;
480				label = "lan2";
481			};
482
483			ethernet-port@3 {
484				reg = <3>;
485				label = "lan3";
486			};
487
488			ethernet-port@4 {
489				reg = <4>;
490				label = "lan4";
491			};
492
493			ethernet-port@5 {
494				reg = <5>;
495				ethernet = <&eth1>;
496				phy-mode = "rgmii-id";
497
498				fixed-link {
499					speed = <1000>;
500					full-duplex;
501				};
502			};
503
504			ethernet-port@6 {
505				reg = <6>;
506				ethernet = <&eth0>;
507				phy-mode = "rgmii-id";
508
509				fixed-link {
510					speed = <1000>;
511					full-duplex;
512				};
513			};
514		};
515	};
516};
517
518&pinctrl {
519	mcu_pins: mcu-pins {
520		marvell,pins = "mpp43";
521		marvell,function = "gpio";
522	};
523
524	pcawan_pins: pcawan-pins {
525		marvell,pins = "mpp46";
526		marvell,function = "gpio";
527	};
528
529	swint_pins: swint-pins {
530		marvell,pins = "mpp45";
531		marvell,function = "gpio";
532	};
533
534	spi0cs0_pins: spi0cs0-pins {
535		marvell,pins = "mpp25";
536		marvell,function = "spi0";
537	};
538
539	spi0cs2_pins: spi0cs2-pins {
540		marvell,pins = "mpp26";
541		marvell,function = "spi0";
542	};
543};
544
545&spi0 {
546	pinctrl-names = "default";
547	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
548	status = "okay";
549
550	flash@0 {
551		compatible = "spansion,s25fl164k", "jedec,spi-nor";
552		#address-cells = <1>;
553		#size-cells = <1>;
554		reg = <0>;
555		spi-max-frequency = <40000000>;
556
557		partitions {
558			compatible = "fixed-partitions";
559			#address-cells = <1>;
560			#size-cells = <1>;
561
562			partition@0 {
563				reg = <0x0 0x00100000>;
564				label = "U-Boot";
565			};
566
567			partition@100000 {
568				reg = <0x00100000 0x00700000>;
569				label = "Rescue system";
570			};
571		};
572	};
573
574	/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
575};
576
577&uart0 {
578	/* Pin header CN10 */
579	pinctrl-names = "default";
580	pinctrl-0 = <&uart0_pins>;
581	status = "okay";
582};
583
584&uart1 {
585	/* Pin header CN11 */
586	pinctrl-names = "default";
587	pinctrl-0 = <&uart1_pins>;
588	status = "okay";
589};
590