xref: /linux/scripts/dtc/include-prefixes/arm/marvell/armada-385-clearfog-gtr-l8.dts (revision 668445d1c7ca4c0e056fda85935d2c291b46ac10)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3#include "armada-385-clearfog-gtr.dtsi"
4
5/ {
6	model = "SolidRun Clearfog GTR L8";
7	compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
8		     "marvell,armada380";
9};
10
11&mdio {
12	switch0: ethernet-switch@4 {
13		compatible = "marvell,mv88e6190";
14		reg = <4>;
15		pinctrl-names = "default";
16		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
17		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
18
19		ethernet-ports {
20			#address-cells = <1>;
21			#size-cells = <0>;
22
23			ethernet-port@1 {
24				reg = <1>;
25				label = "lan8";
26				phy-handle = <&switch0phy0>;
27			};
28
29			ethernet-port@2 {
30				reg = <2>;
31				label = "lan7";
32				phy-handle = <&switch0phy1>;
33			};
34
35			ethernet-port@3 {
36				reg = <3>;
37				label = "lan6";
38				phy-handle = <&switch0phy2>;
39			};
40
41			ethernet-port@4 {
42				reg = <4>;
43				label = "lan5";
44				phy-handle = <&switch0phy3>;
45			};
46
47			ethernet-port@5 {
48				reg = <5>;
49				label = "lan4";
50				phy-handle = <&switch0phy4>;
51			};
52
53			ethernet-port@6 {
54				reg = <6>;
55				label = "lan3";
56				phy-handle = <&switch0phy5>;
57			};
58
59			ethernet-port@7 {
60				reg = <7>;
61				label = "lan2";
62				phy-handle = <&switch0phy6>;
63			};
64
65			ethernet-port@8 {
66				reg = <8>;
67				label = "lan1";
68				phy-handle = <&switch0phy7>;
69			};
70
71			ethernet-port@10 {
72				reg = <10>;
73				phy-mode = "2500base-x";
74
75				ethernet = <&eth1>;
76				fixed-link {
77					speed = <2500>;
78					full-duplex;
79				};
80			};
81
82		};
83
84		mdio {
85			#address-cells = <1>;
86			#size-cells = <0>;
87
88			switch0phy0: ethernet-phy@1 {
89				reg = <0x1>;
90			};
91
92			switch0phy1: ethernet-phy@2 {
93				reg = <0x2>;
94			};
95
96			switch0phy2: ethernet-phy@3 {
97				reg = <0x3>;
98			};
99
100			switch0phy3: ethernet-phy@4 {
101				reg = <0x4>;
102			};
103
104			switch0phy4: ethernet-phy@5 {
105				reg = <0x5>;
106			};
107
108			switch0phy5: ethernet-phy@6 {
109				reg = <0x6>;
110			};
111
112			switch0phy6: ethernet-phy@7 {
113				reg = <0x7>;
114			};
115
116			switch0phy7: ethernet-phy@8 {
117				reg = <0x8>;
118			};
119		};
120
121	};
122};
123