1724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2724ba675SRob Herring/* 3724ba675SRob Herring * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board. 4724ba675SRob Herring (x530/AT-GS980MX) 5724ba675SRob Herring * 6724ba675SRob Herring Copyright (C) 2020 Allied Telesis Labs 7724ba675SRob Herring */ 8724ba675SRob Herring 9724ba675SRob Herring/dts-v1/; 10724ba675SRob Herring#include "armada-385.dtsi" 11724ba675SRob Herring 12724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 13724ba675SRob Herring 14724ba675SRob Herring/ { 15724ba675SRob Herring model = "x530/AT-GS980MX"; 16724ba675SRob Herring compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; 17724ba675SRob Herring 18724ba675SRob Herring chosen { 19724ba675SRob Herring stdout-path = "serial1:115200n8"; 20724ba675SRob Herring }; 21724ba675SRob Herring 22724ba675SRob Herring memory { 23724ba675SRob Herring device_type = "memory"; 24724ba675SRob Herring reg = <0x00000000 0x40000000>; /* 1GB */ 25724ba675SRob Herring }; 26724ba675SRob Herring 27724ba675SRob Herring soc { 28724ba675SRob Herring ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 29724ba675SRob Herring MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000 30724ba675SRob Herring MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 31724ba675SRob Herring 32724ba675SRob Herring internal-regs { 33724ba675SRob Herring i2c0: i2c@11000 { 34724ba675SRob Herring pinctrl-names = "default"; 35724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 36724ba675SRob Herring status = "okay"; 37724ba675SRob Herring }; 38724ba675SRob Herring 39724ba675SRob Herring uart0: serial@12000 { 40724ba675SRob Herring pinctrl-names = "default"; 41724ba675SRob Herring pinctrl-0 = <&uart0_pins>; 42724ba675SRob Herring status = "okay"; 43724ba675SRob Herring }; 44724ba675SRob Herring }; 45724ba675SRob Herring }; 46*7852134dSChris Packham 47*7852134dSChris Packham led-7seg { 48*7852134dSChris Packham compatible = "gpio-7-segment"; 49*7852134dSChris Packham segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>, 50*7852134dSChris Packham <&led_7seg_gpio 1 GPIO_ACTIVE_LOW>, 51*7852134dSChris Packham <&led_7seg_gpio 2 GPIO_ACTIVE_LOW>, 52*7852134dSChris Packham <&led_7seg_gpio 3 GPIO_ACTIVE_LOW>, 53*7852134dSChris Packham <&led_7seg_gpio 4 GPIO_ACTIVE_LOW>, 54*7852134dSChris Packham <&led_7seg_gpio 5 GPIO_ACTIVE_LOW>, 55*7852134dSChris Packham <&led_7seg_gpio 6 GPIO_ACTIVE_LOW>; 56*7852134dSChris Packham }; 57724ba675SRob Herring}; 58724ba675SRob Herring 59724ba675SRob Herring&pciec { 60724ba675SRob Herring status = "okay"; 61724ba675SRob Herring}; 62724ba675SRob Herring 63724ba675SRob Herring&pcie1 { 64724ba675SRob Herring status = "okay"; 65724ba675SRob Herring reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 66724ba675SRob Herring reset-delay-us = <400000>; 67724ba675SRob Herring}; 68724ba675SRob Herring 69724ba675SRob Herring&pcie2 { 70724ba675SRob Herring status = "okay"; 71724ba675SRob Herring}; 72724ba675SRob Herring 73724ba675SRob Herring&devbus_cs1 { 74724ba675SRob Herring compatible = "marvell,mvebu-devbus"; 75724ba675SRob Herring status = "okay"; 76724ba675SRob Herring 77724ba675SRob Herring devbus,bus-width = <8>; 78724ba675SRob Herring devbus,turn-off-ps = <60000>; 79724ba675SRob Herring devbus,badr-skew-ps = <0>; 80724ba675SRob Herring devbus,acc-first-ps = <124000>; 81724ba675SRob Herring devbus,acc-next-ps = <248000>; 82724ba675SRob Herring devbus,rd-setup-ps = <0>; 83724ba675SRob Herring devbus,rd-hold-ps = <0>; 84724ba675SRob Herring 85724ba675SRob Herring /* Write parameters */ 86724ba675SRob Herring devbus,sync-enable = <0>; 87724ba675SRob Herring devbus,wr-high-ps = <60000>; 88724ba675SRob Herring devbus,wr-low-ps = <60000>; 89724ba675SRob Herring devbus,ale-wr-ps = <60000>; 90724ba675SRob Herring 91724ba675SRob Herring nvs@0 { 92724ba675SRob Herring status = "okay"; 93724ba675SRob Herring 94724ba675SRob Herring compatible = "mtd-ram"; 95724ba675SRob Herring reg = <0 0x00080000>; 96724ba675SRob Herring bank-width = <1>; 97724ba675SRob Herring label = "nvs"; 98724ba675SRob Herring }; 99724ba675SRob Herring}; 100724ba675SRob Herring 101724ba675SRob Herring&pinctrl { 102724ba675SRob Herring i2c0_gpio_pins: i2c-gpio-pins-0 { 103724ba675SRob Herring marvell,pins = "mpp2", "mpp3"; 104724ba675SRob Herring marvell,function = "gpio"; 105724ba675SRob Herring }; 106724ba675SRob Herring}; 107724ba675SRob Herring 108724ba675SRob Herring&i2c0 { 109724ba675SRob Herring clock-frequency = <100000>; 110724ba675SRob Herring status = "okay"; 111724ba675SRob Herring 112724ba675SRob Herring pinctrl-names = "default", "gpio"; 113724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 114724ba675SRob Herring pinctrl-1 = <&i2c0_gpio_pins>; 115724ba675SRob Herring scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 116724ba675SRob Herring sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 117724ba675SRob Herring 118724ba675SRob Herring i2c0mux: mux@71 { 119724ba675SRob Herring #address-cells = <1>; 120724ba675SRob Herring #size-cells = <0>; 121724ba675SRob Herring compatible = "nxp,pca9544"; 122724ba675SRob Herring reg = <0x71>; 123724ba675SRob Herring i2c-mux-idle-disconnect; 124724ba675SRob Herring 125724ba675SRob Herring i2c@0 { /* POE devices MUX */ 126724ba675SRob Herring #address-cells = <1>; 127724ba675SRob Herring #size-cells = <0>; 128724ba675SRob Herring reg = <0>; 129724ba675SRob Herring }; 130724ba675SRob Herring 131724ba675SRob Herring i2c@1 { 132724ba675SRob Herring #address-cells = <1>; 133724ba675SRob Herring #size-cells = <0>; 134724ba675SRob Herring reg = <1>; 135724ba675SRob Herring 136724ba675SRob Herring adt7476_2e: hwmon@2e { 137724ba675SRob Herring compatible = "adi,adt7476"; 138724ba675SRob Herring reg = <0x2e>; 139724ba675SRob Herring }; 140724ba675SRob Herring 141724ba675SRob Herring adt7476_2d: hwmon@2d { 142724ba675SRob Herring compatible = "adi,adt7476"; 143724ba675SRob Herring reg = <0x2d>; 144724ba675SRob Herring }; 145724ba675SRob Herring }; 146724ba675SRob Herring 147724ba675SRob Herring i2c@2 { 148724ba675SRob Herring #address-cells = <1>; 149724ba675SRob Herring #size-cells = <0>; 150724ba675SRob Herring reg = <2>; 151724ba675SRob Herring 152724ba675SRob Herring rtc@68 { 153724ba675SRob Herring compatible = "dallas,ds1340"; 154724ba675SRob Herring reg = <0x68>; 155724ba675SRob Herring }; 156724ba675SRob Herring }; 157724ba675SRob Herring 158724ba675SRob Herring i2c@3 { 159724ba675SRob Herring #address-cells = <1>; 160724ba675SRob Herring #size-cells = <0>; 161724ba675SRob Herring reg = <3>; 162724ba675SRob Herring 163*7852134dSChris Packham led_7seg_gpio: gpio@20 { 164724ba675SRob Herring compatible = "nxp,pca9554"; 165724ba675SRob Herring gpio-controller; 166724ba675SRob Herring #gpio-cells = <2>; 167724ba675SRob Herring reg = <0x20>; 168724ba675SRob Herring }; 169724ba675SRob Herring }; 170724ba675SRob Herring }; 171724ba675SRob Herring}; 172724ba675SRob Herring 173724ba675SRob Herring&usb0 { 174724ba675SRob Herring status = "okay"; 175724ba675SRob Herring}; 176724ba675SRob Herring 177724ba675SRob Herring&spi1 { 178724ba675SRob Herring pinctrl-names = "default"; 179724ba675SRob Herring pinctrl-0 = <&spi1_pins>; 180724ba675SRob Herring status = "okay"; 181724ba675SRob Herring 182724ba675SRob Herring flash@1 { 183724ba675SRob Herring #address-cells = <1>; 184724ba675SRob Herring #size-cells = <1>; 185724ba675SRob Herring compatible = "jedec,spi-nor"; 186724ba675SRob Herring reg = <1>; /* Chip select 1 */ 187724ba675SRob Herring spi-max-frequency = <54000000>; 188724ba675SRob Herring 189724ba675SRob Herring partitions { 190724ba675SRob Herring compatible = "fixed-partitions"; 191724ba675SRob Herring #address-cells = <1>; 192724ba675SRob Herring #size-cells = <1>; 193724ba675SRob Herring partition@0 { 194724ba675SRob Herring reg = <0x00000000 0x00100000>; 195724ba675SRob Herring label = "u-boot"; 196724ba675SRob Herring }; 197724ba675SRob Herring partition@100000 { 198724ba675SRob Herring reg = <0x00100000 0x00040000>; 199724ba675SRob Herring label = "u-boot-env"; 200724ba675SRob Herring }; 201724ba675SRob Herring partition@140000 { 202724ba675SRob Herring reg = <0x00140000 0x00e80000>; 203724ba675SRob Herring label = "unused"; 204724ba675SRob Herring }; 205724ba675SRob Herring partition@fc0000 { 206724ba675SRob Herring reg = <0x00fc0000 0x00040000>; 207724ba675SRob Herring label = "idprom"; 208724ba675SRob Herring }; 209724ba675SRob Herring }; 210724ba675SRob Herring }; 211724ba675SRob Herring}; 212724ba675SRob Herring 213724ba675SRob Herring&nand_controller { 214724ba675SRob Herring status = "okay"; 215724ba675SRob Herring 216724ba675SRob Herring nand@0 { 217724ba675SRob Herring reg = <0>; 218724ba675SRob Herring label = "pxa3xx_nand-0"; 219724ba675SRob Herring nand-rb = <0>; 220724ba675SRob Herring nand-on-flash-bbt; 221724ba675SRob Herring nand-ecc-strength = <4>; 222724ba675SRob Herring nand-ecc-step-size = <512>; 223724ba675SRob Herring 224724ba675SRob Herring marvell,nand-enable-arbiter; 225724ba675SRob Herring 226724ba675SRob Herring partitions { 227724ba675SRob Herring compatible = "fixed-partitions"; 228724ba675SRob Herring #address-cells = <1>; 229724ba675SRob Herring #size-cells = <1>; 230724ba675SRob Herring partition@0 { 231724ba675SRob Herring reg = <0x00000000 0x0f000000>; 232724ba675SRob Herring label = "user"; 233724ba675SRob Herring }; 234724ba675SRob Herring partition@f000000 { 235724ba675SRob Herring /* Maximum mtdoops size is 8MB, so set to that. */ 236724ba675SRob Herring reg = <0x0f000000 0x00800000>; 237724ba675SRob Herring label = "errlog"; 238724ba675SRob Herring }; 239724ba675SRob Herring partition@f800000 { 240724ba675SRob Herring reg = <0x0f800000 0x00800000>; 241724ba675SRob Herring label = "nand-bbt"; 242724ba675SRob Herring }; 243724ba675SRob Herring }; 244724ba675SRob Herring }; 245724ba675SRob Herring}; 246724ba675SRob Herring 247