1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board. 4*724ba675SRob Herring (x530/AT-GS980MX) 5*724ba675SRob Herring * 6*724ba675SRob Herring Copyright (C) 2020 Allied Telesis Labs 7*724ba675SRob Herring */ 8*724ba675SRob Herring 9*724ba675SRob Herring/dts-v1/; 10*724ba675SRob Herring#include "armada-385.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 13*724ba675SRob Herring 14*724ba675SRob Herring/ { 15*724ba675SRob Herring model = "x530/AT-GS980MX"; 16*724ba675SRob Herring compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; 17*724ba675SRob Herring 18*724ba675SRob Herring chosen { 19*724ba675SRob Herring stdout-path = "serial1:115200n8"; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring memory { 23*724ba675SRob Herring device_type = "memory"; 24*724ba675SRob Herring reg = <0x00000000 0x40000000>; /* 1GB */ 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring soc { 28*724ba675SRob Herring ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 29*724ba675SRob Herring MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000 30*724ba675SRob Herring MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 31*724ba675SRob Herring 32*724ba675SRob Herring internal-regs { 33*724ba675SRob Herring i2c0: i2c@11000 { 34*724ba675SRob Herring pinctrl-names = "default"; 35*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring uart0: serial@12000 { 40*724ba675SRob Herring pinctrl-names = "default"; 41*724ba675SRob Herring pinctrl-0 = <&uart0_pins>; 42*724ba675SRob Herring status = "okay"; 43*724ba675SRob Herring }; 44*724ba675SRob Herring }; 45*724ba675SRob Herring }; 46*724ba675SRob Herring}; 47*724ba675SRob Herring 48*724ba675SRob Herring&pciec { 49*724ba675SRob Herring status = "okay"; 50*724ba675SRob Herring}; 51*724ba675SRob Herring 52*724ba675SRob Herring&pcie1 { 53*724ba675SRob Herring status = "okay"; 54*724ba675SRob Herring reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 55*724ba675SRob Herring reset-delay-us = <400000>; 56*724ba675SRob Herring}; 57*724ba675SRob Herring 58*724ba675SRob Herring&pcie2 { 59*724ba675SRob Herring status = "okay"; 60*724ba675SRob Herring}; 61*724ba675SRob Herring 62*724ba675SRob Herring&devbus_cs1 { 63*724ba675SRob Herring compatible = "marvell,mvebu-devbus"; 64*724ba675SRob Herring status = "okay"; 65*724ba675SRob Herring 66*724ba675SRob Herring devbus,bus-width = <8>; 67*724ba675SRob Herring devbus,turn-off-ps = <60000>; 68*724ba675SRob Herring devbus,badr-skew-ps = <0>; 69*724ba675SRob Herring devbus,acc-first-ps = <124000>; 70*724ba675SRob Herring devbus,acc-next-ps = <248000>; 71*724ba675SRob Herring devbus,rd-setup-ps = <0>; 72*724ba675SRob Herring devbus,rd-hold-ps = <0>; 73*724ba675SRob Herring 74*724ba675SRob Herring /* Write parameters */ 75*724ba675SRob Herring devbus,sync-enable = <0>; 76*724ba675SRob Herring devbus,wr-high-ps = <60000>; 77*724ba675SRob Herring devbus,wr-low-ps = <60000>; 78*724ba675SRob Herring devbus,ale-wr-ps = <60000>; 79*724ba675SRob Herring 80*724ba675SRob Herring nvs@0 { 81*724ba675SRob Herring status = "okay"; 82*724ba675SRob Herring 83*724ba675SRob Herring compatible = "mtd-ram"; 84*724ba675SRob Herring reg = <0 0x00080000>; 85*724ba675SRob Herring bank-width = <1>; 86*724ba675SRob Herring label = "nvs"; 87*724ba675SRob Herring }; 88*724ba675SRob Herring}; 89*724ba675SRob Herring 90*724ba675SRob Herring&pinctrl { 91*724ba675SRob Herring i2c0_gpio_pins: i2c-gpio-pins-0 { 92*724ba675SRob Herring marvell,pins = "mpp2", "mpp3"; 93*724ba675SRob Herring marvell,function = "gpio"; 94*724ba675SRob Herring }; 95*724ba675SRob Herring}; 96*724ba675SRob Herring 97*724ba675SRob Herring&i2c0 { 98*724ba675SRob Herring clock-frequency = <100000>; 99*724ba675SRob Herring status = "okay"; 100*724ba675SRob Herring 101*724ba675SRob Herring pinctrl-names = "default", "gpio"; 102*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 103*724ba675SRob Herring pinctrl-1 = <&i2c0_gpio_pins>; 104*724ba675SRob Herring scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 105*724ba675SRob Herring sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 106*724ba675SRob Herring 107*724ba675SRob Herring i2c0mux: mux@71 { 108*724ba675SRob Herring #address-cells = <1>; 109*724ba675SRob Herring #size-cells = <0>; 110*724ba675SRob Herring compatible = "nxp,pca9544"; 111*724ba675SRob Herring reg = <0x71>; 112*724ba675SRob Herring i2c-mux-idle-disconnect; 113*724ba675SRob Herring 114*724ba675SRob Herring i2c@0 { /* POE devices MUX */ 115*724ba675SRob Herring #address-cells = <1>; 116*724ba675SRob Herring #size-cells = <0>; 117*724ba675SRob Herring reg = <0>; 118*724ba675SRob Herring }; 119*724ba675SRob Herring 120*724ba675SRob Herring i2c@1 { 121*724ba675SRob Herring #address-cells = <1>; 122*724ba675SRob Herring #size-cells = <0>; 123*724ba675SRob Herring reg = <1>; 124*724ba675SRob Herring 125*724ba675SRob Herring adt7476_2e: hwmon@2e { 126*724ba675SRob Herring compatible = "adi,adt7476"; 127*724ba675SRob Herring reg = <0x2e>; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring adt7476_2d: hwmon@2d { 131*724ba675SRob Herring compatible = "adi,adt7476"; 132*724ba675SRob Herring reg = <0x2d>; 133*724ba675SRob Herring }; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring i2c@2 { 137*724ba675SRob Herring #address-cells = <1>; 138*724ba675SRob Herring #size-cells = <0>; 139*724ba675SRob Herring reg = <2>; 140*724ba675SRob Herring 141*724ba675SRob Herring rtc@68 { 142*724ba675SRob Herring compatible = "dallas,ds1340"; 143*724ba675SRob Herring reg = <0x68>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring }; 146*724ba675SRob Herring 147*724ba675SRob Herring i2c@3 { 148*724ba675SRob Herring #address-cells = <1>; 149*724ba675SRob Herring #size-cells = <0>; 150*724ba675SRob Herring reg = <3>; 151*724ba675SRob Herring 152*724ba675SRob Herring gpio@20 { 153*724ba675SRob Herring compatible = "nxp,pca9554"; 154*724ba675SRob Herring gpio-controller; 155*724ba675SRob Herring #gpio-cells = <2>; 156*724ba675SRob Herring reg = <0x20>; 157*724ba675SRob Herring }; 158*724ba675SRob Herring }; 159*724ba675SRob Herring }; 160*724ba675SRob Herring}; 161*724ba675SRob Herring 162*724ba675SRob Herring&usb0 { 163*724ba675SRob Herring status = "okay"; 164*724ba675SRob Herring}; 165*724ba675SRob Herring 166*724ba675SRob Herring&spi1 { 167*724ba675SRob Herring pinctrl-names = "default"; 168*724ba675SRob Herring pinctrl-0 = <&spi1_pins>; 169*724ba675SRob Herring status = "okay"; 170*724ba675SRob Herring 171*724ba675SRob Herring flash@1 { 172*724ba675SRob Herring #address-cells = <1>; 173*724ba675SRob Herring #size-cells = <1>; 174*724ba675SRob Herring compatible = "jedec,spi-nor"; 175*724ba675SRob Herring reg = <1>; /* Chip select 1 */ 176*724ba675SRob Herring spi-max-frequency = <54000000>; 177*724ba675SRob Herring 178*724ba675SRob Herring partitions { 179*724ba675SRob Herring compatible = "fixed-partitions"; 180*724ba675SRob Herring #address-cells = <1>; 181*724ba675SRob Herring #size-cells = <1>; 182*724ba675SRob Herring partition@0 { 183*724ba675SRob Herring reg = <0x00000000 0x00100000>; 184*724ba675SRob Herring label = "u-boot"; 185*724ba675SRob Herring }; 186*724ba675SRob Herring partition@100000 { 187*724ba675SRob Herring reg = <0x00100000 0x00040000>; 188*724ba675SRob Herring label = "u-boot-env"; 189*724ba675SRob Herring }; 190*724ba675SRob Herring partition@140000 { 191*724ba675SRob Herring reg = <0x00140000 0x00e80000>; 192*724ba675SRob Herring label = "unused"; 193*724ba675SRob Herring }; 194*724ba675SRob Herring partition@fc0000 { 195*724ba675SRob Herring reg = <0x00fc0000 0x00040000>; 196*724ba675SRob Herring label = "idprom"; 197*724ba675SRob Herring }; 198*724ba675SRob Herring }; 199*724ba675SRob Herring }; 200*724ba675SRob Herring}; 201*724ba675SRob Herring 202*724ba675SRob Herring&nand_controller { 203*724ba675SRob Herring status = "okay"; 204*724ba675SRob Herring 205*724ba675SRob Herring nand@0 { 206*724ba675SRob Herring reg = <0>; 207*724ba675SRob Herring label = "pxa3xx_nand-0"; 208*724ba675SRob Herring nand-rb = <0>; 209*724ba675SRob Herring nand-on-flash-bbt; 210*724ba675SRob Herring nand-ecc-strength = <4>; 211*724ba675SRob Herring nand-ecc-step-size = <512>; 212*724ba675SRob Herring 213*724ba675SRob Herring marvell,nand-enable-arbiter; 214*724ba675SRob Herring 215*724ba675SRob Herring partitions { 216*724ba675SRob Herring compatible = "fixed-partitions"; 217*724ba675SRob Herring #address-cells = <1>; 218*724ba675SRob Herring #size-cells = <1>; 219*724ba675SRob Herring partition@0 { 220*724ba675SRob Herring reg = <0x00000000 0x0f000000>; 221*724ba675SRob Herring label = "user"; 222*724ba675SRob Herring }; 223*724ba675SRob Herring partition@f000000 { 224*724ba675SRob Herring /* Maximum mtdoops size is 8MB, so set to that. */ 225*724ba675SRob Herring reg = <0x0f000000 0x00800000>; 226*724ba675SRob Herring label = "errlog"; 227*724ba675SRob Herring }; 228*724ba675SRob Herring partition@f800000 { 229*724ba675SRob Herring reg = <0x0f800000 0x00800000>; 230*724ba675SRob Herring label = "nand-bbt"; 231*724ba675SRob Herring }; 232*724ba675SRob Herring }; 233*724ba675SRob Herring }; 234*724ba675SRob Herring}; 235*724ba675SRob Herring 236