1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2020 HiSilicon Limited. 4*724ba675SRob Herring * 5*724ba675SRob Herring * DTS file for Hisilicon SD5203 Board 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring/dts-v1/; 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Hisilicon SD5203"; 12*724ba675SRob Herring compatible = "H836ASDJ", "hisilicon,sd5203"; 13*724ba675SRob Herring interrupt-parent = <&vic>; 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <1>; 16*724ba675SRob Herring 17*724ba675SRob Herring chosen { 18*724ba675SRob Herring bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring aliases { 22*724ba675SRob Herring serial0 = &uart0; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring cpus { 26*724ba675SRob Herring #address-cells = <1>; 27*724ba675SRob Herring #size-cells = <0>; 28*724ba675SRob Herring 29*724ba675SRob Herring cpu0 { 30*724ba675SRob Herring device_type = "cpu"; 31*724ba675SRob Herring compatible = "arm,arm926ej-s"; 32*724ba675SRob Herring reg = <0x0>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring memory@30000000 { 37*724ba675SRob Herring device_type = "memory"; 38*724ba675SRob Herring reg = <0x30000000 0x8000000>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring soc { 42*724ba675SRob Herring #address-cells = <1>; 43*724ba675SRob Herring #size-cells = <1>; 44*724ba675SRob Herring compatible = "simple-bus"; 45*724ba675SRob Herring ranges; 46*724ba675SRob Herring 47*724ba675SRob Herring vic: interrupt-controller@10130000 { 48*724ba675SRob Herring compatible = "snps,dw-apb-ictl"; 49*724ba675SRob Herring reg = <0x10130000 0x1000>; 50*724ba675SRob Herring interrupt-controller; 51*724ba675SRob Herring #interrupt-cells = <1>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring refclk125mhz: refclk125mhz { 55*724ba675SRob Herring compatible = "fixed-clock"; 56*724ba675SRob Herring #clock-cells = <0>; 57*724ba675SRob Herring clock-frequency = <125000000>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring 60*724ba675SRob Herring timer0: timer@16002000 { 61*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 62*724ba675SRob Herring reg = <0x16002000 0x1000>; 63*724ba675SRob Herring interrupts = <4>; 64*724ba675SRob Herring clocks = <&refclk125mhz>; 65*724ba675SRob Herring clock-names = "apb_pclk"; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring timer1: timer@16003000 { 69*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 70*724ba675SRob Herring reg = <0x16003000 0x1000>; 71*724ba675SRob Herring interrupts = <5>; 72*724ba675SRob Herring clocks = <&refclk125mhz>; 73*724ba675SRob Herring clock-names = "apb_pclk"; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring uart0: serial@1600d000 { 77*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 78*724ba675SRob Herring reg = <0x1600d000 0x1000>; 79*724ba675SRob Herring bus_id = "uart0"; 80*724ba675SRob Herring clocks = <&refclk125mhz>; 81*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 82*724ba675SRob Herring reg-shift = <2>; 83*724ba675SRob Herring interrupts = <17>; 84*724ba675SRob Herring }; 85*724ba675SRob Herring 86*724ba675SRob Herring uart1: serial@1600c000 { 87*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 88*724ba675SRob Herring reg = <0x1600c000 0x1000>; 89*724ba675SRob Herring clocks = <&refclk125mhz>; 90*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 91*724ba675SRob Herring reg-shift = <2>; 92*724ba675SRob Herring interrupts = <16>; 93*724ba675SRob Herring status = "disabled"; 94*724ba675SRob Herring }; 95*724ba675SRob Herring }; 96*724ba675SRob Herring}; 97