1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * HiSilicon Ltd. HiP04 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013-2014 HiSilicon Ltd. 6*724ba675SRob Herring * Copyright (C) 2013-2014 Linaro Ltd. 7*724ba675SRob Herring * 8*724ba675SRob Herring * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring /* memory bus is 64-bit */ 13*724ba675SRob Herring #address-cells = <2>; 14*724ba675SRob Herring #size-cells = <2>; 15*724ba675SRob Herring 16*724ba675SRob Herring aliases { 17*724ba675SRob Herring serial0 = &uart0; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring bootwrapper { 21*724ba675SRob Herring compatible = "hisilicon,hip04-bootwrapper"; 22*724ba675SRob Herring boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring cpus { 26*724ba675SRob Herring #address-cells = <1>; 27*724ba675SRob Herring #size-cells = <0>; 28*724ba675SRob Herring 29*724ba675SRob Herring cpu-map { 30*724ba675SRob Herring cluster0 { 31*724ba675SRob Herring core0 { 32*724ba675SRob Herring cpu = <&CPU0>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring core1 { 35*724ba675SRob Herring cpu = <&CPU1>; 36*724ba675SRob Herring }; 37*724ba675SRob Herring core2 { 38*724ba675SRob Herring cpu = <&CPU2>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring core3 { 41*724ba675SRob Herring cpu = <&CPU3>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring }; 44*724ba675SRob Herring cluster1 { 45*724ba675SRob Herring core0 { 46*724ba675SRob Herring cpu = <&CPU4>; 47*724ba675SRob Herring }; 48*724ba675SRob Herring core1 { 49*724ba675SRob Herring cpu = <&CPU5>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring core2 { 52*724ba675SRob Herring cpu = <&CPU6>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring core3 { 55*724ba675SRob Herring cpu = <&CPU7>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring }; 58*724ba675SRob Herring cluster2 { 59*724ba675SRob Herring core0 { 60*724ba675SRob Herring cpu = <&CPU8>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring core1 { 63*724ba675SRob Herring cpu = <&CPU9>; 64*724ba675SRob Herring }; 65*724ba675SRob Herring core2 { 66*724ba675SRob Herring cpu = <&CPU10>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring core3 { 69*724ba675SRob Herring cpu = <&CPU11>; 70*724ba675SRob Herring }; 71*724ba675SRob Herring }; 72*724ba675SRob Herring cluster3 { 73*724ba675SRob Herring core0 { 74*724ba675SRob Herring cpu = <&CPU12>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring core1 { 77*724ba675SRob Herring cpu = <&CPU13>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring core2 { 80*724ba675SRob Herring cpu = <&CPU14>; 81*724ba675SRob Herring }; 82*724ba675SRob Herring core3 { 83*724ba675SRob Herring cpu = <&CPU15>; 84*724ba675SRob Herring }; 85*724ba675SRob Herring }; 86*724ba675SRob Herring }; 87*724ba675SRob Herring CPU0: cpu@0 { 88*724ba675SRob Herring device_type = "cpu"; 89*724ba675SRob Herring compatible = "arm,cortex-a15"; 90*724ba675SRob Herring reg = <0>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring CPU1: cpu@1 { 93*724ba675SRob Herring device_type = "cpu"; 94*724ba675SRob Herring compatible = "arm,cortex-a15"; 95*724ba675SRob Herring reg = <1>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring CPU2: cpu@2 { 98*724ba675SRob Herring device_type = "cpu"; 99*724ba675SRob Herring compatible = "arm,cortex-a15"; 100*724ba675SRob Herring reg = <2>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring CPU3: cpu@3 { 103*724ba675SRob Herring device_type = "cpu"; 104*724ba675SRob Herring compatible = "arm,cortex-a15"; 105*724ba675SRob Herring reg = <3>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring CPU4: cpu@100 { 108*724ba675SRob Herring device_type = "cpu"; 109*724ba675SRob Herring compatible = "arm,cortex-a15"; 110*724ba675SRob Herring reg = <0x100>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring CPU5: cpu@101 { 113*724ba675SRob Herring device_type = "cpu"; 114*724ba675SRob Herring compatible = "arm,cortex-a15"; 115*724ba675SRob Herring reg = <0x101>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring CPU6: cpu@102 { 118*724ba675SRob Herring device_type = "cpu"; 119*724ba675SRob Herring compatible = "arm,cortex-a15"; 120*724ba675SRob Herring reg = <0x102>; 121*724ba675SRob Herring }; 122*724ba675SRob Herring CPU7: cpu@103 { 123*724ba675SRob Herring device_type = "cpu"; 124*724ba675SRob Herring compatible = "arm,cortex-a15"; 125*724ba675SRob Herring reg = <0x103>; 126*724ba675SRob Herring }; 127*724ba675SRob Herring CPU8: cpu@200 { 128*724ba675SRob Herring device_type = "cpu"; 129*724ba675SRob Herring compatible = "arm,cortex-a15"; 130*724ba675SRob Herring reg = <0x200>; 131*724ba675SRob Herring }; 132*724ba675SRob Herring CPU9: cpu@201 { 133*724ba675SRob Herring device_type = "cpu"; 134*724ba675SRob Herring compatible = "arm,cortex-a15"; 135*724ba675SRob Herring reg = <0x201>; 136*724ba675SRob Herring }; 137*724ba675SRob Herring CPU10: cpu@202 { 138*724ba675SRob Herring device_type = "cpu"; 139*724ba675SRob Herring compatible = "arm,cortex-a15"; 140*724ba675SRob Herring reg = <0x202>; 141*724ba675SRob Herring }; 142*724ba675SRob Herring CPU11: cpu@203 { 143*724ba675SRob Herring device_type = "cpu"; 144*724ba675SRob Herring compatible = "arm,cortex-a15"; 145*724ba675SRob Herring reg = <0x203>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring CPU12: cpu@300 { 148*724ba675SRob Herring device_type = "cpu"; 149*724ba675SRob Herring compatible = "arm,cortex-a15"; 150*724ba675SRob Herring reg = <0x300>; 151*724ba675SRob Herring }; 152*724ba675SRob Herring CPU13: cpu@301 { 153*724ba675SRob Herring device_type = "cpu"; 154*724ba675SRob Herring compatible = "arm,cortex-a15"; 155*724ba675SRob Herring reg = <0x301>; 156*724ba675SRob Herring }; 157*724ba675SRob Herring CPU14: cpu@302 { 158*724ba675SRob Herring device_type = "cpu"; 159*724ba675SRob Herring compatible = "arm,cortex-a15"; 160*724ba675SRob Herring reg = <0x302>; 161*724ba675SRob Herring }; 162*724ba675SRob Herring CPU15: cpu@303 { 163*724ba675SRob Herring device_type = "cpu"; 164*724ba675SRob Herring compatible = "arm,cortex-a15"; 165*724ba675SRob Herring reg = <0x303>; 166*724ba675SRob Herring }; 167*724ba675SRob Herring }; 168*724ba675SRob Herring 169*724ba675SRob Herring timer { 170*724ba675SRob Herring compatible = "arm,armv7-timer"; 171*724ba675SRob Herring interrupt-parent = <&gic>; 172*724ba675SRob Herring interrupts = <1 13 0xf08>, 173*724ba675SRob Herring <1 14 0xf08>, 174*724ba675SRob Herring <1 11 0xf08>, 175*724ba675SRob Herring <1 10 0xf08>; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring clk_50m: clk_50m { 179*724ba675SRob Herring #clock-cells = <0>; 180*724ba675SRob Herring compatible = "fixed-clock"; 181*724ba675SRob Herring clock-frequency = <50000000>; 182*724ba675SRob Herring }; 183*724ba675SRob Herring 184*724ba675SRob Herring clk_168m: clk_168m { 185*724ba675SRob Herring #clock-cells = <0>; 186*724ba675SRob Herring compatible = "fixed-clock"; 187*724ba675SRob Herring clock-frequency = <168000000>; 188*724ba675SRob Herring }; 189*724ba675SRob Herring 190*724ba675SRob Herring clk_375m: clk_375m { 191*724ba675SRob Herring #clock-cells = <0>; 192*724ba675SRob Herring compatible = "fixed-clock"; 193*724ba675SRob Herring clock-frequency = <375000000>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring soc { 197*724ba675SRob Herring /* It's a 32-bit SoC. */ 198*724ba675SRob Herring #address-cells = <1>; 199*724ba675SRob Herring #size-cells = <1>; 200*724ba675SRob Herring compatible = "simple-bus"; 201*724ba675SRob Herring interrupt-parent = <&gic>; 202*724ba675SRob Herring ranges = <0 0 0xe0000000 0x10000000>; 203*724ba675SRob Herring 204*724ba675SRob Herring gic: interrupt-controller@c01000 { 205*724ba675SRob Herring compatible = "hisilicon,hip04-intc"; 206*724ba675SRob Herring #interrupt-cells = <3>; 207*724ba675SRob Herring #address-cells = <0>; 208*724ba675SRob Herring interrupt-controller; 209*724ba675SRob Herring interrupts = <1 9 0xf04>; 210*724ba675SRob Herring 211*724ba675SRob Herring reg = <0xc01000 0x1000>, <0xc02000 0x1000>, 212*724ba675SRob Herring <0xc04000 0x2000>, <0xc06000 0x2000>; 213*724ba675SRob Herring }; 214*724ba675SRob Herring 215*724ba675SRob Herring sysctrl: sysctrl { 216*724ba675SRob Herring compatible = "hisilicon,sysctrl", "syscon"; 217*724ba675SRob Herring reg = <0x3e00000 0x00100000>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring fabric: fabric { 221*724ba675SRob Herring compatible = "hisilicon,hip04-fabric"; 222*724ba675SRob Herring reg = <0x302a000 0x1000>; 223*724ba675SRob Herring }; 224*724ba675SRob Herring 225*724ba675SRob Herring dual_timer0: dual_timer@3000000 { 226*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 227*724ba675SRob Herring reg = <0x3000000 0x1000>; 228*724ba675SRob Herring interrupts = <0 224 4>; 229*724ba675SRob Herring clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; 230*724ba675SRob Herring clock-names = "timer0clk", "timer1clk", "apb_pclk"; 231*724ba675SRob Herring }; 232*724ba675SRob Herring 233*724ba675SRob Herring arm-pmu { 234*724ba675SRob Herring compatible = "arm,cortex-a15-pmu"; 235*724ba675SRob Herring interrupts = <0 64 4>, 236*724ba675SRob Herring <0 65 4>, 237*724ba675SRob Herring <0 66 4>, 238*724ba675SRob Herring <0 67 4>, 239*724ba675SRob Herring <0 68 4>, 240*724ba675SRob Herring <0 69 4>, 241*724ba675SRob Herring <0 70 4>, 242*724ba675SRob Herring <0 71 4>, 243*724ba675SRob Herring <0 72 4>, 244*724ba675SRob Herring <0 73 4>, 245*724ba675SRob Herring <0 74 4>, 246*724ba675SRob Herring <0 75 4>, 247*724ba675SRob Herring <0 76 4>, 248*724ba675SRob Herring <0 77 4>, 249*724ba675SRob Herring <0 78 4>, 250*724ba675SRob Herring <0 79 4>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring uart0: serial@4007000 { 254*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 255*724ba675SRob Herring reg = <0x4007000 0x1000>; 256*724ba675SRob Herring interrupts = <0 381 4>; 257*724ba675SRob Herring clocks = <&clk_168m>, <&clk_168m>; 258*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 259*724ba675SRob Herring reg-shift = <2>; 260*724ba675SRob Herring status = "disabled"; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring sata0: sata@a000000 { 264*724ba675SRob Herring compatible = "hisilicon,hisi-ahci"; 265*724ba675SRob Herring reg = <0xa000000 0x1000000>; 266*724ba675SRob Herring interrupts = <0 372 4>; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring }; 270*724ba675SRob Herring 271*724ba675SRob Herring etb@0,e3c42000 { 272*724ba675SRob Herring compatible = "arm,coresight-etb10", "arm,primecell"; 273*724ba675SRob Herring reg = <0 0xe3c42000 0 0x1000>; 274*724ba675SRob Herring 275*724ba675SRob Herring clocks = <&clk_375m>; 276*724ba675SRob Herring clock-names = "apb_pclk"; 277*724ba675SRob Herring in-ports { 278*724ba675SRob Herring port { 279*724ba675SRob Herring etb0_in_port: endpoint@0 { 280*724ba675SRob Herring remote-endpoint = <&replicator0_out_port0>; 281*724ba675SRob Herring }; 282*724ba675SRob Herring }; 283*724ba675SRob Herring }; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring etb@0,e3c82000 { 287*724ba675SRob Herring compatible = "arm,coresight-etb10", "arm,primecell"; 288*724ba675SRob Herring reg = <0 0xe3c82000 0 0x1000>; 289*724ba675SRob Herring 290*724ba675SRob Herring clocks = <&clk_375m>; 291*724ba675SRob Herring clock-names = "apb_pclk"; 292*724ba675SRob Herring in-ports { 293*724ba675SRob Herring port { 294*724ba675SRob Herring etb1_in_port: endpoint@0 { 295*724ba675SRob Herring remote-endpoint = <&replicator1_out_port0>; 296*724ba675SRob Herring }; 297*724ba675SRob Herring }; 298*724ba675SRob Herring }; 299*724ba675SRob Herring }; 300*724ba675SRob Herring 301*724ba675SRob Herring etb@0,e3cc2000 { 302*724ba675SRob Herring compatible = "arm,coresight-etb10", "arm,primecell"; 303*724ba675SRob Herring reg = <0 0xe3cc2000 0 0x1000>; 304*724ba675SRob Herring 305*724ba675SRob Herring clocks = <&clk_375m>; 306*724ba675SRob Herring clock-names = "apb_pclk"; 307*724ba675SRob Herring in-ports { 308*724ba675SRob Herring port { 309*724ba675SRob Herring etb2_in_port: endpoint@0 { 310*724ba675SRob Herring remote-endpoint = <&replicator2_out_port0>; 311*724ba675SRob Herring }; 312*724ba675SRob Herring }; 313*724ba675SRob Herring }; 314*724ba675SRob Herring }; 315*724ba675SRob Herring 316*724ba675SRob Herring etb@0,e3d02000 { 317*724ba675SRob Herring compatible = "arm,coresight-etb10", "arm,primecell"; 318*724ba675SRob Herring reg = <0 0xe3d02000 0 0x1000>; 319*724ba675SRob Herring 320*724ba675SRob Herring clocks = <&clk_375m>; 321*724ba675SRob Herring clock-names = "apb_pclk"; 322*724ba675SRob Herring in-ports { 323*724ba675SRob Herring port { 324*724ba675SRob Herring etb3_in_port: endpoint@0 { 325*724ba675SRob Herring remote-endpoint = <&replicator3_out_port0>; 326*724ba675SRob Herring }; 327*724ba675SRob Herring }; 328*724ba675SRob Herring }; 329*724ba675SRob Herring }; 330*724ba675SRob Herring 331*724ba675SRob Herring tpiu@0,e3c05000 { 332*724ba675SRob Herring compatible = "arm,coresight-tpiu", "arm,primecell"; 333*724ba675SRob Herring reg = <0 0xe3c05000 0 0x1000>; 334*724ba675SRob Herring 335*724ba675SRob Herring clocks = <&clk_375m>; 336*724ba675SRob Herring clock-names = "apb_pclk"; 337*724ba675SRob Herring in-ports { 338*724ba675SRob Herring port { 339*724ba675SRob Herring tpiu_in_port: endpoint@0 { 340*724ba675SRob Herring remote-endpoint = <&funnel4_out_port0>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring }; 343*724ba675SRob Herring }; 344*724ba675SRob Herring }; 345*724ba675SRob Herring 346*724ba675SRob Herring replicator0 { 347*724ba675SRob Herring /* non-configurable replicators don't show up on the 348*724ba675SRob Herring * AMBA bus. As such no need to add "arm,primecell". 349*724ba675SRob Herring */ 350*724ba675SRob Herring compatible = "arm,coresight-static-replicator"; 351*724ba675SRob Herring 352*724ba675SRob Herring out-ports { 353*724ba675SRob Herring #address-cells = <1>; 354*724ba675SRob Herring #size-cells = <0>; 355*724ba675SRob Herring 356*724ba675SRob Herring /* replicator output ports */ 357*724ba675SRob Herring port@0 { 358*724ba675SRob Herring reg = <0>; 359*724ba675SRob Herring replicator0_out_port0: endpoint { 360*724ba675SRob Herring remote-endpoint = <&etb0_in_port>; 361*724ba675SRob Herring }; 362*724ba675SRob Herring }; 363*724ba675SRob Herring 364*724ba675SRob Herring port@1 { 365*724ba675SRob Herring reg = <1>; 366*724ba675SRob Herring replicator0_out_port1: endpoint { 367*724ba675SRob Herring remote-endpoint = <&funnel4_in_port0>; 368*724ba675SRob Herring }; 369*724ba675SRob Herring }; 370*724ba675SRob Herring }; 371*724ba675SRob Herring 372*724ba675SRob Herring in-ports { 373*724ba675SRob Herring port { 374*724ba675SRob Herring replicator0_in_port0: endpoint { 375*724ba675SRob Herring remote-endpoint = <&funnel0_out_port0>; 376*724ba675SRob Herring }; 377*724ba675SRob Herring }; 378*724ba675SRob Herring }; 379*724ba675SRob Herring }; 380*724ba675SRob Herring 381*724ba675SRob Herring replicator1 { 382*724ba675SRob Herring /* non-configurable replicators don't show up on the 383*724ba675SRob Herring * AMBA bus. As such no need to add "arm,primecell". 384*724ba675SRob Herring */ 385*724ba675SRob Herring compatible = "arm,coresight-static-replicator"; 386*724ba675SRob Herring 387*724ba675SRob Herring out-ports { 388*724ba675SRob Herring #address-cells = <1>; 389*724ba675SRob Herring #size-cells = <0>; 390*724ba675SRob Herring 391*724ba675SRob Herring /* replicator output ports */ 392*724ba675SRob Herring port@0 { 393*724ba675SRob Herring reg = <0>; 394*724ba675SRob Herring replicator1_out_port0: endpoint { 395*724ba675SRob Herring remote-endpoint = <&etb1_in_port>; 396*724ba675SRob Herring }; 397*724ba675SRob Herring }; 398*724ba675SRob Herring 399*724ba675SRob Herring port@1 { 400*724ba675SRob Herring reg = <1>; 401*724ba675SRob Herring replicator1_out_port1: endpoint { 402*724ba675SRob Herring remote-endpoint = <&funnel4_in_port1>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring }; 405*724ba675SRob Herring }; 406*724ba675SRob Herring 407*724ba675SRob Herring in-ports { 408*724ba675SRob Herring port { 409*724ba675SRob Herring replicator1_in_port0: endpoint { 410*724ba675SRob Herring remote-endpoint = <&funnel1_out_port0>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring }; 413*724ba675SRob Herring }; 414*724ba675SRob Herring }; 415*724ba675SRob Herring 416*724ba675SRob Herring replicator2 { 417*724ba675SRob Herring /* non-configurable replicators don't show up on the 418*724ba675SRob Herring * AMBA bus. As such no need to add "arm,primecell". 419*724ba675SRob Herring */ 420*724ba675SRob Herring compatible = "arm,coresight-static-replicator"; 421*724ba675SRob Herring 422*724ba675SRob Herring out-ports { 423*724ba675SRob Herring #address-cells = <1>; 424*724ba675SRob Herring #size-cells = <0>; 425*724ba675SRob Herring 426*724ba675SRob Herring port@0 { 427*724ba675SRob Herring reg = <0>; 428*724ba675SRob Herring replicator2_out_port0: endpoint { 429*724ba675SRob Herring remote-endpoint = <&etb2_in_port>; 430*724ba675SRob Herring }; 431*724ba675SRob Herring }; 432*724ba675SRob Herring 433*724ba675SRob Herring port@1 { 434*724ba675SRob Herring reg = <1>; 435*724ba675SRob Herring replicator2_out_port1: endpoint { 436*724ba675SRob Herring remote-endpoint = <&funnel4_in_port2>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring }; 439*724ba675SRob Herring }; 440*724ba675SRob Herring 441*724ba675SRob Herring in-ports { 442*724ba675SRob Herring port { 443*724ba675SRob Herring replicator2_in_port0: endpoint { 444*724ba675SRob Herring remote-endpoint = <&funnel2_out_port0>; 445*724ba675SRob Herring }; 446*724ba675SRob Herring }; 447*724ba675SRob Herring }; 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring replicator3 { 451*724ba675SRob Herring /* non-configurable replicators don't show up on the 452*724ba675SRob Herring * AMBA bus. As such no need to add "arm,primecell". 453*724ba675SRob Herring */ 454*724ba675SRob Herring compatible = "arm,coresight-static-replicator"; 455*724ba675SRob Herring 456*724ba675SRob Herring out-ports { 457*724ba675SRob Herring #address-cells = <1>; 458*724ba675SRob Herring #size-cells = <0>; 459*724ba675SRob Herring 460*724ba675SRob Herring port@0 { 461*724ba675SRob Herring reg = <0>; 462*724ba675SRob Herring replicator3_out_port0: endpoint { 463*724ba675SRob Herring remote-endpoint = <&etb3_in_port>; 464*724ba675SRob Herring }; 465*724ba675SRob Herring }; 466*724ba675SRob Herring 467*724ba675SRob Herring port@1 { 468*724ba675SRob Herring reg = <1>; 469*724ba675SRob Herring replicator3_out_port1: endpoint { 470*724ba675SRob Herring remote-endpoint = <&funnel4_in_port3>; 471*724ba675SRob Herring }; 472*724ba675SRob Herring }; 473*724ba675SRob Herring }; 474*724ba675SRob Herring 475*724ba675SRob Herring in-ports { 476*724ba675SRob Herring port { 477*724ba675SRob Herring replicator3_in_port0: endpoint { 478*724ba675SRob Herring remote-endpoint = <&funnel3_out_port0>; 479*724ba675SRob Herring }; 480*724ba675SRob Herring }; 481*724ba675SRob Herring }; 482*724ba675SRob Herring }; 483*724ba675SRob Herring 484*724ba675SRob Herring funnel@0,e3c41000 { 485*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 486*724ba675SRob Herring reg = <0 0xe3c41000 0 0x1000>; 487*724ba675SRob Herring 488*724ba675SRob Herring clocks = <&clk_375m>; 489*724ba675SRob Herring clock-names = "apb_pclk"; 490*724ba675SRob Herring out-ports { 491*724ba675SRob Herring port { 492*724ba675SRob Herring funnel0_out_port0: endpoint { 493*724ba675SRob Herring remote-endpoint = 494*724ba675SRob Herring <&replicator0_in_port0>; 495*724ba675SRob Herring }; 496*724ba675SRob Herring }; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring in-ports { 500*724ba675SRob Herring #address-cells = <1>; 501*724ba675SRob Herring #size-cells = <0>; 502*724ba675SRob Herring 503*724ba675SRob Herring port@0 { 504*724ba675SRob Herring reg = <0>; 505*724ba675SRob Herring funnel0_in_port0: endpoint { 506*724ba675SRob Herring remote-endpoint = <&ptm0_out_port>; 507*724ba675SRob Herring }; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring port@1 { 511*724ba675SRob Herring reg = <1>; 512*724ba675SRob Herring funnel0_in_port1: endpoint { 513*724ba675SRob Herring remote-endpoint = <&ptm1_out_port>; 514*724ba675SRob Herring }; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring port@2 { 518*724ba675SRob Herring reg = <2>; 519*724ba675SRob Herring funnel0_in_port2: endpoint { 520*724ba675SRob Herring remote-endpoint = <&ptm2_out_port>; 521*724ba675SRob Herring }; 522*724ba675SRob Herring }; 523*724ba675SRob Herring 524*724ba675SRob Herring port@3 { 525*724ba675SRob Herring reg = <3>; 526*724ba675SRob Herring funnel0_in_port3: endpoint { 527*724ba675SRob Herring remote-endpoint = <&ptm3_out_port>; 528*724ba675SRob Herring }; 529*724ba675SRob Herring }; 530*724ba675SRob Herring }; 531*724ba675SRob Herring }; 532*724ba675SRob Herring 533*724ba675SRob Herring funnel@0,e3c81000 { 534*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 535*724ba675SRob Herring reg = <0 0xe3c81000 0 0x1000>; 536*724ba675SRob Herring 537*724ba675SRob Herring clocks = <&clk_375m>; 538*724ba675SRob Herring clock-names = "apb_pclk"; 539*724ba675SRob Herring out-ports { 540*724ba675SRob Herring port { 541*724ba675SRob Herring funnel1_out_port0: endpoint { 542*724ba675SRob Herring remote-endpoint = 543*724ba675SRob Herring <&replicator1_in_port0>; 544*724ba675SRob Herring }; 545*724ba675SRob Herring }; 546*724ba675SRob Herring }; 547*724ba675SRob Herring 548*724ba675SRob Herring in-ports { 549*724ba675SRob Herring #address-cells = <1>; 550*724ba675SRob Herring #size-cells = <0>; 551*724ba675SRob Herring 552*724ba675SRob Herring port@0 { 553*724ba675SRob Herring reg = <0>; 554*724ba675SRob Herring funnel1_in_port0: endpoint { 555*724ba675SRob Herring remote-endpoint = <&ptm4_out_port>; 556*724ba675SRob Herring }; 557*724ba675SRob Herring }; 558*724ba675SRob Herring 559*724ba675SRob Herring port@1 { 560*724ba675SRob Herring reg = <1>; 561*724ba675SRob Herring funnel1_in_port1: endpoint { 562*724ba675SRob Herring remote-endpoint = <&ptm5_out_port>; 563*724ba675SRob Herring }; 564*724ba675SRob Herring }; 565*724ba675SRob Herring 566*724ba675SRob Herring port@2 { 567*724ba675SRob Herring reg = <2>; 568*724ba675SRob Herring funnel1_in_port2: endpoint { 569*724ba675SRob Herring remote-endpoint = <&ptm6_out_port>; 570*724ba675SRob Herring }; 571*724ba675SRob Herring }; 572*724ba675SRob Herring 573*724ba675SRob Herring port@3 { 574*724ba675SRob Herring reg = <3>; 575*724ba675SRob Herring funnel1_in_port3: endpoint { 576*724ba675SRob Herring remote-endpoint = <&ptm7_out_port>; 577*724ba675SRob Herring }; 578*724ba675SRob Herring }; 579*724ba675SRob Herring }; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring funnel@0,e3cc1000 { 583*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 584*724ba675SRob Herring reg = <0 0xe3cc1000 0 0x1000>; 585*724ba675SRob Herring 586*724ba675SRob Herring clocks = <&clk_375m>; 587*724ba675SRob Herring clock-names = "apb_pclk"; 588*724ba675SRob Herring out-ports { 589*724ba675SRob Herring port { 590*724ba675SRob Herring funnel2_out_port0: endpoint { 591*724ba675SRob Herring remote-endpoint = 592*724ba675SRob Herring <&replicator2_in_port0>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring }; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring in-ports { 598*724ba675SRob Herring #address-cells = <1>; 599*724ba675SRob Herring #size-cells = <0>; 600*724ba675SRob Herring 601*724ba675SRob Herring port@0 { 602*724ba675SRob Herring reg = <0>; 603*724ba675SRob Herring funnel2_in_port0: endpoint { 604*724ba675SRob Herring remote-endpoint = <&ptm8_out_port>; 605*724ba675SRob Herring }; 606*724ba675SRob Herring }; 607*724ba675SRob Herring 608*724ba675SRob Herring port@1 { 609*724ba675SRob Herring reg = <1>; 610*724ba675SRob Herring funnel2_in_port1: endpoint { 611*724ba675SRob Herring remote-endpoint = <&ptm9_out_port>; 612*724ba675SRob Herring }; 613*724ba675SRob Herring }; 614*724ba675SRob Herring 615*724ba675SRob Herring port@2 { 616*724ba675SRob Herring reg = <2>; 617*724ba675SRob Herring funnel2_in_port2: endpoint { 618*724ba675SRob Herring remote-endpoint = <&ptm10_out_port>; 619*724ba675SRob Herring }; 620*724ba675SRob Herring }; 621*724ba675SRob Herring 622*724ba675SRob Herring port@3 { 623*724ba675SRob Herring reg = <3>; 624*724ba675SRob Herring funnel2_in_port3: endpoint { 625*724ba675SRob Herring remote-endpoint = <&ptm11_out_port>; 626*724ba675SRob Herring }; 627*724ba675SRob Herring }; 628*724ba675SRob Herring }; 629*724ba675SRob Herring }; 630*724ba675SRob Herring 631*724ba675SRob Herring funnel@0,e3d01000 { 632*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 633*724ba675SRob Herring reg = <0 0xe3d01000 0 0x1000>; 634*724ba675SRob Herring 635*724ba675SRob Herring clocks = <&clk_375m>; 636*724ba675SRob Herring clock-names = "apb_pclk"; 637*724ba675SRob Herring out-ports { 638*724ba675SRob Herring port { 639*724ba675SRob Herring funnel3_out_port0: endpoint { 640*724ba675SRob Herring remote-endpoint = 641*724ba675SRob Herring <&replicator3_in_port0>; 642*724ba675SRob Herring }; 643*724ba675SRob Herring }; 644*724ba675SRob Herring }; 645*724ba675SRob Herring 646*724ba675SRob Herring in-ports { 647*724ba675SRob Herring #address-cells = <1>; 648*724ba675SRob Herring #size-cells = <0>; 649*724ba675SRob Herring 650*724ba675SRob Herring port@0 { 651*724ba675SRob Herring reg = <0>; 652*724ba675SRob Herring funnel3_in_port0: endpoint { 653*724ba675SRob Herring remote-endpoint = <&ptm12_out_port>; 654*724ba675SRob Herring }; 655*724ba675SRob Herring }; 656*724ba675SRob Herring 657*724ba675SRob Herring port@1 { 658*724ba675SRob Herring reg = <1>; 659*724ba675SRob Herring funnel3_in_port1: endpoint { 660*724ba675SRob Herring remote-endpoint = <&ptm13_out_port>; 661*724ba675SRob Herring }; 662*724ba675SRob Herring }; 663*724ba675SRob Herring 664*724ba675SRob Herring port@2 { 665*724ba675SRob Herring reg = <2>; 666*724ba675SRob Herring funnel3_in_port2: endpoint { 667*724ba675SRob Herring remote-endpoint = <&ptm14_out_port>; 668*724ba675SRob Herring }; 669*724ba675SRob Herring }; 670*724ba675SRob Herring 671*724ba675SRob Herring port@3 { 672*724ba675SRob Herring reg = <3>; 673*724ba675SRob Herring funnel3_in_port3: endpoint { 674*724ba675SRob Herring remote-endpoint = <&ptm15_out_port>; 675*724ba675SRob Herring }; 676*724ba675SRob Herring }; 677*724ba675SRob Herring }; 678*724ba675SRob Herring }; 679*724ba675SRob Herring 680*724ba675SRob Herring funnel@0,e3c04000 { 681*724ba675SRob Herring compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 682*724ba675SRob Herring reg = <0 0xe3c04000 0 0x1000>; 683*724ba675SRob Herring 684*724ba675SRob Herring clocks = <&clk_375m>; 685*724ba675SRob Herring clock-names = "apb_pclk"; 686*724ba675SRob Herring out-ports { 687*724ba675SRob Herring port { 688*724ba675SRob Herring funnel4_out_port0: endpoint { 689*724ba675SRob Herring remote-endpoint = <&tpiu_in_port>; 690*724ba675SRob Herring }; 691*724ba675SRob Herring }; 692*724ba675SRob Herring }; 693*724ba675SRob Herring 694*724ba675SRob Herring in-ports { 695*724ba675SRob Herring #address-cells = <1>; 696*724ba675SRob Herring #size-cells = <0>; 697*724ba675SRob Herring 698*724ba675SRob Herring port@0 { 699*724ba675SRob Herring reg = <0>; 700*724ba675SRob Herring funnel4_in_port0: endpoint { 701*724ba675SRob Herring remote-endpoint = 702*724ba675SRob Herring <&replicator0_out_port1>; 703*724ba675SRob Herring }; 704*724ba675SRob Herring }; 705*724ba675SRob Herring 706*724ba675SRob Herring port@1 { 707*724ba675SRob Herring reg = <1>; 708*724ba675SRob Herring funnel4_in_port1: endpoint { 709*724ba675SRob Herring remote-endpoint = 710*724ba675SRob Herring <&replicator1_out_port1>; 711*724ba675SRob Herring }; 712*724ba675SRob Herring }; 713*724ba675SRob Herring 714*724ba675SRob Herring port@2 { 715*724ba675SRob Herring reg = <2>; 716*724ba675SRob Herring funnel4_in_port2: endpoint { 717*724ba675SRob Herring remote-endpoint = 718*724ba675SRob Herring <&replicator2_out_port1>; 719*724ba675SRob Herring }; 720*724ba675SRob Herring }; 721*724ba675SRob Herring 722*724ba675SRob Herring port@3 { 723*724ba675SRob Herring reg = <3>; 724*724ba675SRob Herring funnel4_in_port3: endpoint { 725*724ba675SRob Herring remote-endpoint = 726*724ba675SRob Herring <&replicator3_out_port1>; 727*724ba675SRob Herring }; 728*724ba675SRob Herring }; 729*724ba675SRob Herring }; 730*724ba675SRob Herring }; 731*724ba675SRob Herring 732*724ba675SRob Herring ptm@0,e3c7c000 { 733*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 734*724ba675SRob Herring reg = <0 0xe3c7c000 0 0x1000>; 735*724ba675SRob Herring 736*724ba675SRob Herring clocks = <&clk_375m>; 737*724ba675SRob Herring clock-names = "apb_pclk"; 738*724ba675SRob Herring cpu = <&CPU0>; 739*724ba675SRob Herring out-ports { 740*724ba675SRob Herring port { 741*724ba675SRob Herring ptm0_out_port: endpoint { 742*724ba675SRob Herring remote-endpoint = <&funnel0_in_port0>; 743*724ba675SRob Herring }; 744*724ba675SRob Herring }; 745*724ba675SRob Herring }; 746*724ba675SRob Herring }; 747*724ba675SRob Herring 748*724ba675SRob Herring ptm@0,e3c7d000 { 749*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 750*724ba675SRob Herring reg = <0 0xe3c7d000 0 0x1000>; 751*724ba675SRob Herring 752*724ba675SRob Herring clocks = <&clk_375m>; 753*724ba675SRob Herring clock-names = "apb_pclk"; 754*724ba675SRob Herring cpu = <&CPU1>; 755*724ba675SRob Herring out-ports { 756*724ba675SRob Herring port { 757*724ba675SRob Herring ptm1_out_port: endpoint { 758*724ba675SRob Herring remote-endpoint = <&funnel0_in_port1>; 759*724ba675SRob Herring }; 760*724ba675SRob Herring }; 761*724ba675SRob Herring }; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring ptm@0,e3c7e000 { 765*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 766*724ba675SRob Herring reg = <0 0xe3c7e000 0 0x1000>; 767*724ba675SRob Herring 768*724ba675SRob Herring clocks = <&clk_375m>; 769*724ba675SRob Herring clock-names = "apb_pclk"; 770*724ba675SRob Herring cpu = <&CPU2>; 771*724ba675SRob Herring out-ports { 772*724ba675SRob Herring port { 773*724ba675SRob Herring ptm2_out_port: endpoint { 774*724ba675SRob Herring remote-endpoint = <&funnel0_in_port2>; 775*724ba675SRob Herring }; 776*724ba675SRob Herring }; 777*724ba675SRob Herring }; 778*724ba675SRob Herring }; 779*724ba675SRob Herring 780*724ba675SRob Herring ptm@0,e3c7f000 { 781*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 782*724ba675SRob Herring reg = <0 0xe3c7f000 0 0x1000>; 783*724ba675SRob Herring 784*724ba675SRob Herring clocks = <&clk_375m>; 785*724ba675SRob Herring clock-names = "apb_pclk"; 786*724ba675SRob Herring cpu = <&CPU3>; 787*724ba675SRob Herring out-ports { 788*724ba675SRob Herring port { 789*724ba675SRob Herring ptm3_out_port: endpoint { 790*724ba675SRob Herring remote-endpoint = <&funnel0_in_port3>; 791*724ba675SRob Herring }; 792*724ba675SRob Herring }; 793*724ba675SRob Herring }; 794*724ba675SRob Herring }; 795*724ba675SRob Herring 796*724ba675SRob Herring ptm@0,e3cbc000 { 797*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 798*724ba675SRob Herring reg = <0 0xe3cbc000 0 0x1000>; 799*724ba675SRob Herring 800*724ba675SRob Herring clocks = <&clk_375m>; 801*724ba675SRob Herring clock-names = "apb_pclk"; 802*724ba675SRob Herring cpu = <&CPU4>; 803*724ba675SRob Herring out-ports { 804*724ba675SRob Herring port { 805*724ba675SRob Herring ptm4_out_port: endpoint { 806*724ba675SRob Herring remote-endpoint = <&funnel1_in_port0>; 807*724ba675SRob Herring }; 808*724ba675SRob Herring }; 809*724ba675SRob Herring }; 810*724ba675SRob Herring }; 811*724ba675SRob Herring 812*724ba675SRob Herring ptm@0,e3cbd000 { 813*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 814*724ba675SRob Herring reg = <0 0xe3cbd000 0 0x1000>; 815*724ba675SRob Herring 816*724ba675SRob Herring clocks = <&clk_375m>; 817*724ba675SRob Herring clock-names = "apb_pclk"; 818*724ba675SRob Herring cpu = <&CPU5>; 819*724ba675SRob Herring out-ports { 820*724ba675SRob Herring port { 821*724ba675SRob Herring ptm5_out_port: endpoint { 822*724ba675SRob Herring remote-endpoint = <&funnel1_in_port1>; 823*724ba675SRob Herring }; 824*724ba675SRob Herring }; 825*724ba675SRob Herring }; 826*724ba675SRob Herring }; 827*724ba675SRob Herring 828*724ba675SRob Herring ptm@0,e3cbe000 { 829*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 830*724ba675SRob Herring reg = <0 0xe3cbe000 0 0x1000>; 831*724ba675SRob Herring 832*724ba675SRob Herring clocks = <&clk_375m>; 833*724ba675SRob Herring clock-names = "apb_pclk"; 834*724ba675SRob Herring cpu = <&CPU6>; 835*724ba675SRob Herring out-ports { 836*724ba675SRob Herring port { 837*724ba675SRob Herring ptm6_out_port: endpoint { 838*724ba675SRob Herring remote-endpoint = <&funnel1_in_port2>; 839*724ba675SRob Herring }; 840*724ba675SRob Herring }; 841*724ba675SRob Herring }; 842*724ba675SRob Herring }; 843*724ba675SRob Herring 844*724ba675SRob Herring ptm@0,e3cbf000 { 845*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 846*724ba675SRob Herring reg = <0 0xe3cbf000 0 0x1000>; 847*724ba675SRob Herring 848*724ba675SRob Herring clocks = <&clk_375m>; 849*724ba675SRob Herring clock-names = "apb_pclk"; 850*724ba675SRob Herring cpu = <&CPU7>; 851*724ba675SRob Herring out-ports { 852*724ba675SRob Herring port { 853*724ba675SRob Herring ptm7_out_port: endpoint { 854*724ba675SRob Herring remote-endpoint = <&funnel1_in_port3>; 855*724ba675SRob Herring }; 856*724ba675SRob Herring }; 857*724ba675SRob Herring }; 858*724ba675SRob Herring }; 859*724ba675SRob Herring 860*724ba675SRob Herring ptm@0,e3cfc000 { 861*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 862*724ba675SRob Herring reg = <0 0xe3cfc000 0 0x1000>; 863*724ba675SRob Herring 864*724ba675SRob Herring clocks = <&clk_375m>; 865*724ba675SRob Herring clock-names = "apb_pclk"; 866*724ba675SRob Herring cpu = <&CPU8>; 867*724ba675SRob Herring out-ports { 868*724ba675SRob Herring port { 869*724ba675SRob Herring ptm8_out_port: endpoint { 870*724ba675SRob Herring remote-endpoint = <&funnel2_in_port0>; 871*724ba675SRob Herring }; 872*724ba675SRob Herring }; 873*724ba675SRob Herring }; 874*724ba675SRob Herring }; 875*724ba675SRob Herring 876*724ba675SRob Herring ptm@0,e3cfd000 { 877*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 878*724ba675SRob Herring reg = <0 0xe3cfd000 0 0x1000>; 879*724ba675SRob Herring clocks = <&clk_375m>; 880*724ba675SRob Herring clock-names = "apb_pclk"; 881*724ba675SRob Herring cpu = <&CPU9>; 882*724ba675SRob Herring out-ports { 883*724ba675SRob Herring port { 884*724ba675SRob Herring ptm9_out_port: endpoint { 885*724ba675SRob Herring remote-endpoint = <&funnel2_in_port1>; 886*724ba675SRob Herring }; 887*724ba675SRob Herring }; 888*724ba675SRob Herring }; 889*724ba675SRob Herring }; 890*724ba675SRob Herring 891*724ba675SRob Herring ptm@0,e3cfe000 { 892*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 893*724ba675SRob Herring reg = <0 0xe3cfe000 0 0x1000>; 894*724ba675SRob Herring 895*724ba675SRob Herring clocks = <&clk_375m>; 896*724ba675SRob Herring clock-names = "apb_pclk"; 897*724ba675SRob Herring cpu = <&CPU10>; 898*724ba675SRob Herring out-ports { 899*724ba675SRob Herring port { 900*724ba675SRob Herring ptm10_out_port: endpoint { 901*724ba675SRob Herring remote-endpoint = <&funnel2_in_port2>; 902*724ba675SRob Herring }; 903*724ba675SRob Herring }; 904*724ba675SRob Herring }; 905*724ba675SRob Herring }; 906*724ba675SRob Herring 907*724ba675SRob Herring ptm@0,e3cff000 { 908*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 909*724ba675SRob Herring reg = <0 0xe3cff000 0 0x1000>; 910*724ba675SRob Herring 911*724ba675SRob Herring clocks = <&clk_375m>; 912*724ba675SRob Herring clock-names = "apb_pclk"; 913*724ba675SRob Herring cpu = <&CPU11>; 914*724ba675SRob Herring out-ports { 915*724ba675SRob Herring port { 916*724ba675SRob Herring ptm11_out_port: endpoint { 917*724ba675SRob Herring remote-endpoint = <&funnel2_in_port3>; 918*724ba675SRob Herring }; 919*724ba675SRob Herring }; 920*724ba675SRob Herring }; 921*724ba675SRob Herring }; 922*724ba675SRob Herring 923*724ba675SRob Herring ptm@0,e3d3c000 { 924*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 925*724ba675SRob Herring reg = <0 0xe3d3c000 0 0x1000>; 926*724ba675SRob Herring 927*724ba675SRob Herring clocks = <&clk_375m>; 928*724ba675SRob Herring clock-names = "apb_pclk"; 929*724ba675SRob Herring cpu = <&CPU12>; 930*724ba675SRob Herring out-ports { 931*724ba675SRob Herring port { 932*724ba675SRob Herring ptm12_out_port: endpoint { 933*724ba675SRob Herring remote-endpoint = <&funnel3_in_port0>; 934*724ba675SRob Herring }; 935*724ba675SRob Herring }; 936*724ba675SRob Herring }; 937*724ba675SRob Herring }; 938*724ba675SRob Herring 939*724ba675SRob Herring ptm@0,e3d3d000 { 940*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 941*724ba675SRob Herring reg = <0 0xe3d3d000 0 0x1000>; 942*724ba675SRob Herring 943*724ba675SRob Herring clocks = <&clk_375m>; 944*724ba675SRob Herring clock-names = "apb_pclk"; 945*724ba675SRob Herring cpu = <&CPU13>; 946*724ba675SRob Herring out-ports { 947*724ba675SRob Herring port { 948*724ba675SRob Herring ptm13_out_port: endpoint { 949*724ba675SRob Herring remote-endpoint = <&funnel3_in_port1>; 950*724ba675SRob Herring }; 951*724ba675SRob Herring }; 952*724ba675SRob Herring }; 953*724ba675SRob Herring }; 954*724ba675SRob Herring 955*724ba675SRob Herring ptm@0,e3d3e000 { 956*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 957*724ba675SRob Herring reg = <0 0xe3d3e000 0 0x1000>; 958*724ba675SRob Herring 959*724ba675SRob Herring clocks = <&clk_375m>; 960*724ba675SRob Herring clock-names = "apb_pclk"; 961*724ba675SRob Herring cpu = <&CPU14>; 962*724ba675SRob Herring out-ports { 963*724ba675SRob Herring port { 964*724ba675SRob Herring ptm14_out_port: endpoint { 965*724ba675SRob Herring remote-endpoint = <&funnel3_in_port2>; 966*724ba675SRob Herring }; 967*724ba675SRob Herring }; 968*724ba675SRob Herring }; 969*724ba675SRob Herring }; 970*724ba675SRob Herring 971*724ba675SRob Herring ptm@0,e3d3f000 { 972*724ba675SRob Herring compatible = "arm,coresight-etm3x", "arm,primecell"; 973*724ba675SRob Herring reg = <0 0xe3d3f000 0 0x1000>; 974*724ba675SRob Herring 975*724ba675SRob Herring clocks = <&clk_375m>; 976*724ba675SRob Herring clock-names = "apb_pclk"; 977*724ba675SRob Herring cpu = <&CPU15>; 978*724ba675SRob Herring out-ports { 979*724ba675SRob Herring port { 980*724ba675SRob Herring ptm15_out_port: endpoint { 981*724ba675SRob Herring remote-endpoint = <&funnel3_in_port3>; 982*724ba675SRob Herring }; 983*724ba675SRob Herring }; 984*724ba675SRob Herring }; 985*724ba675SRob Herring }; 986*724ba675SRob Herring}; 987