1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * HiSilicon Ltd. Hi3620 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2012-2013 HiSilicon Ltd. 6*724ba675SRob Herring * Copyright (C) 2012-2013 Linaro Ltd. 7*724ba675SRob Herring * 8*724ba675SRob Herring * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring#include <dt-bindings/clock/hi3620-clock.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <1>; 16*724ba675SRob Herring 17*724ba675SRob Herring aliases { 18*724ba675SRob Herring serial0 = &uart0; 19*724ba675SRob Herring serial1 = &uart1; 20*724ba675SRob Herring serial2 = &uart2; 21*724ba675SRob Herring serial3 = &uart3; 22*724ba675SRob Herring serial4 = &uart4; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring pclk: clk { 26*724ba675SRob Herring compatible = "fixed-clock"; 27*724ba675SRob Herring #clock-cells = <0>; 28*724ba675SRob Herring clock-frequency = <26000000>; 29*724ba675SRob Herring clock-output-names = "apb_pclk"; 30*724ba675SRob Herring }; 31*724ba675SRob Herring 32*724ba675SRob Herring cpus { 33*724ba675SRob Herring #address-cells = <1>; 34*724ba675SRob Herring #size-cells = <0>; 35*724ba675SRob Herring enable-method = "hisilicon,hi3620-smp"; 36*724ba675SRob Herring 37*724ba675SRob Herring cpu@0 { 38*724ba675SRob Herring device_type = "cpu"; 39*724ba675SRob Herring compatible = "arm,cortex-a9"; 40*724ba675SRob Herring reg = <0x0>; 41*724ba675SRob Herring next-level-cache = <&L2>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring cpu@1 { 45*724ba675SRob Herring compatible = "arm,cortex-a9"; 46*724ba675SRob Herring device_type = "cpu"; 47*724ba675SRob Herring reg = <1>; 48*724ba675SRob Herring next-level-cache = <&L2>; 49*724ba675SRob Herring }; 50*724ba675SRob Herring 51*724ba675SRob Herring cpu@2 { 52*724ba675SRob Herring compatible = "arm,cortex-a9"; 53*724ba675SRob Herring device_type = "cpu"; 54*724ba675SRob Herring reg = <2>; 55*724ba675SRob Herring next-level-cache = <&L2>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring cpu@3 { 59*724ba675SRob Herring compatible = "arm,cortex-a9"; 60*724ba675SRob Herring device_type = "cpu"; 61*724ba675SRob Herring reg = <3>; 62*724ba675SRob Herring next-level-cache = <&L2>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring }; 65*724ba675SRob Herring 66*724ba675SRob Herring amba-bus { 67*724ba675SRob Herring 68*724ba675SRob Herring #address-cells = <1>; 69*724ba675SRob Herring #size-cells = <1>; 70*724ba675SRob Herring compatible = "simple-bus"; 71*724ba675SRob Herring interrupt-parent = <&gic>; 72*724ba675SRob Herring ranges = <0 0xfc000000 0x2000000>; 73*724ba675SRob Herring 74*724ba675SRob Herring L2: cache-controller { 75*724ba675SRob Herring compatible = "arm,pl310-cache"; 76*724ba675SRob Herring reg = <0x100000 0x100000>; 77*724ba675SRob Herring interrupts = <0 15 4>; 78*724ba675SRob Herring cache-unified; 79*724ba675SRob Herring cache-level = <2>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring gic: interrupt-controller@1000 { 83*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 84*724ba675SRob Herring #interrupt-cells = <3>; 85*724ba675SRob Herring #address-cells = <0>; 86*724ba675SRob Herring interrupt-controller; 87*724ba675SRob Herring /* gic dist base, gic cpu base */ 88*724ba675SRob Herring reg = <0x1000 0x1000>, <0x100 0x100>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring sysctrl: system-controller@802000 { 92*724ba675SRob Herring compatible = "hisilicon,sysctrl", "syscon"; 93*724ba675SRob Herring #address-cells = <1>; 94*724ba675SRob Herring #size-cells = <1>; 95*724ba675SRob Herring ranges = <0 0x802000 0x1000>; 96*724ba675SRob Herring reg = <0x802000 0x1000>; 97*724ba675SRob Herring 98*724ba675SRob Herring smp-offset = <0x31c>; 99*724ba675SRob Herring resume-offset = <0x308>; 100*724ba675SRob Herring reboot-offset = <0x4>; 101*724ba675SRob Herring 102*724ba675SRob Herring clock: clock@0 { 103*724ba675SRob Herring compatible = "hisilicon,hi3620-clock"; 104*724ba675SRob Herring reg = <0 0x10000>; 105*724ba675SRob Herring #clock-cells = <1>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring dual_timer0: dual_timer@800000 { 110*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 111*724ba675SRob Herring reg = <0x800000 0x1000>; 112*724ba675SRob Herring /* timer00 & timer01 */ 113*724ba675SRob Herring interrupts = <0 0 4>, <0 1 4>; 114*724ba675SRob Herring clocks = <&clock HI3620_TIMER0_MUX>, 115*724ba675SRob Herring <&clock HI3620_TIMER1_MUX>, 116*724ba675SRob Herring <&clock HI3620_TIMER0_MUX>; 117*724ba675SRob Herring clock-names = "timer0clk", "timer1clk", "apb_pclk"; 118*724ba675SRob Herring status = "disabled"; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring dual_timer1: dual_timer@801000 { 122*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 123*724ba675SRob Herring reg = <0x801000 0x1000>; 124*724ba675SRob Herring /* timer10 & timer11 */ 125*724ba675SRob Herring interrupts = <0 2 4>, <0 3 4>; 126*724ba675SRob Herring clocks = <&clock HI3620_TIMER2_MUX>, 127*724ba675SRob Herring <&clock HI3620_TIMER3_MUX>, 128*724ba675SRob Herring <&clock HI3620_TIMER2_MUX>; 129*724ba675SRob Herring clock-names = "timer0clk", "timer1clk", "apb_pclk"; 130*724ba675SRob Herring status = "disabled"; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring dual_timer2: dual_timer@a01000 { 134*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 135*724ba675SRob Herring reg = <0xa01000 0x1000>; 136*724ba675SRob Herring /* timer20 & timer21 */ 137*724ba675SRob Herring interrupts = <0 4 4>, <0 5 4>; 138*724ba675SRob Herring clocks = <&clock HI3620_TIMER4_MUX>, 139*724ba675SRob Herring <&clock HI3620_TIMER5_MUX>, 140*724ba675SRob Herring <&clock HI3620_TIMER4_MUX>; 141*724ba675SRob Herring clock-names = "timer0lck", "timer1clk", "apb_pclk"; 142*724ba675SRob Herring status = "disabled"; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring dual_timer3: dual_timer@a02000 { 146*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 147*724ba675SRob Herring reg = <0xa02000 0x1000>; 148*724ba675SRob Herring /* timer30 & timer31 */ 149*724ba675SRob Herring interrupts = <0 6 4>, <0 7 4>; 150*724ba675SRob Herring clocks = <&clock HI3620_TIMER6_MUX>, 151*724ba675SRob Herring <&clock HI3620_TIMER7_MUX>, 152*724ba675SRob Herring <&clock HI3620_TIMER6_MUX>; 153*724ba675SRob Herring clock-names = "timer0clk", "timer1clk", "apb_pclk"; 154*724ba675SRob Herring status = "disabled"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring dual_timer4: dual_timer@a03000 { 158*724ba675SRob Herring compatible = "arm,sp804", "arm,primecell"; 159*724ba675SRob Herring reg = <0xa03000 0x1000>; 160*724ba675SRob Herring /* timer40 & timer41 */ 161*724ba675SRob Herring interrupts = <0 96 4>, <0 97 4>; 162*724ba675SRob Herring clocks = <&clock HI3620_TIMER8_MUX>, 163*724ba675SRob Herring <&clock HI3620_TIMER9_MUX>, 164*724ba675SRob Herring <&clock HI3620_TIMER8_MUX>; 165*724ba675SRob Herring clock-names = "timer0clk", "timer1clk", "apb_pclk"; 166*724ba675SRob Herring status = "disabled"; 167*724ba675SRob Herring }; 168*724ba675SRob Herring 169*724ba675SRob Herring timer5: timer@600 { 170*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 171*724ba675SRob Herring reg = <0x600 0x20>; 172*724ba675SRob Herring interrupts = <1 13 0xf01>; 173*724ba675SRob Herring }; 174*724ba675SRob Herring 175*724ba675SRob Herring uart0: serial@b00000 { 176*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 177*724ba675SRob Herring reg = <0xb00000 0x1000>; 178*724ba675SRob Herring interrupts = <0 20 4>; 179*724ba675SRob Herring clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; 180*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 181*724ba675SRob Herring status = "disabled"; 182*724ba675SRob Herring }; 183*724ba675SRob Herring 184*724ba675SRob Herring uart1: serial@b01000 { 185*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 186*724ba675SRob Herring reg = <0xb01000 0x1000>; 187*724ba675SRob Herring interrupts = <0 21 4>; 188*724ba675SRob Herring clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; 189*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 190*724ba675SRob Herring status = "disabled"; 191*724ba675SRob Herring }; 192*724ba675SRob Herring 193*724ba675SRob Herring uart2: serial@b02000 { 194*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 195*724ba675SRob Herring reg = <0xb02000 0x1000>; 196*724ba675SRob Herring interrupts = <0 22 4>; 197*724ba675SRob Herring clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; 198*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 199*724ba675SRob Herring status = "disabled"; 200*724ba675SRob Herring }; 201*724ba675SRob Herring 202*724ba675SRob Herring uart3: serial@b03000 { 203*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 204*724ba675SRob Herring reg = <0xb03000 0x1000>; 205*724ba675SRob Herring interrupts = <0 23 4>; 206*724ba675SRob Herring clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; 207*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 208*724ba675SRob Herring status = "disabled"; 209*724ba675SRob Herring }; 210*724ba675SRob Herring 211*724ba675SRob Herring uart4: serial@b04000 { 212*724ba675SRob Herring compatible = "arm,pl011", "arm,primecell"; 213*724ba675SRob Herring reg = <0xb04000 0x1000>; 214*724ba675SRob Herring interrupts = <0 24 4>; 215*724ba675SRob Herring clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; 216*724ba675SRob Herring clock-names = "uartclk", "apb_pclk"; 217*724ba675SRob Herring status = "disabled"; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring gpio0: gpio@806000 { 221*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 222*724ba675SRob Herring reg = <0x806000 0x1000>; 223*724ba675SRob Herring interrupts = <0 64 0x4>; 224*724ba675SRob Herring gpio-controller; 225*724ba675SRob Herring #gpio-cells = <2>; 226*724ba675SRob Herring gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 227*724ba675SRob Herring &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; 228*724ba675SRob Herring interrupt-controller; 229*724ba675SRob Herring #interrupt-cells = <2>; 230*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK0>; 231*724ba675SRob Herring clock-names = "apb_pclk"; 232*724ba675SRob Herring }; 233*724ba675SRob Herring 234*724ba675SRob Herring gpio1: gpio@807000 { 235*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 236*724ba675SRob Herring reg = <0x807000 0x1000>; 237*724ba675SRob Herring interrupts = <0 65 0x4>; 238*724ba675SRob Herring gpio-controller; 239*724ba675SRob Herring #gpio-cells = <2>; 240*724ba675SRob Herring gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 241*724ba675SRob Herring &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 242*724ba675SRob Herring &pmx0 6 5 1 &pmx0 7 6 1>; 243*724ba675SRob Herring interrupt-controller; 244*724ba675SRob Herring #interrupt-cells = <2>; 245*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK1>; 246*724ba675SRob Herring clock-names = "apb_pclk"; 247*724ba675SRob Herring }; 248*724ba675SRob Herring 249*724ba675SRob Herring gpio2: gpio@808000 { 250*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 251*724ba675SRob Herring reg = <0x808000 0x1000>; 252*724ba675SRob Herring interrupts = <0 66 0x4>; 253*724ba675SRob Herring gpio-controller; 254*724ba675SRob Herring #gpio-cells = <2>; 255*724ba675SRob Herring gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 256*724ba675SRob Herring &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 257*724ba675SRob Herring &pmx0 6 3 1 &pmx0 7 3 1>; 258*724ba675SRob Herring interrupt-controller; 259*724ba675SRob Herring #interrupt-cells = <2>; 260*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK2>; 261*724ba675SRob Herring clock-names = "apb_pclk"; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring gpio3: gpio@809000 { 265*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 266*724ba675SRob Herring reg = <0x809000 0x1000>; 267*724ba675SRob Herring interrupts = <0 67 0x4>; 268*724ba675SRob Herring gpio-controller; 269*724ba675SRob Herring #gpio-cells = <2>; 270*724ba675SRob Herring gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 271*724ba675SRob Herring &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 272*724ba675SRob Herring &pmx0 6 11 1 &pmx0 7 11 1>; 273*724ba675SRob Herring interrupt-controller; 274*724ba675SRob Herring #interrupt-cells = <2>; 275*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK3>; 276*724ba675SRob Herring clock-names = "apb_pclk"; 277*724ba675SRob Herring }; 278*724ba675SRob Herring 279*724ba675SRob Herring gpio4: gpio@80a000 { 280*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 281*724ba675SRob Herring reg = <0x80a000 0x1000>; 282*724ba675SRob Herring interrupts = <0 68 0x4>; 283*724ba675SRob Herring gpio-controller; 284*724ba675SRob Herring #gpio-cells = <2>; 285*724ba675SRob Herring gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 286*724ba675SRob Herring &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 287*724ba675SRob Herring &pmx0 6 13 1 &pmx0 7 13 1>; 288*724ba675SRob Herring interrupt-controller; 289*724ba675SRob Herring #interrupt-cells = <2>; 290*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK4>; 291*724ba675SRob Herring clock-names = "apb_pclk"; 292*724ba675SRob Herring }; 293*724ba675SRob Herring 294*724ba675SRob Herring gpio5: gpio@80b000 { 295*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 296*724ba675SRob Herring reg = <0x80b000 0x1000>; 297*724ba675SRob Herring interrupts = <0 69 0x4>; 298*724ba675SRob Herring gpio-controller; 299*724ba675SRob Herring #gpio-cells = <2>; 300*724ba675SRob Herring gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 301*724ba675SRob Herring &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 302*724ba675SRob Herring &pmx0 6 16 1 &pmx0 7 16 1>; 303*724ba675SRob Herring interrupt-controller; 304*724ba675SRob Herring #interrupt-cells = <2>; 305*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK5>; 306*724ba675SRob Herring clock-names = "apb_pclk"; 307*724ba675SRob Herring }; 308*724ba675SRob Herring 309*724ba675SRob Herring gpio6: gpio@80c000 { 310*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 311*724ba675SRob Herring reg = <0x80c000 0x1000>; 312*724ba675SRob Herring interrupts = <0 70 0x4>; 313*724ba675SRob Herring gpio-controller; 314*724ba675SRob Herring #gpio-cells = <2>; 315*724ba675SRob Herring gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 316*724ba675SRob Herring &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 317*724ba675SRob Herring &pmx0 6 18 1 &pmx0 7 19 1>; 318*724ba675SRob Herring interrupt-controller; 319*724ba675SRob Herring #interrupt-cells = <2>; 320*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK6>; 321*724ba675SRob Herring clock-names = "apb_pclk"; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring gpio7: gpio@80d000 { 325*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 326*724ba675SRob Herring reg = <0x80d000 0x1000>; 327*724ba675SRob Herring interrupts = <0 71 0x4>; 328*724ba675SRob Herring gpio-controller; 329*724ba675SRob Herring #gpio-cells = <2>; 330*724ba675SRob Herring gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 331*724ba675SRob Herring &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 332*724ba675SRob Herring &pmx0 6 25 1 &pmx0 7 26 1>; 333*724ba675SRob Herring interrupt-controller; 334*724ba675SRob Herring #interrupt-cells = <2>; 335*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK7>; 336*724ba675SRob Herring clock-names = "apb_pclk"; 337*724ba675SRob Herring }; 338*724ba675SRob Herring 339*724ba675SRob Herring gpio8: gpio@80e000 { 340*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 341*724ba675SRob Herring reg = <0x80e000 0x1000>; 342*724ba675SRob Herring interrupts = <0 72 0x4>; 343*724ba675SRob Herring gpio-controller; 344*724ba675SRob Herring #gpio-cells = <2>; 345*724ba675SRob Herring gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 346*724ba675SRob Herring &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 347*724ba675SRob Herring &pmx0 6 33 1 &pmx0 7 34 1>; 348*724ba675SRob Herring interrupt-controller; 349*724ba675SRob Herring #interrupt-cells = <2>; 350*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK8>; 351*724ba675SRob Herring clock-names = "apb_pclk"; 352*724ba675SRob Herring }; 353*724ba675SRob Herring 354*724ba675SRob Herring gpio9: gpio@80f000 { 355*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 356*724ba675SRob Herring reg = <0x80f000 0x1000>; 357*724ba675SRob Herring interrupts = <0 73 0x4>; 358*724ba675SRob Herring gpio-controller; 359*724ba675SRob Herring #gpio-cells = <2>; 360*724ba675SRob Herring gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 361*724ba675SRob Herring &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 362*724ba675SRob Herring &pmx0 6 41 1>; 363*724ba675SRob Herring interrupt-controller; 364*724ba675SRob Herring #interrupt-cells = <2>; 365*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK9>; 366*724ba675SRob Herring clock-names = "apb_pclk"; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring gpio10: gpio@810000 { 370*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 371*724ba675SRob Herring reg = <0x810000 0x1000>; 372*724ba675SRob Herring interrupts = <0 74 0x4>; 373*724ba675SRob Herring gpio-controller; 374*724ba675SRob Herring #gpio-cells = <2>; 375*724ba675SRob Herring gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 376*724ba675SRob Herring &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; 377*724ba675SRob Herring interrupt-controller; 378*724ba675SRob Herring #interrupt-cells = <2>; 379*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK10>; 380*724ba675SRob Herring clock-names = "apb_pclk"; 381*724ba675SRob Herring }; 382*724ba675SRob Herring 383*724ba675SRob Herring gpio11: gpio@811000 { 384*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 385*724ba675SRob Herring reg = <0x811000 0x1000>; 386*724ba675SRob Herring interrupts = <0 75 0x4>; 387*724ba675SRob Herring gpio-controller; 388*724ba675SRob Herring #gpio-cells = <2>; 389*724ba675SRob Herring gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 390*724ba675SRob Herring &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 391*724ba675SRob Herring &pmx0 6 49 1 &pmx0 7 49 1>; 392*724ba675SRob Herring interrupt-controller; 393*724ba675SRob Herring #interrupt-cells = <2>; 394*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK11>; 395*724ba675SRob Herring clock-names = "apb_pclk"; 396*724ba675SRob Herring }; 397*724ba675SRob Herring 398*724ba675SRob Herring gpio12: gpio@812000 { 399*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 400*724ba675SRob Herring reg = <0x812000 0x1000>; 401*724ba675SRob Herring interrupts = <0 76 0x4>; 402*724ba675SRob Herring gpio-controller; 403*724ba675SRob Herring #gpio-cells = <2>; 404*724ba675SRob Herring gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 405*724ba675SRob Herring &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 406*724ba675SRob Herring &pmx0 6 51 1 &pmx0 7 52 1>; 407*724ba675SRob Herring interrupt-controller; 408*724ba675SRob Herring #interrupt-cells = <2>; 409*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK12>; 410*724ba675SRob Herring clock-names = "apb_pclk"; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring gpio13: gpio@813000 { 414*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 415*724ba675SRob Herring reg = <0x813000 0x1000>; 416*724ba675SRob Herring interrupts = <0 77 0x4>; 417*724ba675SRob Herring gpio-controller; 418*724ba675SRob Herring #gpio-cells = <2>; 419*724ba675SRob Herring gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 420*724ba675SRob Herring &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 421*724ba675SRob Herring &pmx0 6 55 1 &pmx0 7 56 1>; 422*724ba675SRob Herring interrupt-controller; 423*724ba675SRob Herring #interrupt-cells = <2>; 424*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK13>; 425*724ba675SRob Herring clock-names = "apb_pclk"; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring gpio14: gpio@814000 { 429*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 430*724ba675SRob Herring reg = <0x814000 0x1000>; 431*724ba675SRob Herring interrupts = <0 78 0x4>; 432*724ba675SRob Herring gpio-controller; 433*724ba675SRob Herring #gpio-cells = <2>; 434*724ba675SRob Herring gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 435*724ba675SRob Herring &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 436*724ba675SRob Herring &pmx0 6 60 1 &pmx0 7 61 1>; 437*724ba675SRob Herring interrupt-controller; 438*724ba675SRob Herring #interrupt-cells = <2>; 439*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK14>; 440*724ba675SRob Herring clock-names = "apb_pclk"; 441*724ba675SRob Herring }; 442*724ba675SRob Herring 443*724ba675SRob Herring gpio15: gpio@815000 { 444*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 445*724ba675SRob Herring reg = <0x815000 0x1000>; 446*724ba675SRob Herring interrupts = <0 79 0x4>; 447*724ba675SRob Herring gpio-controller; 448*724ba675SRob Herring #gpio-cells = <2>; 449*724ba675SRob Herring gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 450*724ba675SRob Herring &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 451*724ba675SRob Herring &pmx0 6 64 1 &pmx0 7 65 1>; 452*724ba675SRob Herring interrupt-controller; 453*724ba675SRob Herring #interrupt-cells = <2>; 454*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK15>; 455*724ba675SRob Herring clock-names = "apb_pclk"; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring gpio16: gpio@816000 { 459*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 460*724ba675SRob Herring reg = <0x816000 0x1000>; 461*724ba675SRob Herring interrupts = <0 80 0x4>; 462*724ba675SRob Herring gpio-controller; 463*724ba675SRob Herring #gpio-cells = <2>; 464*724ba675SRob Herring gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 465*724ba675SRob Herring &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 466*724ba675SRob Herring &pmx0 6 72 1 &pmx0 7 73 1>; 467*724ba675SRob Herring interrupt-controller; 468*724ba675SRob Herring #interrupt-cells = <2>; 469*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK16>; 470*724ba675SRob Herring clock-names = "apb_pclk"; 471*724ba675SRob Herring }; 472*724ba675SRob Herring 473*724ba675SRob Herring gpio17: gpio@817000 { 474*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 475*724ba675SRob Herring reg = <0x817000 0x1000>; 476*724ba675SRob Herring interrupts = <0 81 0x4>; 477*724ba675SRob Herring gpio-controller; 478*724ba675SRob Herring #gpio-cells = <2>; 479*724ba675SRob Herring gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 480*724ba675SRob Herring &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 481*724ba675SRob Herring &pmx0 6 80 1 &pmx0 7 81 1>; 482*724ba675SRob Herring interrupt-controller; 483*724ba675SRob Herring #interrupt-cells = <2>; 484*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK17>; 485*724ba675SRob Herring clock-names = "apb_pclk"; 486*724ba675SRob Herring }; 487*724ba675SRob Herring 488*724ba675SRob Herring gpio18: gpio@818000 { 489*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 490*724ba675SRob Herring reg = <0x818000 0x1000>; 491*724ba675SRob Herring interrupts = <0 82 0x4>; 492*724ba675SRob Herring gpio-controller; 493*724ba675SRob Herring #gpio-cells = <2>; 494*724ba675SRob Herring gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 495*724ba675SRob Herring &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 496*724ba675SRob Herring &pmx0 6 86 1 &pmx0 7 87 1>; 497*724ba675SRob Herring interrupt-controller; 498*724ba675SRob Herring #interrupt-cells = <2>; 499*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK18>; 500*724ba675SRob Herring clock-names = "apb_pclk"; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring gpio19: gpio@819000 { 504*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 505*724ba675SRob Herring reg = <0x819000 0x1000>; 506*724ba675SRob Herring interrupts = <0 83 0x4>; 507*724ba675SRob Herring gpio-controller; 508*724ba675SRob Herring #gpio-cells = <2>; 509*724ba675SRob Herring gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 510*724ba675SRob Herring &pmx0 3 88 1>; 511*724ba675SRob Herring interrupt-controller; 512*724ba675SRob Herring #interrupt-cells = <2>; 513*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK19>; 514*724ba675SRob Herring clock-names = "apb_pclk"; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring gpio20: gpio@81a000 { 518*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 519*724ba675SRob Herring reg = <0x81a000 0x1000>; 520*724ba675SRob Herring interrupts = <0 84 0x4>; 521*724ba675SRob Herring gpio-controller; 522*724ba675SRob Herring #gpio-cells = <2>; 523*724ba675SRob Herring gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 524*724ba675SRob Herring &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; 525*724ba675SRob Herring interrupt-controller; 526*724ba675SRob Herring #interrupt-cells = <2>; 527*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK20>; 528*724ba675SRob Herring clock-names = "apb_pclk"; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring gpio21: gpio@81b000 { 532*724ba675SRob Herring compatible = "arm,pl061", "arm,primecell"; 533*724ba675SRob Herring reg = <0x81b000 0x1000>; 534*724ba675SRob Herring interrupts = <0 85 0x4>; 535*724ba675SRob Herring gpio-controller; 536*724ba675SRob Herring #gpio-cells = <2>; 537*724ba675SRob Herring gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; 538*724ba675SRob Herring interrupt-controller; 539*724ba675SRob Herring #interrupt-cells = <2>; 540*724ba675SRob Herring clocks = <&clock HI3620_GPIOCLK21>; 541*724ba675SRob Herring clock-names = "apb_pclk"; 542*724ba675SRob Herring }; 543*724ba675SRob Herring 544*724ba675SRob Herring pmx0: pinmux@803000 { 545*724ba675SRob Herring compatible = "pinctrl-single"; 546*724ba675SRob Herring reg = <0x803000 0x188>; 547*724ba675SRob Herring #address-cells = <1>; 548*724ba675SRob Herring #size-cells = <0>; 549*724ba675SRob Herring #pinctrl-cells = <1>; 550*724ba675SRob Herring #gpio-range-cells = <3>; 551*724ba675SRob Herring 552*724ba675SRob Herring pinctrl-single,register-width = <32>; 553*724ba675SRob Herring pinctrl-single,function-mask = <7>; 554*724ba675SRob Herring /* pin base, nr pins & gpio function */ 555*724ba675SRob Herring pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 556*724ba675SRob Herring &range 12 1 0 &range 13 29 1 557*724ba675SRob Herring &range 43 1 0 &range 44 49 1 558*724ba675SRob Herring &range 94 1 1 &range 96 2 1>; 559*724ba675SRob Herring 560*724ba675SRob Herring range: gpio-range { 561*724ba675SRob Herring #pinctrl-single,gpio-range-cells = <3>; 562*724ba675SRob Herring }; 563*724ba675SRob Herring }; 564*724ba675SRob Herring 565*724ba675SRob Herring pmx1: pinmux@803800 { 566*724ba675SRob Herring compatible = "pinconf-single"; 567*724ba675SRob Herring reg = <0x803800 0x2dc>; 568*724ba675SRob Herring #address-cells = <1>; 569*724ba675SRob Herring #size-cells = <0>; 570*724ba675SRob Herring #pinctrl-cells = <1>; 571*724ba675SRob Herring 572*724ba675SRob Herring pinctrl-single,register-width = <32>; 573*724ba675SRob Herring }; 574*724ba675SRob Herring }; 575*724ba675SRob Herring}; 576