1*724ba675SRob Herring/* 2*724ba675SRob Herring * Broadcom BCM470X / BCM5301X ARM platform code. 3*724ba675SRob Herring * DTS for BCM4708 SoC. 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 6*724ba675SRob Herring * 7*724ba675SRob Herring * Licensed under the GNU/GPL. See COPYING for details. 8*724ba675SRob Herring */ 9*724ba675SRob Herring 10*724ba675SRob Herring#include "bcm5301x.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring compatible = "brcm,bcm4708"; 14*724ba675SRob Herring 15*724ba675SRob Herring aliases { 16*724ba675SRob Herring serial0 = &uart0; 17*724ba675SRob Herring }; 18*724ba675SRob Herring 19*724ba675SRob Herring chosen { 20*724ba675SRob Herring stdout-path = "serial0:115200n8"; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring cpus { 24*724ba675SRob Herring #address-cells = <1>; 25*724ba675SRob Herring #size-cells = <0>; 26*724ba675SRob Herring enable-method = "brcm,bcm-nsp-smp"; 27*724ba675SRob Herring 28*724ba675SRob Herring cpu@0 { 29*724ba675SRob Herring device_type = "cpu"; 30*724ba675SRob Herring compatible = "arm,cortex-a9"; 31*724ba675SRob Herring next-level-cache = <&L2>; 32*724ba675SRob Herring reg = <0x0>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring cpu@1 { 36*724ba675SRob Herring device_type = "cpu"; 37*724ba675SRob Herring compatible = "arm,cortex-a9"; 38*724ba675SRob Herring next-level-cache = <&L2>; 39*724ba675SRob Herring secondary-boot-reg = <0xffff0400>; 40*724ba675SRob Herring reg = <0x1>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&uart0 { 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring}; 49