xref: /linux/scripts/dtc/include-prefixes/arm/broadcom/bcm2837.dtsi (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1724ba675SRob Herring#include "bcm283x.dtsi"
2724ba675SRob Herring#include "bcm2835-common.dtsi"
3724ba675SRob Herring
4724ba675SRob Herring/ {
5724ba675SRob Herring	compatible = "brcm,bcm2837";
6724ba675SRob Herring
7724ba675SRob Herring	soc {
8724ba675SRob Herring		ranges = <0x7e000000 0x3f000000 0x1000000>,
9724ba675SRob Herring			 <0x40000000 0x40000000 0x00001000>;
10724ba675SRob Herring		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
11724ba675SRob Herring
12*eb81f43cSStefan Wahren		local_intc: interrupt-controller@40000000 {
13724ba675SRob Herring			compatible = "brcm,bcm2836-l1-intc";
14724ba675SRob Herring			reg = <0x40000000 0x100>;
15724ba675SRob Herring			interrupt-controller;
16724ba675SRob Herring			#interrupt-cells = <2>;
17724ba675SRob Herring			interrupt-parent = <&local_intc>;
18724ba675SRob Herring		};
19724ba675SRob Herring	};
20724ba675SRob Herring
21724ba675SRob Herring	arm-pmu {
22724ba675SRob Herring		compatible = "arm,cortex-a53-pmu";
23724ba675SRob Herring		interrupt-parent = <&local_intc>;
24724ba675SRob Herring		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
25724ba675SRob Herring	};
26724ba675SRob Herring
27724ba675SRob Herring	timer {
28724ba675SRob Herring		compatible = "arm,armv7-timer";
29724ba675SRob Herring		interrupt-parent = <&local_intc>;
30724ba675SRob Herring		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
31724ba675SRob Herring			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
32724ba675SRob Herring			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
33724ba675SRob Herring			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
34724ba675SRob Herring		always-on;
35724ba675SRob Herring	};
36724ba675SRob Herring
37724ba675SRob Herring	cpus: cpus {
38724ba675SRob Herring		#address-cells = <1>;
39724ba675SRob Herring		#size-cells = <0>;
40724ba675SRob Herring		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
41724ba675SRob Herring
42724ba675SRob Herring		/* Source for d/i-cache-line-size and d/i-cache-sets
43724ba675SRob Herring		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
44724ba675SRob Herring		 * /about-the-l1-memory-system?lang=en
45724ba675SRob Herring		 *
46724ba675SRob Herring		 * Source for d/i-cache-size
47724ba675SRob Herring		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
48724ba675SRob Herring		 */
49724ba675SRob Herring		cpu0: cpu@0 {
50724ba675SRob Herring			device_type = "cpu";
51724ba675SRob Herring			compatible = "arm,cortex-a53";
52724ba675SRob Herring			reg = <0>;
53724ba675SRob Herring			enable-method = "spin-table";
54724ba675SRob Herring			cpu-release-addr = <0x0 0x000000d8>;
55724ba675SRob Herring			d-cache-size = <0x8000>;
56724ba675SRob Herring			d-cache-line-size = <64>;
57724ba675SRob Herring			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
58724ba675SRob Herring			i-cache-size = <0x8000>;
59724ba675SRob Herring			i-cache-line-size = <64>;
60724ba675SRob Herring			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
61724ba675SRob Herring			next-level-cache = <&l2>;
62724ba675SRob Herring		};
63724ba675SRob Herring
64724ba675SRob Herring		cpu1: cpu@1 {
65724ba675SRob Herring			device_type = "cpu";
66724ba675SRob Herring			compatible = "arm,cortex-a53";
67724ba675SRob Herring			reg = <1>;
68724ba675SRob Herring			enable-method = "spin-table";
69724ba675SRob Herring			cpu-release-addr = <0x0 0x000000e0>;
70724ba675SRob Herring			d-cache-size = <0x8000>;
71724ba675SRob Herring			d-cache-line-size = <64>;
72724ba675SRob Herring			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
73724ba675SRob Herring			i-cache-size = <0x8000>;
74724ba675SRob Herring			i-cache-line-size = <64>;
75724ba675SRob Herring			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
76724ba675SRob Herring			next-level-cache = <&l2>;
77724ba675SRob Herring		};
78724ba675SRob Herring
79724ba675SRob Herring		cpu2: cpu@2 {
80724ba675SRob Herring			device_type = "cpu";
81724ba675SRob Herring			compatible = "arm,cortex-a53";
82724ba675SRob Herring			reg = <2>;
83724ba675SRob Herring			enable-method = "spin-table";
84724ba675SRob Herring			cpu-release-addr = <0x0 0x000000e8>;
85724ba675SRob Herring			d-cache-size = <0x8000>;
86724ba675SRob Herring			d-cache-line-size = <64>;
87724ba675SRob Herring			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
88724ba675SRob Herring			i-cache-size = <0x8000>;
89724ba675SRob Herring			i-cache-line-size = <64>;
90724ba675SRob Herring			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
91724ba675SRob Herring			next-level-cache = <&l2>;
92724ba675SRob Herring		};
93724ba675SRob Herring
94724ba675SRob Herring		cpu3: cpu@3 {
95724ba675SRob Herring			device_type = "cpu";
96724ba675SRob Herring			compatible = "arm,cortex-a53";
97724ba675SRob Herring			reg = <3>;
98724ba675SRob Herring			enable-method = "spin-table";
99724ba675SRob Herring			cpu-release-addr = <0x0 0x000000f0>;
100724ba675SRob Herring			d-cache-size = <0x8000>;
101724ba675SRob Herring			d-cache-line-size = <64>;
102724ba675SRob Herring			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103724ba675SRob Herring			i-cache-size = <0x8000>;
104724ba675SRob Herring			i-cache-line-size = <64>;
105724ba675SRob Herring			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
106724ba675SRob Herring			next-level-cache = <&l2>;
107724ba675SRob Herring		};
108724ba675SRob Herring
109724ba675SRob Herring		/* Source for cache-line-size + cache-sets
110724ba675SRob Herring		 * https://developer.arm.com/documentation/ddi0500
111724ba675SRob Herring		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
112724ba675SRob Herring		 * Source for cache-size
113724ba675SRob Herring		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
114724ba675SRob Herring		 */
115724ba675SRob Herring		l2: l2-cache0 {
116724ba675SRob Herring			compatible = "cache";
117724ba675SRob Herring			cache-unified;
118724ba675SRob Herring			cache-size = <0x80000>;
119724ba675SRob Herring			cache-line-size = <64>;
120724ba675SRob Herring			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
121724ba675SRob Herring			cache-level = <2>;
122724ba675SRob Herring		};
123724ba675SRob Herring	};
124724ba675SRob Herring};
125724ba675SRob Herring
126724ba675SRob Herring/* Make the BCM2835-style global interrupt controller be a child of the
127724ba675SRob Herring * CPU-local interrupt controller.
128724ba675SRob Herring */
129724ba675SRob Herring&intc {
130724ba675SRob Herring	compatible = "brcm,bcm2836-armctrl-ic";
131724ba675SRob Herring	reg = <0x7e00b200 0x200>;
132724ba675SRob Herring	interrupt-parent = <&local_intc>;
133724ba675SRob Herring	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
134724ba675SRob Herring};
135724ba675SRob Herring
136724ba675SRob Herring&cpu_thermal {
137724ba675SRob Herring	coefficients = <(-538)	412000>;
138724ba675SRob Herring};
139724ba675SRob Herring
140724ba675SRob Herring/* enable thermal sensor with the correct compatible property set */
141724ba675SRob Herring&thermal {
142724ba675SRob Herring	compatible = "brcm,bcm2837-thermal";
143724ba675SRob Herring	status = "okay";
144724ba675SRob Herring};
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