1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/clock/aspeed-clock.h> 3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2500"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&vic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &vuart; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm1176jzf-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x80000000 0>; 49 }; 50 51 ahb { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 fmc: spi@1e620000 { 58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 compatible = "aspeed,ast2500-fmc"; 62 clocks = <&syscon ASPEED_CLK_AHB>; 63 status = "disabled"; 64 interrupts = <19>; 65 flash@0 { 66 reg = < 0 >; 67 compatible = "jedec,spi-nor"; 68 spi-max-frequency = <50000000>; 69 spi-rx-bus-width = <2>; 70 status = "disabled"; 71 }; 72 flash@1 { 73 reg = < 1 >; 74 compatible = "jedec,spi-nor"; 75 spi-max-frequency = <50000000>; 76 spi-rx-bus-width = <2>; 77 status = "disabled"; 78 }; 79 flash@2 { 80 reg = < 2 >; 81 compatible = "jedec,spi-nor"; 82 spi-max-frequency = <50000000>; 83 spi-rx-bus-width = <2>; 84 status = "disabled"; 85 }; 86 }; 87 88 spi1: spi@1e630000 { 89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 compatible = "aspeed,ast2500-spi"; 93 clocks = <&syscon ASPEED_CLK_AHB>; 94 status = "disabled"; 95 flash@0 { 96 reg = < 0 >; 97 compatible = "jedec,spi-nor"; 98 spi-max-frequency = <50000000>; 99 spi-rx-bus-width = <2>; 100 status = "disabled"; 101 }; 102 flash@1 { 103 reg = < 1 >; 104 compatible = "jedec,spi-nor"; 105 spi-max-frequency = <50000000>; 106 spi-rx-bus-width = <2>; 107 status = "disabled"; 108 }; 109 }; 110 111 spi2: spi@1e631000 { 112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 compatible = "aspeed,ast2500-spi"; 116 clocks = <&syscon ASPEED_CLK_AHB>; 117 status = "disabled"; 118 flash@0 { 119 reg = < 0 >; 120 compatible = "jedec,spi-nor"; 121 spi-max-frequency = <50000000>; 122 spi-rx-bus-width = <2>; 123 status = "disabled"; 124 }; 125 flash@1 { 126 reg = < 1 >; 127 compatible = "jedec,spi-nor"; 128 spi-max-frequency = <50000000>; 129 spi-rx-bus-width = <2>; 130 status = "disabled"; 131 }; 132 }; 133 134 vic: interrupt-controller@1e6c0080 { 135 compatible = "aspeed,ast2400-vic"; 136 interrupt-controller; 137 #interrupt-cells = <1>; 138 valid-sources = <0xfefff7ff 0x0807ffff>; 139 reg = <0x1e6c0080 0x80>; 140 }; 141 142 cvic: interrupt-controller@1e6c2000 { 143 compatible = "aspeed,ast2500-cvic", "aspeed,cvic"; 144 valid-sources = <0xffffffff>; 145 copro-sw-interrupts = <1>; 146 reg = <0x1e6c2000 0x80>; 147 }; 148 149 mac0: ethernet@1e660000 { 150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 151 reg = <0x1e660000 0x180>; 152 interrupts = <2>; 153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 154 status = "disabled"; 155 }; 156 157 mac1: ethernet@1e680000 { 158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 159 reg = <0x1e680000 0x180>; 160 interrupts = <3>; 161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 162 status = "disabled"; 163 }; 164 165 ehci0: usb@1e6a1000 { 166 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 167 reg = <0x1e6a1000 0x100>; 168 interrupts = <5>; 169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_usb2ah_default>; 172 status = "disabled"; 173 }; 174 175 ehci1: usb@1e6a3000 { 176 compatible = "aspeed,ast2500-ehci", "generic-ehci"; 177 reg = <0x1e6a3000 0x100>; 178 interrupts = <13>; 179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_usb2bh_default>; 182 status = "disabled"; 183 }; 184 185 uhci: usb@1e6b0000 { 186 compatible = "aspeed,ast2500-uhci", "generic-uhci"; 187 reg = <0x1e6b0000 0x100>; 188 interrupts = <14>; 189 #ports = <2>; 190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 191 status = "disabled"; 192 /* 193 * No default pinmux, it will follow EHCI, use an explicit pinmux 194 * override if you don't enable EHCI 195 */ 196 }; 197 198 vhub: usb-vhub@1e6a0000 { 199 compatible = "aspeed,ast2500-usb-vhub"; 200 reg = <0x1e6a0000 0x300>; 201 interrupts = <5>; 202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 203 aspeed,vhub-downstream-ports = <5>; 204 aspeed,vhub-generic-endpoints = <15>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_usb2ad_default>; 207 status = "disabled"; 208 }; 209 210 apb { 211 compatible = "simple-bus"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges; 215 216 edac: memory-controller@1e6e0000 { 217 compatible = "aspeed,ast2500-sdram-edac"; 218 reg = <0x1e6e0000 0x174>; 219 interrupts = <0>; 220 status = "disabled"; 221 }; 222 223 syscon: syscon@1e6e2000 { 224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; 225 reg = <0x1e6e2000 0x1a8>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0 0x1e6e2000 0x1000>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 232 scu_ic: interrupt-controller@18 { 233 #interrupt-cells = <1>; 234 compatible = "aspeed,ast2500-scu-ic"; 235 reg = <0x18 0x4>; 236 interrupts = <21>; 237 interrupt-controller; 238 }; 239 240 p2a: p2a-control@2c { 241 compatible = "aspeed,ast2500-p2a-ctrl"; 242 reg = <0x2c 0x4>; 243 status = "disabled"; 244 }; 245 246 silicon-id@7c { 247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; 248 reg = <0x7c 0x4 0x150 0x8>; 249 }; 250 251 pinctrl: pinctrl@80 { 252 compatible = "aspeed,ast2500-pinctrl"; 253 reg = <0x80 0x18>, <0xa0 0x10>; 254 aspeed,external-nodes = <&gfx>, <&lhc>; 255 }; 256 }; 257 258 rng: hwrng@1e6e2078 { 259 compatible = "timeriomem_rng"; 260 reg = <0x1e6e2078 0x4>; 261 period = <1>; 262 quality = <100>; 263 }; 264 265 hace: crypto@1e6e3000 { 266 compatible = "aspeed,ast2500-hace"; 267 reg = <0x1e6e3000 0x100>; 268 interrupts = <4>; 269 clocks = <&syscon ASPEED_CLK_GATE_YCLK>; 270 resets = <&syscon ASPEED_RESET_HACE>; 271 }; 272 273 gfx: display@1e6e6000 { 274 compatible = "aspeed,ast2500-gfx", "syscon"; 275 reg = <0x1e6e6000 0x1000>; 276 reg-io-width = <4>; 277 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 278 resets = <&syscon ASPEED_RESET_CRT1>; 279 syscon = <&syscon>; 280 status = "disabled"; 281 interrupts = <0x19>; 282 }; 283 284 adc: adc@1e6e9000 { 285 compatible = "aspeed,ast2500-adc"; 286 reg = <0x1e6e9000 0xb0>; 287 clocks = <&syscon ASPEED_CLK_APB>; 288 resets = <&syscon ASPEED_RESET_ADC>; 289 #io-channel-cells = <1>; 290 status = "disabled"; 291 }; 292 293 video: video@1e700000 { 294 compatible = "aspeed,ast2500-video-engine"; 295 reg = <0x1e700000 0x1000>; 296 clocks = <&syscon ASPEED_CLK_GATE_VCLK>, 297 <&syscon ASPEED_CLK_GATE_ECLK>; 298 clock-names = "vclk", "eclk"; 299 interrupts = <7>; 300 status = "disabled"; 301 }; 302 303 sram: sram@1e720000 { 304 compatible = "mmio-sram"; 305 reg = <0x1e720000 0x9000>; // 36K 306 ranges; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 }; 310 311 sdmmc: sd-controller@1e740000 { 312 compatible = "aspeed,ast2500-sd-controller"; 313 reg = <0x1e740000 0x100>; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 ranges = <0 0x1e740000 0x10000>; 317 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 318 status = "disabled"; 319 320 sdhci0: sdhci@100 { 321 compatible = "aspeed,ast2500-sdhci"; 322 reg = <0x100 0x100>; 323 interrupts = <26>; 324 sdhci,auto-cmd12; 325 clocks = <&syscon ASPEED_CLK_SDIO>; 326 status = "disabled"; 327 }; 328 329 sdhci1: sdhci@200 { 330 compatible = "aspeed,ast2500-sdhci"; 331 reg = <0x200 0x100>; 332 interrupts = <26>; 333 sdhci,auto-cmd12; 334 clocks = <&syscon ASPEED_CLK_SDIO>; 335 status = "disabled"; 336 }; 337 }; 338 339 gpio: gpio@1e780000 { 340 #gpio-cells = <2>; 341 gpio-controller; 342 compatible = "aspeed,ast2500-gpio"; 343 reg = <0x1e780000 0x200>; 344 interrupts = <20>; 345 gpio-ranges = <&pinctrl 0 0 232>; 346 clocks = <&syscon ASPEED_CLK_APB>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 }; 350 351 sgpio: sgpio@1e780200 { 352 #gpio-cells = <2>; 353 compatible = "aspeed,ast2500-sgpio"; 354 gpio-controller; 355 interrupts = <40>; 356 reg = <0x1e780200 0x0100>; 357 clocks = <&syscon ASPEED_CLK_APB>; 358 #interrupt-cells = <2>; 359 interrupt-controller; 360 bus-frequency = <12000000>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_sgpm_default>; 363 status = "disabled"; 364 }; 365 366 rtc: rtc@1e781000 { 367 compatible = "aspeed,ast2500-rtc"; 368 reg = <0x1e781000 0x18>; 369 status = "disabled"; 370 }; 371 372 timer: timer@1e782000 { 373 /* This timer is a Faraday FTTMR010 derivative */ 374 compatible = "aspeed,ast2400-timer"; 375 reg = <0x1e782000 0x90>; 376 interrupts = <16 17 18 35 36 37 38 39>; 377 clocks = <&syscon ASPEED_CLK_APB>; 378 clock-names = "PCLK"; 379 }; 380 381 uart1: serial@1e783000 { 382 compatible = "ns16550a"; 383 reg = <0x1e783000 0x20>; 384 reg-shift = <2>; 385 interrupts = <9>; 386 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 387 resets = <&lpc_reset 4>; 388 no-loopback-test; 389 status = "disabled"; 390 }; 391 392 uart5: serial@1e784000 { 393 compatible = "ns16550a"; 394 reg = <0x1e784000 0x20>; 395 reg-shift = <2>; 396 interrupts = <10>; 397 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 398 no-loopback-test; 399 status = "disabled"; 400 }; 401 402 wdt1: watchdog@1e785000 { 403 compatible = "aspeed,ast2500-wdt"; 404 reg = <0x1e785000 0x20>; 405 clocks = <&syscon ASPEED_CLK_APB>; 406 }; 407 408 wdt2: watchdog@1e785020 { 409 compatible = "aspeed,ast2500-wdt"; 410 reg = <0x1e785020 0x20>; 411 clocks = <&syscon ASPEED_CLK_APB>; 412 }; 413 414 wdt3: watchdog@1e785040 { 415 compatible = "aspeed,ast2500-wdt"; 416 reg = <0x1e785040 0x20>; 417 clocks = <&syscon ASPEED_CLK_APB>; 418 status = "disabled"; 419 }; 420 421 pwm_tacho: pwm-tacho-controller@1e786000 { 422 compatible = "aspeed,ast2500-pwm-tacho"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 reg = <0x1e786000 0x1000>; 426 clocks = <&syscon ASPEED_CLK_24M>; 427 resets = <&syscon ASPEED_RESET_PWM>; 428 status = "disabled"; 429 }; 430 431 vuart: serial@1e787000 { 432 compatible = "aspeed,ast2500-vuart"; 433 reg = <0x1e787000 0x40>; 434 reg-shift = <2>; 435 interrupts = <8>; 436 clocks = <&syscon ASPEED_CLK_APB>; 437 no-loopback-test; 438 status = "disabled"; 439 }; 440 441 lpc: lpc@1e789000 { 442 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; 443 reg = <0x1e789000 0x1000>; 444 reg-io-width = <4>; 445 446 #address-cells = <1>; 447 #size-cells = <1>; 448 ranges = <0x0 0x1e789000 0x1000>; 449 450 kcs1: kcs@24 { 451 compatible = "aspeed,ast2500-kcs-bmc-v2"; 452 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 453 interrupts = <8>; 454 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 455 status = "disabled"; 456 }; 457 458 kcs2: kcs@28 { 459 compatible = "aspeed,ast2500-kcs-bmc-v2"; 460 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 461 interrupts = <8>; 462 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 463 status = "disabled"; 464 }; 465 466 kcs3: kcs@2c { 467 compatible = "aspeed,ast2500-kcs-bmc-v2"; 468 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 469 interrupts = <8>; 470 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 471 status = "disabled"; 472 }; 473 474 kcs4: kcs@114 { 475 compatible = "aspeed,ast2500-kcs-bmc-v2"; 476 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; 477 interrupts = <8>; 478 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 479 status = "disabled"; 480 }; 481 482 lpc_ctrl: lpc-ctrl@80 { 483 compatible = "aspeed,ast2500-lpc-ctrl"; 484 reg = <0x80 0x10>; 485 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 486 status = "disabled"; 487 }; 488 489 lpc_snoop: lpc-snoop@90 { 490 compatible = "aspeed,ast2500-lpc-snoop"; 491 reg = <0x90 0x8>; 492 interrupts = <8>; 493 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 494 status = "disabled"; 495 }; 496 497 lpc_reset: reset-controller@98 { 498 compatible = "aspeed,ast2500-lpc-reset"; 499 reg = <0x98 0x4>; 500 #reset-cells = <1>; 501 }; 502 503 uart_routing: uart-routing@9c { 504 compatible = "aspeed,ast2500-uart-routing"; 505 reg = <0x9c 0x4>; 506 status = "disabled"; 507 }; 508 509 lhc: lhc@a0 { 510 compatible = "aspeed,ast2500-lhc"; 511 reg = <0xa0 0x24 0xc8 0x8>; 512 }; 513 514 515 ibt: ibt@140 { 516 compatible = "aspeed,ast2500-ibt-bmc"; 517 reg = <0x140 0x18>; 518 interrupts = <8>; 519 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 520 status = "disabled"; 521 }; 522 }; 523 524 peci0: peci-controller@1e78b000 { 525 compatible = "aspeed,ast2500-peci"; 526 reg = <0x1e78b000 0x60>; 527 interrupts = <15>; 528 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; 529 resets = <&syscon ASPEED_RESET_PECI>; 530 cmd-timeout-ms = <1000>; 531 clock-frequency = <1000000>; 532 status = "disabled"; 533 }; 534 535 uart2: serial@1e78d000 { 536 compatible = "ns16550a"; 537 reg = <0x1e78d000 0x20>; 538 reg-shift = <2>; 539 interrupts = <32>; 540 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 541 resets = <&lpc_reset 5>; 542 no-loopback-test; 543 status = "disabled"; 544 }; 545 546 uart3: serial@1e78e000 { 547 compatible = "ns16550a"; 548 reg = <0x1e78e000 0x20>; 549 reg-shift = <2>; 550 interrupts = <33>; 551 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 552 resets = <&lpc_reset 6>; 553 no-loopback-test; 554 status = "disabled"; 555 }; 556 557 uart4: serial@1e78f000 { 558 compatible = "ns16550a"; 559 reg = <0x1e78f000 0x20>; 560 reg-shift = <2>; 561 interrupts = <34>; 562 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 563 resets = <&lpc_reset 7>; 564 no-loopback-test; 565 status = "disabled"; 566 }; 567 568 i2c: bus@1e78a000 { 569 compatible = "simple-bus"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges = <0 0x1e78a000 0x1000>; 573 }; 574 }; 575 }; 576}; 577 578&i2c { 579 i2c_ic: interrupt-controller@0 { 580 #interrupt-cells = <1>; 581 compatible = "aspeed,ast2500-i2c-ic"; 582 reg = <0x0 0x40>; 583 interrupts = <12>; 584 interrupt-controller; 585 }; 586 587 i2c0: i2c@40 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 591 reg = <0x40 0x40>; 592 compatible = "aspeed,ast2500-i2c-bus"; 593 clocks = <&syscon ASPEED_CLK_APB>; 594 resets = <&syscon ASPEED_RESET_I2C>; 595 bus-frequency = <100000>; 596 interrupts = <0>; 597 interrupt-parent = <&i2c_ic>; 598 status = "disabled"; 599 /* Does not need pinctrl properties */ 600 }; 601 602 i2c1: i2c@80 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 606 reg = <0x80 0x40>; 607 compatible = "aspeed,ast2500-i2c-bus"; 608 clocks = <&syscon ASPEED_CLK_APB>; 609 resets = <&syscon ASPEED_RESET_I2C>; 610 bus-frequency = <100000>; 611 interrupts = <1>; 612 interrupt-parent = <&i2c_ic>; 613 status = "disabled"; 614 /* Does not need pinctrl properties */ 615 }; 616 617 i2c2: i2c@c0 { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 621 reg = <0xc0 0x40>; 622 compatible = "aspeed,ast2500-i2c-bus"; 623 clocks = <&syscon ASPEED_CLK_APB>; 624 resets = <&syscon ASPEED_RESET_I2C>; 625 bus-frequency = <100000>; 626 interrupts = <2>; 627 interrupt-parent = <&i2c_ic>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&pinctrl_i2c3_default>; 630 status = "disabled"; 631 }; 632 633 i2c3: i2c@100 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 637 reg = <0x100 0x40>; 638 compatible = "aspeed,ast2500-i2c-bus"; 639 clocks = <&syscon ASPEED_CLK_APB>; 640 resets = <&syscon ASPEED_RESET_I2C>; 641 bus-frequency = <100000>; 642 interrupts = <3>; 643 interrupt-parent = <&i2c_ic>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_i2c4_default>; 646 status = "disabled"; 647 }; 648 649 i2c4: i2c@140 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 653 reg = <0x140 0x40>; 654 compatible = "aspeed,ast2500-i2c-bus"; 655 clocks = <&syscon ASPEED_CLK_APB>; 656 resets = <&syscon ASPEED_RESET_I2C>; 657 bus-frequency = <100000>; 658 interrupts = <4>; 659 interrupt-parent = <&i2c_ic>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_i2c5_default>; 662 status = "disabled"; 663 }; 664 665 i2c5: i2c@180 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 669 reg = <0x180 0x40>; 670 compatible = "aspeed,ast2500-i2c-bus"; 671 clocks = <&syscon ASPEED_CLK_APB>; 672 resets = <&syscon ASPEED_RESET_I2C>; 673 bus-frequency = <100000>; 674 interrupts = <5>; 675 interrupt-parent = <&i2c_ic>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&pinctrl_i2c6_default>; 678 status = "disabled"; 679 }; 680 681 i2c6: i2c@1c0 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 685 reg = <0x1c0 0x40>; 686 compatible = "aspeed,ast2500-i2c-bus"; 687 clocks = <&syscon ASPEED_CLK_APB>; 688 resets = <&syscon ASPEED_RESET_I2C>; 689 bus-frequency = <100000>; 690 interrupts = <6>; 691 interrupt-parent = <&i2c_ic>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pinctrl_i2c7_default>; 694 status = "disabled"; 695 }; 696 697 i2c7: i2c@300 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 701 reg = <0x300 0x40>; 702 compatible = "aspeed,ast2500-i2c-bus"; 703 clocks = <&syscon ASPEED_CLK_APB>; 704 resets = <&syscon ASPEED_RESET_I2C>; 705 bus-frequency = <100000>; 706 interrupts = <7>; 707 interrupt-parent = <&i2c_ic>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pinctrl_i2c8_default>; 710 status = "disabled"; 711 }; 712 713 i2c8: i2c@340 { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 reg = <0x340 0x40>; 718 compatible = "aspeed,ast2500-i2c-bus"; 719 clocks = <&syscon ASPEED_CLK_APB>; 720 resets = <&syscon ASPEED_RESET_I2C>; 721 bus-frequency = <100000>; 722 interrupts = <8>; 723 interrupt-parent = <&i2c_ic>; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&pinctrl_i2c9_default>; 726 status = "disabled"; 727 }; 728 729 i2c9: i2c@380 { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 reg = <0x380 0x40>; 734 compatible = "aspeed,ast2500-i2c-bus"; 735 clocks = <&syscon ASPEED_CLK_APB>; 736 resets = <&syscon ASPEED_RESET_I2C>; 737 bus-frequency = <100000>; 738 interrupts = <9>; 739 interrupt-parent = <&i2c_ic>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&pinctrl_i2c10_default>; 742 status = "disabled"; 743 }; 744 745 i2c10: i2c@3c0 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 reg = <0x3c0 0x40>; 750 compatible = "aspeed,ast2500-i2c-bus"; 751 clocks = <&syscon ASPEED_CLK_APB>; 752 resets = <&syscon ASPEED_RESET_I2C>; 753 bus-frequency = <100000>; 754 interrupts = <10>; 755 interrupt-parent = <&i2c_ic>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&pinctrl_i2c11_default>; 758 status = "disabled"; 759 }; 760 761 i2c11: i2c@400 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 765 reg = <0x400 0x40>; 766 compatible = "aspeed,ast2500-i2c-bus"; 767 clocks = <&syscon ASPEED_CLK_APB>; 768 resets = <&syscon ASPEED_RESET_I2C>; 769 bus-frequency = <100000>; 770 interrupts = <11>; 771 interrupt-parent = <&i2c_ic>; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&pinctrl_i2c12_default>; 774 status = "disabled"; 775 }; 776 777 i2c12: i2c@440 { 778 #address-cells = <1>; 779 #size-cells = <0>; 780 781 reg = <0x440 0x40>; 782 compatible = "aspeed,ast2500-i2c-bus"; 783 clocks = <&syscon ASPEED_CLK_APB>; 784 resets = <&syscon ASPEED_RESET_I2C>; 785 bus-frequency = <100000>; 786 interrupts = <12>; 787 interrupt-parent = <&i2c_ic>; 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_i2c13_default>; 790 status = "disabled"; 791 }; 792 793 i2c13: i2c@480 { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 797 reg = <0x480 0x40>; 798 compatible = "aspeed,ast2500-i2c-bus"; 799 clocks = <&syscon ASPEED_CLK_APB>; 800 resets = <&syscon ASPEED_RESET_I2C>; 801 bus-frequency = <100000>; 802 interrupts = <13>; 803 interrupt-parent = <&i2c_ic>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&pinctrl_i2c14_default>; 806 status = "disabled"; 807 }; 808}; 809 810&pinctrl { 811 pinctrl_acpi_default: acpi_default { 812 function = "ACPI"; 813 groups = "ACPI"; 814 }; 815 816 pinctrl_adc0_default: adc0_default { 817 function = "ADC0"; 818 groups = "ADC0"; 819 }; 820 821 pinctrl_adc1_default: adc1_default { 822 function = "ADC1"; 823 groups = "ADC1"; 824 }; 825 826 pinctrl_adc10_default: adc10_default { 827 function = "ADC10"; 828 groups = "ADC10"; 829 }; 830 831 pinctrl_adc11_default: adc11_default { 832 function = "ADC11"; 833 groups = "ADC11"; 834 }; 835 836 pinctrl_adc12_default: adc12_default { 837 function = "ADC12"; 838 groups = "ADC12"; 839 }; 840 841 pinctrl_adc13_default: adc13_default { 842 function = "ADC13"; 843 groups = "ADC13"; 844 }; 845 846 pinctrl_adc14_default: adc14_default { 847 function = "ADC14"; 848 groups = "ADC14"; 849 }; 850 851 pinctrl_adc15_default: adc15_default { 852 function = "ADC15"; 853 groups = "ADC15"; 854 }; 855 856 pinctrl_adc2_default: adc2_default { 857 function = "ADC2"; 858 groups = "ADC2"; 859 }; 860 861 pinctrl_adc3_default: adc3_default { 862 function = "ADC3"; 863 groups = "ADC3"; 864 }; 865 866 pinctrl_adc4_default: adc4_default { 867 function = "ADC4"; 868 groups = "ADC4"; 869 }; 870 871 pinctrl_adc5_default: adc5_default { 872 function = "ADC5"; 873 groups = "ADC5"; 874 }; 875 876 pinctrl_adc6_default: adc6_default { 877 function = "ADC6"; 878 groups = "ADC6"; 879 }; 880 881 pinctrl_adc7_default: adc7_default { 882 function = "ADC7"; 883 groups = "ADC7"; 884 }; 885 886 pinctrl_adc8_default: adc8_default { 887 function = "ADC8"; 888 groups = "ADC8"; 889 }; 890 891 pinctrl_adc9_default: adc9_default { 892 function = "ADC9"; 893 groups = "ADC9"; 894 }; 895 896 pinctrl_bmcint_default: bmcint_default { 897 function = "BMCINT"; 898 groups = "BMCINT"; 899 }; 900 901 pinctrl_ddcclk_default: ddcclk_default { 902 function = "DDCCLK"; 903 groups = "DDCCLK"; 904 }; 905 906 pinctrl_ddcdat_default: ddcdat_default { 907 function = "DDCDAT"; 908 groups = "DDCDAT"; 909 }; 910 911 pinctrl_espi_default: espi_default { 912 function = "ESPI"; 913 groups = "ESPI"; 914 }; 915 916 pinctrl_fwspics1_default: fwspics1_default { 917 function = "FWSPICS1"; 918 groups = "FWSPICS1"; 919 }; 920 921 pinctrl_fwspics2_default: fwspics2_default { 922 function = "FWSPICS2"; 923 groups = "FWSPICS2"; 924 }; 925 926 pinctrl_gpid0_default: gpid0_default { 927 function = "GPID0"; 928 groups = "GPID0"; 929 }; 930 931 pinctrl_gpid2_default: gpid2_default { 932 function = "GPID2"; 933 groups = "GPID2"; 934 }; 935 936 pinctrl_gpid4_default: gpid4_default { 937 function = "GPID4"; 938 groups = "GPID4"; 939 }; 940 941 pinctrl_gpid6_default: gpid6_default { 942 function = "GPID6"; 943 groups = "GPID6"; 944 }; 945 946 pinctrl_gpie0_default: gpie0_default { 947 function = "GPIE0"; 948 groups = "GPIE0"; 949 }; 950 951 pinctrl_gpie2_default: gpie2_default { 952 function = "GPIE2"; 953 groups = "GPIE2"; 954 }; 955 956 pinctrl_gpie4_default: gpie4_default { 957 function = "GPIE4"; 958 groups = "GPIE4"; 959 }; 960 961 pinctrl_gpie6_default: gpie6_default { 962 function = "GPIE6"; 963 groups = "GPIE6"; 964 }; 965 966 pinctrl_i2c10_default: i2c10_default { 967 function = "I2C10"; 968 groups = "I2C10"; 969 }; 970 971 pinctrl_i2c11_default: i2c11_default { 972 function = "I2C11"; 973 groups = "I2C11"; 974 }; 975 976 pinctrl_i2c12_default: i2c12_default { 977 function = "I2C12"; 978 groups = "I2C12"; 979 }; 980 981 pinctrl_i2c13_default: i2c13_default { 982 function = "I2C13"; 983 groups = "I2C13"; 984 }; 985 986 pinctrl_i2c14_default: i2c14_default { 987 function = "I2C14"; 988 groups = "I2C14"; 989 }; 990 991 pinctrl_i2c3_default: i2c3_default { 992 function = "I2C3"; 993 groups = "I2C3"; 994 }; 995 996 pinctrl_i2c4_default: i2c4_default { 997 function = "I2C4"; 998 groups = "I2C4"; 999 }; 1000 1001 pinctrl_i2c5_default: i2c5_default { 1002 function = "I2C5"; 1003 groups = "I2C5"; 1004 }; 1005 1006 pinctrl_i2c6_default: i2c6_default { 1007 function = "I2C6"; 1008 groups = "I2C6"; 1009 }; 1010 1011 pinctrl_i2c7_default: i2c7_default { 1012 function = "I2C7"; 1013 groups = "I2C7"; 1014 }; 1015 1016 pinctrl_i2c8_default: i2c8_default { 1017 function = "I2C8"; 1018 groups = "I2C8"; 1019 }; 1020 1021 pinctrl_i2c9_default: i2c9_default { 1022 function = "I2C9"; 1023 groups = "I2C9"; 1024 }; 1025 1026 pinctrl_lad0_default: lad0_default { 1027 function = "LAD0"; 1028 groups = "LAD0"; 1029 }; 1030 1031 pinctrl_lad1_default: lad1_default { 1032 function = "LAD1"; 1033 groups = "LAD1"; 1034 }; 1035 1036 pinctrl_lad2_default: lad2_default { 1037 function = "LAD2"; 1038 groups = "LAD2"; 1039 }; 1040 1041 pinctrl_lad3_default: lad3_default { 1042 function = "LAD3"; 1043 groups = "LAD3"; 1044 }; 1045 1046 pinctrl_lclk_default: lclk_default { 1047 function = "LCLK"; 1048 groups = "LCLK"; 1049 }; 1050 1051 pinctrl_lframe_default: lframe_default { 1052 function = "LFRAME"; 1053 groups = "LFRAME"; 1054 }; 1055 1056 pinctrl_lpchc_default: lpchc_default { 1057 function = "LPCHC"; 1058 groups = "LPCHC"; 1059 }; 1060 1061 pinctrl_lpcpd_default: lpcpd_default { 1062 function = "LPCPD"; 1063 groups = "LPCPD"; 1064 }; 1065 1066 pinctrl_lpcplus_default: lpcplus_default { 1067 function = "LPCPLUS"; 1068 groups = "LPCPLUS"; 1069 }; 1070 1071 pinctrl_lpcpme_default: lpcpme_default { 1072 function = "LPCPME"; 1073 groups = "LPCPME"; 1074 }; 1075 1076 pinctrl_lpcrst_default: lpcrst_default { 1077 function = "LPCRST"; 1078 groups = "LPCRST"; 1079 }; 1080 1081 pinctrl_lpcsmi_default: lpcsmi_default { 1082 function = "LPCSMI"; 1083 groups = "LPCSMI"; 1084 }; 1085 1086 pinctrl_lsirq_default: lsirq_default { 1087 function = "LSIRQ"; 1088 groups = "LSIRQ"; 1089 }; 1090 1091 pinctrl_mac1link_default: mac1link_default { 1092 function = "MAC1LINK"; 1093 groups = "MAC1LINK"; 1094 }; 1095 1096 pinctrl_mac2link_default: mac2link_default { 1097 function = "MAC2LINK"; 1098 groups = "MAC2LINK"; 1099 }; 1100 1101 pinctrl_mdio1_default: mdio1_default { 1102 function = "MDIO1"; 1103 groups = "MDIO1"; 1104 }; 1105 1106 pinctrl_mdio2_default: mdio2_default { 1107 function = "MDIO2"; 1108 groups = "MDIO2"; 1109 }; 1110 1111 pinctrl_ncts1_default: ncts1_default { 1112 function = "NCTS1"; 1113 groups = "NCTS1"; 1114 }; 1115 1116 pinctrl_ncts2_default: ncts2_default { 1117 function = "NCTS2"; 1118 groups = "NCTS2"; 1119 }; 1120 1121 pinctrl_ncts3_default: ncts3_default { 1122 function = "NCTS3"; 1123 groups = "NCTS3"; 1124 }; 1125 1126 pinctrl_ncts4_default: ncts4_default { 1127 function = "NCTS4"; 1128 groups = "NCTS4"; 1129 }; 1130 1131 pinctrl_ndcd1_default: ndcd1_default { 1132 function = "NDCD1"; 1133 groups = "NDCD1"; 1134 }; 1135 1136 pinctrl_ndcd2_default: ndcd2_default { 1137 function = "NDCD2"; 1138 groups = "NDCD2"; 1139 }; 1140 1141 pinctrl_ndcd3_default: ndcd3_default { 1142 function = "NDCD3"; 1143 groups = "NDCD3"; 1144 }; 1145 1146 pinctrl_ndcd4_default: ndcd4_default { 1147 function = "NDCD4"; 1148 groups = "NDCD4"; 1149 }; 1150 1151 pinctrl_ndsr1_default: ndsr1_default { 1152 function = "NDSR1"; 1153 groups = "NDSR1"; 1154 }; 1155 1156 pinctrl_ndsr2_default: ndsr2_default { 1157 function = "NDSR2"; 1158 groups = "NDSR2"; 1159 }; 1160 1161 pinctrl_ndsr3_default: ndsr3_default { 1162 function = "NDSR3"; 1163 groups = "NDSR3"; 1164 }; 1165 1166 pinctrl_ndsr4_default: ndsr4_default { 1167 function = "NDSR4"; 1168 groups = "NDSR4"; 1169 }; 1170 1171 pinctrl_ndtr1_default: ndtr1_default { 1172 function = "NDTR1"; 1173 groups = "NDTR1"; 1174 }; 1175 1176 pinctrl_ndtr2_default: ndtr2_default { 1177 function = "NDTR2"; 1178 groups = "NDTR2"; 1179 }; 1180 1181 pinctrl_ndtr3_default: ndtr3_default { 1182 function = "NDTR3"; 1183 groups = "NDTR3"; 1184 }; 1185 1186 pinctrl_ndtr4_default: ndtr4_default { 1187 function = "NDTR4"; 1188 groups = "NDTR4"; 1189 }; 1190 1191 pinctrl_nri1_default: nri1_default { 1192 function = "NRI1"; 1193 groups = "NRI1"; 1194 }; 1195 1196 pinctrl_nri2_default: nri2_default { 1197 function = "NRI2"; 1198 groups = "NRI2"; 1199 }; 1200 1201 pinctrl_nri3_default: nri3_default { 1202 function = "NRI3"; 1203 groups = "NRI3"; 1204 }; 1205 1206 pinctrl_nri4_default: nri4_default { 1207 function = "NRI4"; 1208 groups = "NRI4"; 1209 }; 1210 1211 pinctrl_nrts1_default: nrts1_default { 1212 function = "NRTS1"; 1213 groups = "NRTS1"; 1214 }; 1215 1216 pinctrl_nrts2_default: nrts2_default { 1217 function = "NRTS2"; 1218 groups = "NRTS2"; 1219 }; 1220 1221 pinctrl_nrts3_default: nrts3_default { 1222 function = "NRTS3"; 1223 groups = "NRTS3"; 1224 }; 1225 1226 pinctrl_nrts4_default: nrts4_default { 1227 function = "NRTS4"; 1228 groups = "NRTS4"; 1229 }; 1230 1231 pinctrl_oscclk_default: oscclk_default { 1232 function = "OSCCLK"; 1233 groups = "OSCCLK"; 1234 }; 1235 1236 pinctrl_pewake_default: pewake_default { 1237 function = "PEWAKE"; 1238 groups = "PEWAKE"; 1239 }; 1240 1241 pinctrl_pnor_default: pnor_default { 1242 function = "PNOR"; 1243 groups = "PNOR"; 1244 }; 1245 1246 pinctrl_pwm0_default: pwm0_default { 1247 function = "PWM0"; 1248 groups = "PWM0"; 1249 }; 1250 1251 pinctrl_pwm1_default: pwm1_default { 1252 function = "PWM1"; 1253 groups = "PWM1"; 1254 }; 1255 1256 pinctrl_pwm2_default: pwm2_default { 1257 function = "PWM2"; 1258 groups = "PWM2"; 1259 }; 1260 1261 pinctrl_pwm3_default: pwm3_default { 1262 function = "PWM3"; 1263 groups = "PWM3"; 1264 }; 1265 1266 pinctrl_pwm4_default: pwm4_default { 1267 function = "PWM4"; 1268 groups = "PWM4"; 1269 }; 1270 1271 pinctrl_pwm5_default: pwm5_default { 1272 function = "PWM5"; 1273 groups = "PWM5"; 1274 }; 1275 1276 pinctrl_pwm6_default: pwm6_default { 1277 function = "PWM6"; 1278 groups = "PWM6"; 1279 }; 1280 1281 pinctrl_pwm7_default: pwm7_default { 1282 function = "PWM7"; 1283 groups = "PWM7"; 1284 }; 1285 1286 pinctrl_rgmii1_default: rgmii1_default { 1287 function = "RGMII1"; 1288 groups = "RGMII1"; 1289 }; 1290 1291 pinctrl_rgmii2_default: rgmii2_default { 1292 function = "RGMII2"; 1293 groups = "RGMII2"; 1294 }; 1295 1296 pinctrl_rmii1_default: rmii1_default { 1297 function = "RMII1"; 1298 groups = "RMII1"; 1299 }; 1300 1301 pinctrl_rmii2_default: rmii2_default { 1302 function = "RMII2"; 1303 groups = "RMII2"; 1304 }; 1305 1306 pinctrl_rxd1_default: rxd1_default { 1307 function = "RXD1"; 1308 groups = "RXD1"; 1309 }; 1310 1311 pinctrl_rxd2_default: rxd2_default { 1312 function = "RXD2"; 1313 groups = "RXD2"; 1314 }; 1315 1316 pinctrl_rxd3_default: rxd3_default { 1317 function = "RXD3"; 1318 groups = "RXD3"; 1319 }; 1320 1321 pinctrl_rxd4_default: rxd4_default { 1322 function = "RXD4"; 1323 groups = "RXD4"; 1324 }; 1325 1326 pinctrl_salt1_default: salt1_default { 1327 function = "SALT1"; 1328 groups = "SALT1"; 1329 }; 1330 1331 pinctrl_salt10_default: salt10_default { 1332 function = "SALT10"; 1333 groups = "SALT10"; 1334 }; 1335 1336 pinctrl_salt11_default: salt11_default { 1337 function = "SALT11"; 1338 groups = "SALT11"; 1339 }; 1340 1341 pinctrl_salt12_default: salt12_default { 1342 function = "SALT12"; 1343 groups = "SALT12"; 1344 }; 1345 1346 pinctrl_salt13_default: salt13_default { 1347 function = "SALT13"; 1348 groups = "SALT13"; 1349 }; 1350 1351 pinctrl_salt14_default: salt14_default { 1352 function = "SALT14"; 1353 groups = "SALT14"; 1354 }; 1355 1356 pinctrl_salt2_default: salt2_default { 1357 function = "SALT2"; 1358 groups = "SALT2"; 1359 }; 1360 1361 pinctrl_salt3_default: salt3_default { 1362 function = "SALT3"; 1363 groups = "SALT3"; 1364 }; 1365 1366 pinctrl_salt4_default: salt4_default { 1367 function = "SALT4"; 1368 groups = "SALT4"; 1369 }; 1370 1371 pinctrl_salt5_default: salt5_default { 1372 function = "SALT5"; 1373 groups = "SALT5"; 1374 }; 1375 1376 pinctrl_salt6_default: salt6_default { 1377 function = "SALT6"; 1378 groups = "SALT6"; 1379 }; 1380 1381 pinctrl_salt7_default: salt7_default { 1382 function = "SALT7"; 1383 groups = "SALT7"; 1384 }; 1385 1386 pinctrl_salt8_default: salt8_default { 1387 function = "SALT8"; 1388 groups = "SALT8"; 1389 }; 1390 1391 pinctrl_salt9_default: salt9_default { 1392 function = "SALT9"; 1393 groups = "SALT9"; 1394 }; 1395 1396 pinctrl_scl1_default: scl1_default { 1397 function = "SCL1"; 1398 groups = "SCL1"; 1399 }; 1400 1401 pinctrl_scl2_default: scl2_default { 1402 function = "SCL2"; 1403 groups = "SCL2"; 1404 }; 1405 1406 pinctrl_sd1_default: sd1_default { 1407 function = "SD1"; 1408 groups = "SD1"; 1409 }; 1410 1411 pinctrl_sd2_default: sd2_default { 1412 function = "SD2"; 1413 groups = "SD2"; 1414 }; 1415 1416 pinctrl_sda1_default: sda1_default { 1417 function = "SDA1"; 1418 groups = "SDA1"; 1419 }; 1420 1421 pinctrl_sda2_default: sda2_default { 1422 function = "SDA2"; 1423 groups = "SDA2"; 1424 }; 1425 1426 pinctrl_sgpm_default: sgpm_default { 1427 function = "SGPM"; 1428 groups = "SGPM"; 1429 }; 1430 1431 pinctrl_sgps1_default: sgps1_default { 1432 function = "SGPS1"; 1433 groups = "SGPS1"; 1434 }; 1435 1436 pinctrl_sgps2_default: sgps2_default { 1437 function = "SGPS2"; 1438 groups = "SGPS2"; 1439 }; 1440 1441 pinctrl_sioonctrl_default: sioonctrl_default { 1442 function = "SIOONCTRL"; 1443 groups = "SIOONCTRL"; 1444 }; 1445 1446 pinctrl_siopbi_default: siopbi_default { 1447 function = "SIOPBI"; 1448 groups = "SIOPBI"; 1449 }; 1450 1451 pinctrl_siopbo_default: siopbo_default { 1452 function = "SIOPBO"; 1453 groups = "SIOPBO"; 1454 }; 1455 1456 pinctrl_siopwreq_default: siopwreq_default { 1457 function = "SIOPWREQ"; 1458 groups = "SIOPWREQ"; 1459 }; 1460 1461 pinctrl_siopwrgd_default: siopwrgd_default { 1462 function = "SIOPWRGD"; 1463 groups = "SIOPWRGD"; 1464 }; 1465 1466 pinctrl_sios3_default: sios3_default { 1467 function = "SIOS3"; 1468 groups = "SIOS3"; 1469 }; 1470 1471 pinctrl_sios5_default: sios5_default { 1472 function = "SIOS5"; 1473 groups = "SIOS5"; 1474 }; 1475 1476 pinctrl_siosci_default: siosci_default { 1477 function = "SIOSCI"; 1478 groups = "SIOSCI"; 1479 }; 1480 1481 pinctrl_spi1_default: spi1_default { 1482 function = "SPI1"; 1483 groups = "SPI1"; 1484 }; 1485 1486 pinctrl_spi1cs1_default: spi1cs1_default { 1487 function = "SPI1CS1"; 1488 groups = "SPI1CS1"; 1489 }; 1490 1491 pinctrl_spi1debug_default: spi1debug_default { 1492 function = "SPI1DEBUG"; 1493 groups = "SPI1DEBUG"; 1494 }; 1495 1496 pinctrl_spi1passthru_default: spi1passthru_default { 1497 function = "SPI1PASSTHRU"; 1498 groups = "SPI1PASSTHRU"; 1499 }; 1500 1501 pinctrl_spi2ck_default: spi2ck_default { 1502 function = "SPI2CK"; 1503 groups = "SPI2CK"; 1504 }; 1505 1506 pinctrl_spi2cs0_default: spi2cs0_default { 1507 function = "SPI2CS0"; 1508 groups = "SPI2CS0"; 1509 }; 1510 1511 pinctrl_spi2cs1_default: spi2cs1_default { 1512 function = "SPI2CS1"; 1513 groups = "SPI2CS1"; 1514 }; 1515 1516 pinctrl_spi2miso_default: spi2miso_default { 1517 function = "SPI2MISO"; 1518 groups = "SPI2MISO"; 1519 }; 1520 1521 pinctrl_spi2mosi_default: spi2mosi_default { 1522 function = "SPI2MOSI"; 1523 groups = "SPI2MOSI"; 1524 }; 1525 1526 pinctrl_timer3_default: timer3_default { 1527 function = "TIMER3"; 1528 groups = "TIMER3"; 1529 }; 1530 1531 pinctrl_timer4_default: timer4_default { 1532 function = "TIMER4"; 1533 groups = "TIMER4"; 1534 }; 1535 1536 pinctrl_timer5_default: timer5_default { 1537 function = "TIMER5"; 1538 groups = "TIMER5"; 1539 }; 1540 1541 pinctrl_timer6_default: timer6_default { 1542 function = "TIMER6"; 1543 groups = "TIMER6"; 1544 }; 1545 1546 pinctrl_timer7_default: timer7_default { 1547 function = "TIMER7"; 1548 groups = "TIMER7"; 1549 }; 1550 1551 pinctrl_timer8_default: timer8_default { 1552 function = "TIMER8"; 1553 groups = "TIMER8"; 1554 }; 1555 1556 pinctrl_txd1_default: txd1_default { 1557 function = "TXD1"; 1558 groups = "TXD1"; 1559 }; 1560 1561 pinctrl_txd2_default: txd2_default { 1562 function = "TXD2"; 1563 groups = "TXD2"; 1564 }; 1565 1566 pinctrl_txd3_default: txd3_default { 1567 function = "TXD3"; 1568 groups = "TXD3"; 1569 }; 1570 1571 pinctrl_txd4_default: txd4_default { 1572 function = "TXD4"; 1573 groups = "TXD4"; 1574 }; 1575 1576 pinctrl_uart6_default: uart6_default { 1577 function = "UART6"; 1578 groups = "UART6"; 1579 }; 1580 1581 pinctrl_usbcki_default: usbcki_default { 1582 function = "USBCKI"; 1583 groups = "USBCKI"; 1584 }; 1585 1586 pinctrl_usb2ah_default: usb2ah_default { 1587 function = "USB2AH"; 1588 groups = "USB2AH"; 1589 }; 1590 1591 pinctrl_usb2ad_default: usb2ad_default { 1592 function = "USB2AD"; 1593 groups = "USB2AD"; 1594 }; 1595 1596 pinctrl_usb11bhid_default: usb11bhid_default { 1597 function = "USB11BHID"; 1598 groups = "USB11BHID"; 1599 }; 1600 1601 pinctrl_usb2bh_default: usb2bh_default { 1602 function = "USB2BH"; 1603 groups = "USB2BH"; 1604 }; 1605 1606 pinctrl_vgabiosrom_default: vgabiosrom_default { 1607 function = "VGABIOSROM"; 1608 groups = "VGABIOSROM"; 1609 }; 1610 1611 pinctrl_vgahs_default: vgahs_default { 1612 function = "VGAHS"; 1613 groups = "VGAHS"; 1614 }; 1615 1616 pinctrl_vgavs_default: vgavs_default { 1617 function = "VGAVS"; 1618 groups = "VGAVS"; 1619 }; 1620 1621 pinctrl_vpi24_default: vpi24_default { 1622 function = "VPI24"; 1623 groups = "VPI24"; 1624 }; 1625 1626 pinctrl_vpo_default: vpo_default { 1627 function = "VPO"; 1628 groups = "VPO"; 1629 }; 1630 1631 pinctrl_wdtrst1_default: wdtrst1_default { 1632 function = "WDTRST1"; 1633 groups = "WDTRST1"; 1634 }; 1635 1636 pinctrl_wdtrst2_default: wdtrst2_default { 1637 function = "WDTRST2"; 1638 groups = "WDTRST2"; 1639 }; 1640}; 1641