xref: /linux/scripts/dtc/include-prefixes/arm/aspeed/aspeed-bmc-vegman-rx20.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+
2*724ba675SRob Herring// Copyright (C) 2021 YADRO
3*724ba675SRob Herring/dts-v1/;
4*724ba675SRob Herring
5*724ba675SRob Herring#include "aspeed-bmc-vegman.dtsi"
6*724ba675SRob Herring
7*724ba675SRob Herring/ {
8*724ba675SRob Herring	model = "YADRO VEGMAN Rx20 BMC";
9*724ba675SRob Herring	compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500";
10*724ba675SRob Herring
11*724ba675SRob Herring	leds {
12*724ba675SRob Herring		compatible = "gpio-leds";
13*724ba675SRob Herring
14*724ba675SRob Herring		temp_alarm {
15*724ba675SRob Herring			label = "temp:red:status";
16*724ba675SRob Herring			default-state = "off";
17*724ba675SRob Herring			gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>;
18*724ba675SRob Herring		};
19*724ba675SRob Herring
20*724ba675SRob Herring		temp_ok {
21*724ba675SRob Herring			label = "temp:green:status";
22*724ba675SRob Herring			default-state = "off";
23*724ba675SRob Herring			gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
24*724ba675SRob Herring		};
25*724ba675SRob Herring
26*724ba675SRob Herring		psu_fault {
27*724ba675SRob Herring			label = "psu:red:status";
28*724ba675SRob Herring			default-state = "off";
29*724ba675SRob Herring			gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>;
30*724ba675SRob Herring		};
31*724ba675SRob Herring
32*724ba675SRob Herring		psu_ok {
33*724ba675SRob Herring			label = "psu:green:status";
34*724ba675SRob Herring			default-state = "off";
35*724ba675SRob Herring			gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
36*724ba675SRob Herring		};
37*724ba675SRob Herring	};
38*724ba675SRob Herring};
39*724ba675SRob Herring
40*724ba675SRob Herring&gpio {
41*724ba675SRob Herring	status = "okay";
42*724ba675SRob Herring	gpio-line-names =
43*724ba675SRob Herring	/*A0-A7*/	"CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
44*724ba675SRob Herring	/*B0-B7*/	"","","","","","","","",
45*724ba675SRob Herring	/*C0-C7*/	"","","","","","","","",
46*724ba675SRob Herring	/*D0-D7*/	"","","","","","","","",
47*724ba675SRob Herring	/*E0-E7*/	"RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G",
48*724ba675SRob Herring	/*F0-F7*/	"NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","",
49*724ba675SRob Herring	/*G0-G7*/	"CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","",
50*724ba675SRob Herring	/*H0-H7*/	"PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
51*724ba675SRob Herring	/*I0-I7*/	"","","","","","","","",
52*724ba675SRob Herring	/*J0-J7*/	"","","","","","","","",
53*724ba675SRob Herring	/*K0-K7*/	"","","","","","","","",
54*724ba675SRob Herring	/*L0-L7*/	"","","","","","","","",
55*724ba675SRob Herring	/*M0-M7*/	"SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","",
56*724ba675SRob Herring	/*N0-N7*/	"","","","","","","","",
57*724ba675SRob Herring	/*O0-O7*/	"","","","","","","","",
58*724ba675SRob Herring	/*P0-P7*/	"","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS",
59*724ba675SRob Herring	/*Q0-Q7*/	"","","","","","","","",
60*724ba675SRob Herring	/*R0-R7*/	"_SPI_BMC_BOOT_CS1","","","","","","","",
61*724ba675SRob Herring	/*S0-S7*/	"_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
62*724ba675SRob Herring	/*T0-T7*/	"","","","","","","","",
63*724ba675SRob Herring	/*U0-U7*/	"","","","","","","","",
64*724ba675SRob Herring	/*V0-V7*/	"","","","","","","","",
65*724ba675SRob Herring	/*W0-W7*/	"","","","","","","","",
66*724ba675SRob Herring	/*X0-X7*/	"","","","","","","","",
67*724ba675SRob Herring	/*Y0-Y7*/	"SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
68*724ba675SRob Herring	/*Z0-Z7*/	"FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
69*724ba675SRob Herring	/*AA0-AA7*/	"CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
70*724ba675SRob Herring	/*AB0-AB7*/	"FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","",
71*724ba675SRob Herring	/*AC0-AC7*/	"","","","","","","","";
72*724ba675SRob Herring};
73*724ba675SRob Herring
74*724ba675SRob Herring&sgpio {
75*724ba675SRob Herring	ngpios = <80>;
76*724ba675SRob Herring	bus-frequency = <2000000>;
77*724ba675SRob Herring	status = "okay";
78*724ba675SRob Herring	/* SGPIO lines. even: input, odd: output */
79*724ba675SRob Herring	gpio-line-names =
80*724ba675SRob Herring	/*A0-A7*/	"CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
81*724ba675SRob Herring	/*B0-B7*/	"CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
82*724ba675SRob Herring	/*C0-C7*/	"","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
83*724ba675SRob Herring	/*D0-D7*/	"","","","","","","","","","","","","","","","",
84*724ba675SRob Herring	/*E0-E7*/	"","","","","","","","","","","","","","","","",
85*724ba675SRob Herring	/*F0-F7*/	"SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
86*724ba675SRob Herring	/*G0-G7*/	"MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
87*724ba675SRob Herring	/*H0-H7*/	"","","","","","","","","","","","","","","","",
88*724ba675SRob Herring	/*I0-I7*/	"","","","","","","","","","","","","","","","",
89*724ba675SRob Herring	/*J0-J7*/	"","","","","","","","","","","","","","","","";
90*724ba675SRob Herring};
91*724ba675SRob Herring
92*724ba675SRob Herring&i2c11 {
93*724ba675SRob Herring	/* SMB_BMC_MGMT_LVC3 */
94*724ba675SRob Herring	gpio@21 {
95*724ba675SRob Herring		compatible = "nxp,pcal9535";
96*724ba675SRob Herring		reg = <0x21>;
97*724ba675SRob Herring		gpio-controller;
98*724ba675SRob Herring		#gpio-cells = <2>;
99*724ba675SRob Herring		gpio-line-names =
100*724ba675SRob Herring		/*IO0.0-0.7*/	"ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N",
101*724ba675SRob Herring		/*IO1.0-1.7*/	"RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", "";
102*724ba675SRob Herring	};
103*724ba675SRob Herring	gpio@23 {
104*724ba675SRob Herring		compatible = "nxp,pcal9535";
105*724ba675SRob Herring		reg = <0x23>;
106*724ba675SRob Herring		gpio-controller;
107*724ba675SRob Herring		#gpio-cells = <2>;
108*724ba675SRob Herring		gpio-line-names =
109*724ba675SRob Herring		/*IO0.0-0.7*/	"FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "",
110*724ba675SRob Herring		/*IO1.0-1.7*/	"", "", "", "", "", "", "", "";
111*724ba675SRob Herring	};
112*724ba675SRob Herring	gpio@27 {
113*724ba675SRob Herring		compatible = "nxp,pca9698";
114*724ba675SRob Herring		reg = <0x27>;
115*724ba675SRob Herring		gpio-controller;
116*724ba675SRob Herring		#gpio-cells = <2>;
117*724ba675SRob Herring		gpio-line-names =
118*724ba675SRob Herring		/*IO0.0-0.7*/	"PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
119*724ba675SRob Herring		/*IO1.0-1.7*/	"PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
120*724ba675SRob Herring		/*IO2.0-2.7*/	"PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
121*724ba675SRob Herring		/*IO3.0-3.7*/	"PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
122*724ba675SRob Herring		/*IO4.0-4.7*/	"PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1";
123*724ba675SRob Herring	};
124*724ba675SRob Herring	gpio@39 {
125*724ba675SRob Herring		compatible = "nxp,pca9554";
126*724ba675SRob Herring		reg = <0x39>;
127*724ba675SRob Herring		gpio-controller;
128*724ba675SRob Herring		#gpio-cells = <2>;
129*724ba675SRob Herring		gpio-line-names =
130*724ba675SRob Herring		/*IO0.0-0.7*/	"FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", "";
131*724ba675SRob Herring	};
132*724ba675SRob Herring};
133*724ba675SRob Herring
134*724ba675SRob Herring&i2c13 {
135*724ba675SRob Herring	/* SMB_PCIE2_STBY_LVC3 */
136*724ba675SRob Herring	mux-expa@70 {
137*724ba675SRob Herring		compatible = "nxp,pca9548";
138*724ba675SRob Herring		reg = <0x70>;
139*724ba675SRob Herring		#address-cells = <1>;
140*724ba675SRob Herring		#size-cells = <0>;
141*724ba675SRob Herring		i2c-mux-idle-disconnect;
142*724ba675SRob Herring
143*724ba675SRob Herring		i2c@2 {
144*724ba675SRob Herring			#address-cells = <1>;
145*724ba675SRob Herring			#size-cells = <0>;
146*724ba675SRob Herring			reg = <2>;
147*724ba675SRob Herring			rsra-mux@72 {
148*724ba675SRob Herring				compatible = "nxp,pca9548";
149*724ba675SRob Herring				reg = <0x72>;
150*724ba675SRob Herring				#address-cells = <1>;
151*724ba675SRob Herring				#size-cells = <0>;
152*724ba675SRob Herring
153*724ba675SRob Herring				i2c@7 {
154*724ba675SRob Herring					#address-cells = <1>;
155*724ba675SRob Herring					#size-cells = <0>;
156*724ba675SRob Herring					reg = <7>;
157*724ba675SRob Herring					at24@50 {
158*724ba675SRob Herring						compatible = "atmel,24c64";
159*724ba675SRob Herring						reg = <0x50>;
160*724ba675SRob Herring						pagesize = <32>;
161*724ba675SRob Herring						size = <8192>;
162*724ba675SRob Herring						address-width = <16>;
163*724ba675SRob Herring					};
164*724ba675SRob Herring				};
165*724ba675SRob Herring			};
166*724ba675SRob Herring		};
167*724ba675SRob Herring	};
168*724ba675SRob Herring	mux-sata@71 {
169*724ba675SRob Herring		compatible = "nxp,pca9543";
170*724ba675SRob Herring		reg = <0x71>;
171*724ba675SRob Herring		#address-cells = <1>;
172*724ba675SRob Herring		#size-cells = <0>;
173*724ba675SRob Herring		i2c-mux-idle-disconnect;
174*724ba675SRob Herring	};
175*724ba675SRob Herring};
176*724ba675SRob Herring
177*724ba675SRob Herring&i2c2 {
178*724ba675SRob Herring	/* SMB_PCIE_STBY_LVC3 */
179*724ba675SRob Herring	mux-expb@71 {
180*724ba675SRob Herring		compatible = "nxp,pca9548";
181*724ba675SRob Herring		reg = <0x71>;
182*724ba675SRob Herring		#address-cells = <1>;
183*724ba675SRob Herring		#size-cells = <0>;
184*724ba675SRob Herring		i2c-mux-idle-disconnect;
185*724ba675SRob Herring
186*724ba675SRob Herring		i2c@0 {
187*724ba675SRob Herring			#address-cells = <1>;
188*724ba675SRob Herring			#size-cells = <0>;
189*724ba675SRob Herring			reg = <0>;
190*724ba675SRob Herring			rsrb-mux@72 {
191*724ba675SRob Herring				compatible = "nxp,pca9548";
192*724ba675SRob Herring				reg = <0x72>;
193*724ba675SRob Herring				#address-cells = <1>;
194*724ba675SRob Herring				#size-cells = <0>;
195*724ba675SRob Herring				i2c@7 {
196*724ba675SRob Herring					#address-cells = <1>;
197*724ba675SRob Herring					#size-cells = <0>;
198*724ba675SRob Herring					reg = <7>;
199*724ba675SRob Herring					at24@50 {
200*724ba675SRob Herring						compatible = "atmel,24c64";
201*724ba675SRob Herring						reg = <0x50>;
202*724ba675SRob Herring						pagesize = <32>;
203*724ba675SRob Herring						size = <8192>;
204*724ba675SRob Herring						address-width = <16>;
205*724ba675SRob Herring					};
206*724ba675SRob Herring				};
207*724ba675SRob Herring			};
208*724ba675SRob Herring			at24@50 {
209*724ba675SRob Herring				compatible = "atmel,24c64";
210*724ba675SRob Herring				reg = <0x50>;
211*724ba675SRob Herring				pagesize = <32>;
212*724ba675SRob Herring				size = <8192>;
213*724ba675SRob Herring				address-width = <16>;
214*724ba675SRob Herring			};
215*724ba675SRob Herring		};
216*724ba675SRob Herring	};
217*724ba675SRob Herring};
218*724ba675SRob Herring
219*724ba675SRob Herring&pwm_tacho {
220*724ba675SRob Herring	status = "okay";
221*724ba675SRob Herring	pinctrl-names = "default";
222*724ba675SRob Herring	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
223*724ba675SRob Herring			 &pinctrl_pwm2_default &pinctrl_pwm3_default
224*724ba675SRob Herring			 &pinctrl_pwm4_default &pinctrl_pwm5_default
225*724ba675SRob Herring			 &pinctrl_pwm6_default>;
226*724ba675SRob Herring
227*724ba675SRob Herring	fan@0 {
228*724ba675SRob Herring		reg = <0x00>;
229*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>;
230*724ba675SRob Herring	};
231*724ba675SRob Herring	fan@1 {
232*724ba675SRob Herring		reg = <0x01>;
233*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>;
234*724ba675SRob Herring	};
235*724ba675SRob Herring	fan@2 {
236*724ba675SRob Herring		reg = <0x02>;
237*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>;
238*724ba675SRob Herring	};
239*724ba675SRob Herring	fan@3 {
240*724ba675SRob Herring		reg = <0x03>;
241*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>;
242*724ba675SRob Herring	};
243*724ba675SRob Herring	fan@4 {
244*724ba675SRob Herring		reg = <0x04>;
245*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>;
246*724ba675SRob Herring	};
247*724ba675SRob Herring	fan@5 {
248*724ba675SRob Herring		reg = <0x05>;
249*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>;
250*724ba675SRob Herring	};
251*724ba675SRob Herring	fan@6 {
252*724ba675SRob Herring		reg = <0x06>;
253*724ba675SRob Herring		aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>;
254*724ba675SRob Herring	};
255*724ba675SRob Herring};
256