1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring// Copyright (c) 2017 Facebook Inc. 3*724ba675SRob Herring/dts-v1/; 4*724ba675SRob Herring 5*724ba675SRob Herring#include "aspeed-g5.dtsi" 6*724ba675SRob Herring#include <dt-bindings/gpio/aspeed-gpio.h> 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Portwell Neptune BMC"; 10*724ba675SRob Herring compatible = "portwell,neptune-bmc", "aspeed,ast2500"; 11*724ba675SRob Herring aliases { 12*724ba675SRob Herring serial0 = &uart1; 13*724ba675SRob Herring serial4 = &uart5; 14*724ba675SRob Herring }; 15*724ba675SRob Herring chosen { 16*724ba675SRob Herring stdout-path = &uart5; 17*724ba675SRob Herring bootargs = "console=ttyS4,115200 earlycon"; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring memory@80000000 { 21*724ba675SRob Herring reg = <0x80000000 0x20000000>; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring leds { 25*724ba675SRob Herring compatible = "gpio-leds"; 26*724ba675SRob Herring postcode0 { 27*724ba675SRob Herring label = "BMC_UP"; 28*724ba675SRob Herring gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 29*724ba675SRob Herring default-state = "on"; 30*724ba675SRob Herring }; 31*724ba675SRob Herring postcode1 { 32*724ba675SRob Herring label = "BMC_HB"; 33*724ba675SRob Herring gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 34*724ba675SRob Herring linux,default-trigger = "heartbeat"; 35*724ba675SRob Herring }; 36*724ba675SRob Herring postcode2 { 37*724ba675SRob Herring label = "FAULT"; 38*724ba675SRob Herring gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring // postcode3-7 are GPIOH3-H7 41*724ba675SRob Herring }; 42*724ba675SRob Herring}; 43*724ba675SRob Herring 44*724ba675SRob Herring&fmc { 45*724ba675SRob Herring status = "okay"; 46*724ba675SRob Herring flash@0 { 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring m25p,fast-read; 49*724ba675SRob Herring#include "openbmc-flash-layout.dtsi" 50*724ba675SRob Herring }; 51*724ba675SRob Herring}; 52*724ba675SRob Herring 53*724ba675SRob Herring&spi1 { 54*724ba675SRob Herring status = "okay"; 55*724ba675SRob Herring pinctrl-names = "default"; 56*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi1_default>; 57*724ba675SRob Herring flash@0 { 58*724ba675SRob Herring status = "okay"; 59*724ba675SRob Herring m25p,fast-read; 60*724ba675SRob Herring label = "pnor"; 61*724ba675SRob Herring }; 62*724ba675SRob Herring}; 63*724ba675SRob Herring 64*724ba675SRob Herring&uart1 { 65*724ba675SRob Herring // Host Console 66*724ba675SRob Herring status = "okay"; 67*724ba675SRob Herring pinctrl-names = "default"; 68*724ba675SRob Herring pinctrl-0 = <&pinctrl_txd1_default 69*724ba675SRob Herring &pinctrl_rxd1_default>; 70*724ba675SRob Herring}; 71*724ba675SRob Herring 72*724ba675SRob Herring&uart5 { 73*724ba675SRob Herring // BMC Console 74*724ba675SRob Herring status = "okay"; 75*724ba675SRob Herring}; 76*724ba675SRob Herring 77*724ba675SRob Herring&mac0 { 78*724ba675SRob Herring status = "okay"; 79*724ba675SRob Herring 80*724ba675SRob Herring pinctrl-names = "default"; 81*724ba675SRob Herring pinctrl-0 = <&pinctrl_rmii1_default 82*724ba675SRob Herring &pinctrl_mdio1_default>; 83*724ba675SRob Herring clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, 84*724ba675SRob Herring <&syscon ASPEED_CLK_MAC1RCLK>; 85*724ba675SRob Herring clock-names = "MACCLK", "RCLK"; 86*724ba675SRob Herring}; 87*724ba675SRob Herring 88*724ba675SRob Herring&mac1 { 89*724ba675SRob Herring status = "okay"; 90*724ba675SRob Herring pinctrl-names = "default"; 91*724ba675SRob Herring pinctrl-0 = <&pinctrl_rmii2_default>; 92*724ba675SRob Herring clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, 93*724ba675SRob Herring <&syscon ASPEED_CLK_MAC2RCLK>; 94*724ba675SRob Herring clock-names = "MACCLK", "RCLK"; 95*724ba675SRob Herring use-ncsi; 96*724ba675SRob Herring}; 97*724ba675SRob Herring 98*724ba675SRob Herring&i2c1 { 99*724ba675SRob Herring status = "okay"; 100*724ba675SRob Herring // To PCIe slot SMBUS 101*724ba675SRob Herring}; 102*724ba675SRob Herring 103*724ba675SRob Herring&i2c2 { 104*724ba675SRob Herring status = "okay"; 105*724ba675SRob Herring // To LAN I210 106*724ba675SRob Herring}; 107*724ba675SRob Herring 108*724ba675SRob Herring&i2c3 { 109*724ba675SRob Herring status = "okay"; 110*724ba675SRob Herring // SMBus to COMe AB 111*724ba675SRob Herring}; 112*724ba675SRob Herring 113*724ba675SRob Herring&i2c4 { 114*724ba675SRob Herring status = "okay"; 115*724ba675SRob Herring // I2C to COMe AB 116*724ba675SRob Herring}; 117*724ba675SRob Herring 118*724ba675SRob Herring&i2c5 { 119*724ba675SRob Herring status = "okay"; 120*724ba675SRob Herring// USB Debug card 121*724ba675SRob Herring pca9555@27 { 122*724ba675SRob Herring compatible = "nxp,pca9555"; 123*724ba675SRob Herring reg = <0x27>; 124*724ba675SRob Herring gpio-controller; 125*724ba675SRob Herring #gpio-cells = <2>; 126*724ba675SRob Herring }; 127*724ba675SRob Herring}; 128*724ba675SRob Herring 129*724ba675SRob Herring&i2c6 { 130*724ba675SRob Herring status = "okay"; 131*724ba675SRob Herring tpm@20 { 132*724ba675SRob Herring compatible = "infineon,slb9645tt"; 133*724ba675SRob Herring reg = <0x20>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring tmp421@4e { 136*724ba675SRob Herring compatible = "ti,tmp421"; 137*724ba675SRob Herring reg = <0x4e>; 138*724ba675SRob Herring }; 139*724ba675SRob Herring tmp421@4f { 140*724ba675SRob Herring compatible = "ti,tmp421"; 141*724ba675SRob Herring reg = <0x4f>; 142*724ba675SRob Herring }; 143*724ba675SRob Herring}; 144*724ba675SRob Herring 145*724ba675SRob Herring&i2c8 { 146*724ba675SRob Herring status = "okay"; 147*724ba675SRob Herring eeprom@51 { 148*724ba675SRob Herring compatible = "atmel,24c128"; 149*724ba675SRob Herring reg = <0x51>; 150*724ba675SRob Herring pagesize = <32>; 151*724ba675SRob Herring }; 152*724ba675SRob Herring}; 153*724ba675SRob Herring 154*724ba675SRob Herring&pwm_tacho { 155*724ba675SRob Herring status = "okay"; 156*724ba675SRob Herring pinctrl-names = "default"; 157*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; 158*724ba675SRob Herring fan@0 { 159*724ba675SRob Herring reg = <0x00>; 160*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x00>; 161*724ba675SRob Herring }; 162*724ba675SRob Herring 163*724ba675SRob Herring fan@1 { 164*724ba675SRob Herring reg = <0x00>; 165*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x01>; 166*724ba675SRob Herring }; 167*724ba675SRob Herring}; 168