1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 22924cd18SRuud Derwig/* 32924cd18SRuud Derwig * Support for peripherals on the AXS10x mainboard (VDK version) 42924cd18SRuud Derwig * 52924cd18SRuud Derwig * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 62924cd18SRuud Derwig */ 72924cd18SRuud Derwig 82924cd18SRuud Derwig/ { 92924cd18SRuud Derwig axs10x_mb_vdk { 102924cd18SRuud Derwig compatible = "simple-bus"; 112924cd18SRuud Derwig #address-cells = <1>; 122924cd18SRuud Derwig #size-cells = <1>; 132924cd18SRuud Derwig ranges = <0x00000000 0xe0000000 0x10000000>; 142924cd18SRuud Derwig interrupt-parent = <&mb_intc>; 152924cd18SRuud Derwig 162924cd18SRuud Derwig clocks { 172924cd18SRuud Derwig apbclk: apbclk { 182924cd18SRuud Derwig compatible = "fixed-clock"; 192924cd18SRuud Derwig clock-frequency = <50000000>; 202924cd18SRuud Derwig #clock-cells = <0>; 212924cd18SRuud Derwig }; 222924cd18SRuud Derwig 23d9174e72SAlexey Brodkin mmcclk: mmcclk { 24d9174e72SAlexey Brodkin compatible = "fixed-clock"; 25d9174e72SAlexey Brodkin clock-frequency = <50000000>; 26d9174e72SAlexey Brodkin #clock-cells = <0>; 27d9174e72SAlexey Brodkin }; 28d9174e72SAlexey Brodkin 29c8f1daa8SAlexey Brodkin pguclk: pguclk { 30c8f1daa8SAlexey Brodkin #clock-cells = <0>; 31c8f1daa8SAlexey Brodkin compatible = "fixed-clock"; 32c8f1daa8SAlexey Brodkin clock-frequency = <25175000>; 33c8f1daa8SAlexey Brodkin }; 342924cd18SRuud Derwig }; 352924cd18SRuud Derwig 36ef4c54c3SAlexey Brodkin ethernet@18000 { 372924cd18SRuud Derwig #interrupt-cells = <1>; 382924cd18SRuud Derwig compatible = "snps,dwmac"; 392924cd18SRuud Derwig reg = < 0x18000 0x2000 >; 402924cd18SRuud Derwig interrupts = < 4 >; 412924cd18SRuud Derwig interrupt-names = "macirq"; 422924cd18SRuud Derwig phy-mode = "rgmii"; 432924cd18SRuud Derwig snps,phy-addr = < 0 >; // VDK model phy address is 0 442924cd18SRuud Derwig snps,pbl = < 32 >; 452924cd18SRuud Derwig clocks = <&apbclk>; 462924cd18SRuud Derwig clock-names = "stmmaceth"; 472924cd18SRuud Derwig }; 482924cd18SRuud Derwig 49c8f87858SSerge Semin usb@40000 { 502924cd18SRuud Derwig compatible = "generic-ehci"; 512924cd18SRuud Derwig reg = < 0x40000 0x100 >; 522924cd18SRuud Derwig interrupts = < 8 >; 532924cd18SRuud Derwig }; 542924cd18SRuud Derwig 55ef4c54c3SAlexey Brodkin uart@20000 { 562924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 572924cd18SRuud Derwig reg = <0x20000 0x100>; 582924cd18SRuud Derwig clock-frequency = <2403200>; 592924cd18SRuud Derwig interrupts = <17>; 602924cd18SRuud Derwig baud = <115200>; 612924cd18SRuud Derwig reg-shift = <2>; 622924cd18SRuud Derwig reg-io-width = <4>; 632924cd18SRuud Derwig }; 642924cd18SRuud Derwig 65ef4c54c3SAlexey Brodkin uart@21000 { 662924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 672924cd18SRuud Derwig reg = <0x21000 0x100>; 682924cd18SRuud Derwig clock-frequency = <2403200>; 692924cd18SRuud Derwig interrupts = <18>; 702924cd18SRuud Derwig baud = <115200>; 712924cd18SRuud Derwig reg-shift = <2>; 722924cd18SRuud Derwig reg-io-width = <4>; 732924cd18SRuud Derwig }; 742924cd18SRuud Derwig 75ef4c54c3SAlexey Brodkin uart@22000 { 762924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 772924cd18SRuud Derwig reg = <0x22000 0x100>; 782924cd18SRuud Derwig clock-frequency = <2403200>; 792924cd18SRuud Derwig interrupts = <19>; 802924cd18SRuud Derwig baud = <115200>; 812924cd18SRuud Derwig reg-shift = <2>; 822924cd18SRuud Derwig reg-io-width = <4>; 832924cd18SRuud Derwig }; 842924cd18SRuud Derwig 852924cd18SRuud Derwig/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */ 86c8f1daa8SAlexey Brodkin pgu@17000 { 87c8f1daa8SAlexey Brodkin compatible = "snps,arcpgu"; 882924cd18SRuud Derwig reg = <0x17000 0x400>; 89c8f1daa8SAlexey Brodkin clocks = <&pguclk>; 90c8f1daa8SAlexey Brodkin clock-names = "pxlclk"; 912924cd18SRuud Derwig }; 922924cd18SRuud Derwig 932924cd18SRuud Derwig/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */ 942924cd18SRuud Derwig ps2: ps2@e0017400 { 952924cd18SRuud Derwig compatible = "snps,arc_ps2"; 962924cd18SRuud Derwig reg = <0x17400 0x14>; 972924cd18SRuud Derwig interrupts = <5>; 982924cd18SRuud Derwig interrupt-names = "arc_ps2_irq"; 992924cd18SRuud Derwig }; 100d9174e72SAlexey Brodkin 101ef4c54c3SAlexey Brodkin mmc@15000 { 102d9174e72SAlexey Brodkin compatible = "snps,dw-mshc"; 103d9174e72SAlexey Brodkin reg = <0x15000 0x400>; 104d9174e72SAlexey Brodkin fifo-depth = <1024>; 105d9174e72SAlexey Brodkin card-detect-delay = <200>; 106d9174e72SAlexey Brodkin clocks = <&apbclk>, <&mmcclk>; 107d9174e72SAlexey Brodkin clock-names = "biu", "ciu"; 108d9174e72SAlexey Brodkin interrupts = <7>; 109d9174e72SAlexey Brodkin bus-width = <4>; 110d9174e72SAlexey Brodkin }; 111ae9955aeSAlexey Brodkin }; 112cf16bf77SAlexey Brodkin 113ae9955aeSAlexey Brodkin /* 114ae9955aeSAlexey Brodkin * Embedded Vision subsystem UIO mappings; only relevant for EV VDK 115ae9955aeSAlexey Brodkin * 116*ebfc2fd8SBjorn Helgaas * This node is intentionally put outside of MB above because 117ef4c54c3SAlexey Brodkin * it maps areas outside of MB's 0xez-0xfz. 118ae9955aeSAlexey Brodkin */ 119ef4c54c3SAlexey Brodkin uio_ev: uio@d0000000 { 120cf16bf77SAlexey Brodkin compatible = "generic-uio"; 121ef4c54c3SAlexey Brodkin reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>; 122cf16bf77SAlexey Brodkin reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem"; 123ae9955aeSAlexey Brodkin interrupt-parent = <&mb_intc>; 124cf16bf77SAlexey Brodkin interrupts = <23>; 125cf16bf77SAlexey Brodkin }; 1262924cd18SRuud Derwig}; 127