1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Support for peripherals on the AXS10x mainboard 4 * 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 6 */ 7 8/ { 9 aliases { 10 ethernet = &gmac; 11 }; 12 13 axs10x_mb { 14 compatible = "simple-bus"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>; 18 interrupt-parent = <&mb_intc>; 19 20 creg_rst: reset-controller@11220 { 21 compatible = "snps,axs10x-reset"; 22 #reset-cells = <1>; 23 reg = <0x11220 0x4>; 24 }; 25 26 i2sclk: i2sclk@100a0 { 27 compatible = "snps,axs10x-i2s-pll-clock"; 28 reg = <0x100a0 0x10>; 29 clocks = <&i2spll_clk>; 30 #clock-cells = <0>; 31 }; 32 33 clocks { 34 i2spll_clk: i2spll_clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <27000000>; 37 #clock-cells = <0>; 38 }; 39 40 i2cclk: i2cclk { 41 compatible = "fixed-clock"; 42 clock-frequency = <50000000>; 43 #clock-cells = <0>; 44 }; 45 46 apbclk: apbclk { 47 compatible = "fixed-clock"; 48 clock-frequency = <50000000>; 49 #clock-cells = <0>; 50 }; 51 52 mmcclk: mmcclk { 53 compatible = "fixed-clock"; 54 /* 55 * DW sdio controller has external ciu clock divider 56 * controlled via register in SDIO IP. It divides 57 * sdio_ref_clk (which comes from CGU) by 16 for 58 * default. So default mmcclk clock (which comes 59 * to sdk_in) is 25000000 Hz. 60 */ 61 clock-frequency = <25000000>; 62 #clock-cells = <0>; 63 }; 64 65 pguclk: pguclk { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <74250000>; 69 }; 70 }; 71 72 gmac: ethernet@18000 { 73 #interrupt-cells = <1>; 74 compatible = "snps,dwmac"; 75 reg = < 0x18000 0x2000 >; 76 interrupts = < 4 >; 77 interrupt-names = "macirq"; 78 phy-mode = "rgmii"; 79 snps,pbl = < 32 >; 80 clocks = <&apbclk>; 81 clock-names = "stmmaceth"; 82 max-speed = <100>; 83 resets = <&creg_rst 5>; 84 reset-names = "stmmaceth"; 85 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 86 }; 87 88 ehci@40000 { 89 compatible = "generic-ehci"; 90 reg = < 0x40000 0x100 >; 91 interrupts = < 8 >; 92 }; 93 94 ohci@60000 { 95 compatible = "generic-ohci"; 96 reg = < 0x60000 0x100 >; 97 interrupts = < 8 >; 98 }; 99 100 /* 101 * According to DW Mobile Storage databook it is required 102 * to use "Hold Register" if card is enumerated in SDR12 or 103 * SDR25 modes. 104 * 105 * Utilization of "Hold Register" is already implemented via 106 * dw_mci_pltfm_prepare_command() which in its turn gets 107 * used through dw_mci_drv_data->prepare_command call-back. 108 * This call-back is used in Altera Socfpga platform and so 109 * we may reuse it saying that we're compatible with their 110 * "altr,socfpga-dw-mshc". 111 * 112 * Most probably "Hold Register" utilization is platform- 113 * independent requirement which means that single unified 114 * "snps,dw-mshc" should be enough for all users of DW MMC once 115 * dw_mci_pltfm_prepare_command() is used in generic platform 116 * code. 117 */ 118 mmc@15000 { 119 compatible = "altr,socfpga-dw-mshc"; 120 reg = < 0x15000 0x400 >; 121 fifo-depth = < 16 >; 122 card-detect-delay = < 200 >; 123 clocks = <&apbclk>, <&mmcclk>; 124 clock-names = "biu", "ciu"; 125 interrupts = < 7 >; 126 bus-width = < 4 >; 127 }; 128 129 uart@20000 { 130 compatible = "snps,dw-apb-uart"; 131 reg = <0x20000 0x100>; 132 clock-frequency = <33333333>; 133 interrupts = <17>; 134 baud = <115200>; 135 reg-shift = <2>; 136 reg-io-width = <4>; 137 }; 138 139 uart@21000 { 140 compatible = "snps,dw-apb-uart"; 141 reg = <0x21000 0x100>; 142 clock-frequency = <33333333>; 143 interrupts = <18>; 144 baud = <115200>; 145 reg-shift = <2>; 146 reg-io-width = <4>; 147 }; 148 149 /* UART muxed with USB data port (ttyS3) */ 150 uart@22000 { 151 compatible = "snps,dw-apb-uart"; 152 reg = <0x22000 0x100>; 153 clock-frequency = <33333333>; 154 interrupts = <19>; 155 baud = <115200>; 156 reg-shift = <2>; 157 reg-io-width = <4>; 158 }; 159 160 i2c@1d000 { 161 compatible = "snps,designware-i2c"; 162 reg = <0x1d000 0x100>; 163 clock-frequency = <400000>; 164 clocks = <&i2cclk>; 165 interrupts = <14>; 166 }; 167 168 i2s: i2s@1e000 { 169 compatible = "snps,designware-i2s"; 170 reg = <0x1e000 0x100>; 171 clocks = <&i2sclk 0>; 172 clock-names = "i2sclk"; 173 interrupts = <15>; 174 #sound-dai-cells = <0>; 175 }; 176 177 i2c@1f000 { 178 compatible = "snps,designware-i2c"; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 reg = <0x1f000 0x100>; 182 clock-frequency = <400000>; 183 clocks = <&i2cclk>; 184 interrupts = <16>; 185 186 adv7511:adv7511@39{ 187 compatible="adi,adv7511"; 188 reg = <0x39>; 189 interrupts = <23>; 190 adi,input-depth = <8>; 191 adi,input-colorspace = "rgb"; 192 adi,input-clock = "1x"; 193 adi,clock-delay = <0x03>; 194 #sound-dai-cells = <0>; 195 196 ports { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 /* RGB/YUV input */ 201 port@0 { 202 reg = <0>; 203 adv7511_input:endpoint { 204 remote-endpoint = <&pgu_output>; 205 }; 206 }; 207 208 /* HDMI output */ 209 port@1 { 210 reg = <1>; 211 adv7511_output: endpoint { 212 remote-endpoint = <&hdmi_connector_in>; 213 }; 214 }; 215 }; 216 }; 217 218 eeprom@54{ 219 compatible = "atmel,24c01"; 220 reg = <0x54>; 221 pagesize = <0x8>; 222 }; 223 224 eeprom@57{ 225 compatible = "atmel,24c04"; 226 reg = <0x57>; 227 pagesize = <0x8>; 228 }; 229 }; 230 231 hdmi0: connector { 232 compatible = "hdmi-connector"; 233 type = "a"; 234 port { 235 hdmi_connector_in: endpoint { 236 remote-endpoint = <&adv7511_output>; 237 }; 238 }; 239 }; 240 241 gpio0:gpio@13000 { 242 compatible = "snps,dw-apb-gpio"; 243 reg = <0x13000 0x1000>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 gpio0_banka: gpio-controller@0 { 248 compatible = "snps,dw-apb-gpio-port"; 249 gpio-controller; 250 #gpio-cells = <2>; 251 snps,nr-gpios = <32>; 252 reg = <0>; 253 }; 254 255 gpio0_bankb: gpio-controller@1 { 256 compatible = "snps,dw-apb-gpio-port"; 257 gpio-controller; 258 #gpio-cells = <2>; 259 snps,nr-gpios = <8>; 260 reg = <1>; 261 }; 262 263 gpio0_bankc: gpio-controller@2 { 264 compatible = "snps,dw-apb-gpio-port"; 265 gpio-controller; 266 #gpio-cells = <2>; 267 snps,nr-gpios = <8>; 268 reg = <2>; 269 }; 270 }; 271 272 gpio1:gpio@14000 { 273 compatible = "snps,dw-apb-gpio"; 274 reg = <0x14000 0x1000>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 gpio1_banka: gpio-controller@0 { 279 compatible = "snps,dw-apb-gpio-port"; 280 gpio-controller; 281 #gpio-cells = <2>; 282 snps,nr-gpios = <30>; 283 reg = <0>; 284 }; 285 286 gpio1_bankb: gpio-controller@1 { 287 compatible = "snps,dw-apb-gpio-port"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 snps,nr-gpios = <10>; 291 reg = <1>; 292 }; 293 294 gpio1_bankc: gpio-controller@2 { 295 compatible = "snps,dw-apb-gpio-port"; 296 gpio-controller; 297 #gpio-cells = <2>; 298 snps,nr-gpios = <8>; 299 reg = <2>; 300 }; 301 }; 302 303 pgu@17000 { 304 compatible = "snps,arcpgu"; 305 reg = <0x17000 0x400>; 306 encoder-slave = <&adv7511>; 307 clocks = <&pguclk>; 308 clock-names = "pxlclk"; 309 memory-region = <&frame_buffer>; 310 port { 311 pgu_output: endpoint { 312 remote-endpoint = <&adv7511_input>; 313 }; 314 }; 315 }; 316 317 sound_playback { 318 compatible = "simple-audio-card"; 319 simple-audio-card,name = "AXS10x HDMI Audio"; 320 simple-audio-card,format = "i2s"; 321 simple-audio-card,cpu { 322 sound-dai = <&i2s>; 323 }; 324 simple-audio-card,codec { 325 sound-dai = <&adv7511>; 326 }; 327 }; 328 }; 329}; 330