1 // SPDX-License-Identifier: GPL-2.0 2 3 // Copyright (C) 2024 FUJITA Tomonori <fujita.tomonori@gmail.com> 4 5 //! PHY register interfaces. 6 //! 7 //! This module provides support for accessing PHY registers in the 8 //! Ethernet management interface clauses 22 and 45 register namespaces, as 9 //! defined in IEEE 802.3. 10 11 use super::Device; 12 use crate::{ 13 build_assert::build_assert, 14 error::*, 15 uapi, // 16 }; 17 18 mod private { 19 /// Marker that a trait cannot be implemented outside of this crate 20 pub trait Sealed {} 21 } 22 23 /// Accesses PHY registers. 24 /// 25 /// This trait is used to implement the unified interface to access 26 /// C22 and C45 PHY registers. 27 /// 28 /// # Examples 29 /// 30 /// ```ignore 31 /// fn link_change_notify(dev: &mut Device) { 32 /// // read C22 BMCR register 33 /// dev.read(C22::BMCR); 34 /// // read C45 PMA/PMD control 1 register 35 /// dev.read(C45::new(Mmd::PMAPMD, 0)); 36 /// 37 /// // Checks the link status as reported by registers in the C22 namespace 38 /// // and updates current link state. 39 /// dev.genphy_read_status::<phy::C22>(); 40 /// // Checks the link status as reported by registers in the C45 namespace 41 /// // and updates current link state. 42 /// dev.genphy_read_status::<phy::C45>(); 43 /// } 44 /// ``` 45 pub trait Register: private::Sealed { 46 /// Reads a PHY register. 47 fn read(&self, dev: &mut Device) -> Result<u16>; 48 49 /// Writes a PHY register. 50 fn write(&self, dev: &mut Device, val: u16) -> Result; 51 52 /// Checks the link status and updates current link state. 53 fn read_status(dev: &mut Device) -> Result<u16>; 54 } 55 56 /// A single MDIO clause 22 register address (5 bits). 57 #[derive(Copy, Clone, Debug)] 58 pub struct C22(u8); 59 60 impl C22 { 61 /// Basic mode control. 62 pub const BMCR: Self = C22(0x00); 63 /// Basic mode status. 64 pub const BMSR: Self = C22(0x01); 65 /// PHY identifier 1. 66 pub const PHYSID1: Self = C22(0x02); 67 /// PHY identifier 2. 68 pub const PHYSID2: Self = C22(0x03); 69 /// Auto-negotiation advertisement. 70 pub const ADVERTISE: Self = C22(0x04); 71 /// Auto-negotiation link partner base page ability. 72 pub const LPA: Self = C22(0x05); 73 /// Auto-negotiation expansion. 74 pub const EXPANSION: Self = C22(0x06); 75 /// Auto-negotiation next page transmit. 76 pub const NEXT_PAGE_TRANSMIT: Self = C22(0x07); 77 /// Auto-negotiation link partner received next page. 78 pub const LP_RECEIVED_NEXT_PAGE: Self = C22(0x08); 79 /// Master-slave control. 80 pub const MASTER_SLAVE_CONTROL: Self = C22(0x09); 81 /// Master-slave status. 82 pub const MASTER_SLAVE_STATUS: Self = C22(0x0a); 83 /// PSE Control. 84 pub const PSE_CONTROL: Self = C22(0x0b); 85 /// PSE Status. 86 pub const PSE_STATUS: Self = C22(0x0c); 87 /// MMD Register control. 88 pub const MMD_CONTROL: Self = C22(0x0d); 89 /// MMD Register address data. 90 pub const MMD_DATA: Self = C22(0x0e); 91 /// Extended status. 92 pub const EXTENDED_STATUS: Self = C22(0x0f); 93 94 /// Creates a new instance of `C22` with a vendor specific register. 95 pub const fn vendor_specific<const N: u8>() -> Self { 96 build_assert!( 97 N > 0x0f && N < 0x20, 98 "Vendor-specific register address must be between 16 and 31" 99 ); 100 C22(N) 101 } 102 } 103 104 impl private::Sealed for C22 {} 105 106 impl Register for C22 { 107 fn read(&self, dev: &mut Device) -> Result<u16> { 108 let phydev = dev.0.get(); 109 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`. 110 // So it's just an FFI call, open code of `phy_read()` with a valid `phy_device` pointer 111 // `phydev`. 112 let ret = unsafe { 113 bindings::mdiobus_read((*phydev).mdio.bus, (*phydev).mdio.addr, self.0.into()) 114 }; 115 to_result(ret)?; 116 Ok(ret as u16) 117 } 118 119 fn write(&self, dev: &mut Device, val: u16) -> Result { 120 let phydev = dev.0.get(); 121 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`. 122 // So it's just an FFI call, open code of `phy_write()` with a valid `phy_device` pointer 123 // `phydev`. 124 to_result(unsafe { 125 bindings::mdiobus_write((*phydev).mdio.bus, (*phydev).mdio.addr, self.0.into(), val) 126 }) 127 } 128 129 fn read_status(dev: &mut Device) -> Result<u16> { 130 let phydev = dev.0.get(); 131 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Self`. 132 // So it's just an FFI call. 133 let ret = unsafe { bindings::genphy_read_status(phydev) }; 134 to_result(ret)?; 135 Ok(ret as u16) 136 } 137 } 138 139 /// A single MDIO clause 45 register device and address. 140 #[derive(Copy, Clone, Debug)] 141 pub struct Mmd(u8); 142 143 impl Mmd { 144 /// Physical Medium Attachment/Dependent. 145 pub const PMAPMD: Self = Mmd(uapi::MDIO_MMD_PMAPMD as u8); 146 /// WAN interface sublayer. 147 pub const WIS: Self = Mmd(uapi::MDIO_MMD_WIS as u8); 148 /// Physical coding sublayer. 149 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8); 150 /// PHY Extender sublayer. 151 pub const PHYXS: Self = Mmd(uapi::MDIO_MMD_PHYXS as u8); 152 /// DTE Extender sublayer. 153 pub const DTEXS: Self = Mmd(uapi::MDIO_MMD_DTEXS as u8); 154 /// Transmission convergence. 155 pub const TC: Self = Mmd(uapi::MDIO_MMD_TC as u8); 156 /// Auto negotiation. 157 pub const AN: Self = Mmd(uapi::MDIO_MMD_AN as u8); 158 /// Separated PMA (1). 159 pub const SEPARATED_PMA1: Self = Mmd(8); 160 /// Separated PMA (2). 161 pub const SEPARATED_PMA2: Self = Mmd(9); 162 /// Separated PMA (3). 163 pub const SEPARATED_PMA3: Self = Mmd(10); 164 /// Separated PMA (4). 165 pub const SEPARATED_PMA4: Self = Mmd(11); 166 /// OFDM PMA/PMD. 167 pub const OFDM_PMAPMD: Self = Mmd(12); 168 /// Power unit. 169 pub const POWER_UNIT: Self = Mmd(13); 170 /// Clause 22 extension. 171 pub const C22_EXT: Self = Mmd(uapi::MDIO_MMD_C22EXT as u8); 172 /// Vendor specific 1. 173 pub const VEND1: Self = Mmd(uapi::MDIO_MMD_VEND1 as u8); 174 /// Vendor specific 2. 175 pub const VEND2: Self = Mmd(uapi::MDIO_MMD_VEND2 as u8); 176 } 177 178 /// A single MDIO clause 45 register device and address. 179 /// 180 /// Clause 45 uses a 5-bit device address to access a specific MMD within 181 /// a port, then a 16-bit register address to access a location within 182 /// that device. `C45` represents this by storing a [`Mmd`] and 183 /// a register number. 184 pub struct C45 { 185 devad: Mmd, 186 regnum: u16, 187 } 188 189 impl C45 { 190 /// Creates a new instance of `C45`. 191 pub fn new(devad: Mmd, regnum: u16) -> Self { 192 Self { devad, regnum } 193 } 194 } 195 196 impl private::Sealed for C45 {} 197 198 impl Register for C45 { 199 fn read(&self, dev: &mut Device) -> Result<u16> { 200 let phydev = dev.0.get(); 201 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`. 202 // So it's just an FFI call. 203 let ret = 204 unsafe { bindings::phy_read_mmd(phydev, self.devad.0.into(), self.regnum.into()) }; 205 to_result(ret)?; 206 Ok(ret as u16) 207 } 208 209 fn write(&self, dev: &mut Device, val: u16) -> Result { 210 let phydev = dev.0.get(); 211 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`. 212 // So it's just an FFI call. 213 to_result(unsafe { 214 bindings::phy_write_mmd(phydev, self.devad.0.into(), self.regnum.into(), val) 215 }) 216 } 217 218 fn read_status(dev: &mut Device) -> Result<u16> { 219 let phydev = dev.0.get(); 220 // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Self`. 221 // So it's just an FFI call. 222 let ret = unsafe { bindings::genphy_c45_read_status(phydev) }; 223 to_result(ret)?; 224 Ok(ret as u16) 225 } 226 } 227