1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* -*- linux-c -*- ------------------------------------------------------- * 3 * 4 * Copyright 2002 H. Peter Anvin - All Rights Reserved 5 * 6 * ----------------------------------------------------------------------- */ 7 8 /* 9 * raid6/sse1.c 10 * 11 * SSE-1/MMXEXT implementation of RAID-6 syndrome functions 12 * 13 * This is really an MMX implementation, but it requires SSE-1 or 14 * AMD MMXEXT for prefetch support and a few other features. The 15 * support for nontemporal memory accesses is enough to make this 16 * worthwhile as a separate implementation. 17 */ 18 19 #include <asm/cpufeature.h> 20 #include <asm/fpu/api.h> 21 #include "algos.h" 22 23 /* Defined in raid6/mmx.c */ 24 extern const struct raid6_mmx_constants { 25 u64 x1d; 26 } raid6_mmx_constants; 27 28 static int raid6_have_sse1_or_mmxext(void) 29 { 30 /* Not really boot_cpu but "all_cpus" */ 31 return boot_cpu_has(X86_FEATURE_MMX) && 32 (boot_cpu_has(X86_FEATURE_XMM) || 33 boot_cpu_has(X86_FEATURE_MMXEXT)); 34 } 35 36 /* 37 * Plain SSE1 implementation 38 */ 39 static void raid6_sse11_gen_syndrome(int disks, size_t bytes, void **ptrs) 40 { 41 u8 **dptr = (u8 **)ptrs; 42 u8 *p, *q; 43 int d, z, z0; 44 45 z0 = disks - 3; /* Highest data disk */ 46 p = dptr[z0+1]; /* XOR parity */ 47 q = dptr[z0+2]; /* RS syndrome */ 48 49 kernel_fpu_begin(); 50 51 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 52 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 53 54 for ( d = 0 ; d < bytes ; d += 8 ) { 55 asm volatile("prefetchnta %0" : : "m" (dptr[z0][d])); 56 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 57 asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d])); 58 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 59 asm volatile("movq %0,%%mm6" : : "m" (dptr[z0-1][d])); 60 for ( z = z0-2 ; z >= 0 ; z-- ) { 61 asm volatile("prefetchnta %0" : : "m" (dptr[z][d])); 62 asm volatile("pcmpgtb %mm4,%mm5"); 63 asm volatile("paddb %mm4,%mm4"); 64 asm volatile("pand %mm0,%mm5"); 65 asm volatile("pxor %mm5,%mm4"); 66 asm volatile("pxor %mm5,%mm5"); 67 asm volatile("pxor %mm6,%mm2"); 68 asm volatile("pxor %mm6,%mm4"); 69 asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d])); 70 } 71 asm volatile("pcmpgtb %mm4,%mm5"); 72 asm volatile("paddb %mm4,%mm4"); 73 asm volatile("pand %mm0,%mm5"); 74 asm volatile("pxor %mm5,%mm4"); 75 asm volatile("pxor %mm5,%mm5"); 76 asm volatile("pxor %mm6,%mm2"); 77 asm volatile("pxor %mm6,%mm4"); 78 79 asm volatile("movntq %%mm2,%0" : "=m" (p[d])); 80 asm volatile("movntq %%mm4,%0" : "=m" (q[d])); 81 } 82 83 asm volatile("sfence" : : : "memory"); 84 kernel_fpu_end(); 85 } 86 87 const struct raid6_calls raid6_sse1x1 = { 88 .gen_syndrome = raid6_sse11_gen_syndrome, 89 .valid = raid6_have_sse1_or_mmxext, 90 .name = "sse1x1", 91 .priority = 1, /* Has cache hints */ 92 }; 93 94 /* 95 * Unrolled-by-2 SSE1 implementation 96 */ 97 static void raid6_sse12_gen_syndrome(int disks, size_t bytes, void **ptrs) 98 { 99 u8 **dptr = (u8 **)ptrs; 100 u8 *p, *q; 101 int d, z, z0; 102 103 z0 = disks - 3; /* Highest data disk */ 104 p = dptr[z0+1]; /* XOR parity */ 105 q = dptr[z0+2]; /* RS syndrome */ 106 107 kernel_fpu_begin(); 108 109 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 110 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 111 asm volatile("pxor %mm7,%mm7"); /* Zero temp */ 112 113 /* We uniformly assume a single prefetch covers at least 16 bytes */ 114 for ( d = 0 ; d < bytes ; d += 16 ) { 115 asm volatile("prefetchnta %0" : : "m" (dptr[z0][d])); 116 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 117 asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8])); /* P[1] */ 118 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 119 asm volatile("movq %mm3,%mm6"); /* Q[1] */ 120 for ( z = z0-1 ; z >= 0 ; z-- ) { 121 asm volatile("prefetchnta %0" : : "m" (dptr[z][d])); 122 asm volatile("pcmpgtb %mm4,%mm5"); 123 asm volatile("pcmpgtb %mm6,%mm7"); 124 asm volatile("paddb %mm4,%mm4"); 125 asm volatile("paddb %mm6,%mm6"); 126 asm volatile("pand %mm0,%mm5"); 127 asm volatile("pand %mm0,%mm7"); 128 asm volatile("pxor %mm5,%mm4"); 129 asm volatile("pxor %mm7,%mm6"); 130 asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d])); 131 asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8])); 132 asm volatile("pxor %mm5,%mm2"); 133 asm volatile("pxor %mm7,%mm3"); 134 asm volatile("pxor %mm5,%mm4"); 135 asm volatile("pxor %mm7,%mm6"); 136 asm volatile("pxor %mm5,%mm5"); 137 asm volatile("pxor %mm7,%mm7"); 138 } 139 asm volatile("movntq %%mm2,%0" : "=m" (p[d])); 140 asm volatile("movntq %%mm3,%0" : "=m" (p[d+8])); 141 asm volatile("movntq %%mm4,%0" : "=m" (q[d])); 142 asm volatile("movntq %%mm6,%0" : "=m" (q[d+8])); 143 } 144 145 asm volatile("sfence" : :: "memory"); 146 kernel_fpu_end(); 147 } 148 149 const struct raid6_calls raid6_sse1x2 = { 150 .gen_syndrome = raid6_sse12_gen_syndrome, 151 .valid = raid6_have_sse1_or_mmxext, 152 .name = "sse1x2", 153 .priority = 1, /* Has cache hints */ 154 }; 155