1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* -*- linux-c -*- ------------------------------------------------------- * 3 * 4 * Copyright 2002 H. Peter Anvin - All Rights Reserved 5 * 6 * ----------------------------------------------------------------------- */ 7 8 /* 9 * raid6/mmx.c 10 * 11 * MMX implementation of RAID-6 syndrome functions 12 */ 13 14 #include <linux/raid/pq.h> 15 #include <asm/fpu/api.h> 16 17 /* Shared with raid6/sse1.c */ 18 const struct raid6_mmx_constants { 19 u64 x1d; 20 } raid6_mmx_constants = { 21 0x1d1d1d1d1d1d1d1dULL, 22 }; 23 24 static int raid6_have_mmx(void) 25 { 26 /* Not really "boot_cpu" but "all_cpus" */ 27 return boot_cpu_has(X86_FEATURE_MMX); 28 } 29 30 /* 31 * Plain MMX implementation 32 */ 33 static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs) 34 { 35 u8 **dptr = (u8 **)ptrs; 36 u8 *p, *q; 37 int d, z, z0; 38 39 z0 = disks - 3; /* Highest data disk */ 40 p = dptr[z0+1]; /* XOR parity */ 41 q = dptr[z0+2]; /* RS syndrome */ 42 43 kernel_fpu_begin(); 44 45 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 46 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 47 48 for ( d = 0 ; d < bytes ; d += 8 ) { 49 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 50 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 51 for ( z = z0-1 ; z >= 0 ; z-- ) { 52 asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d])); 53 asm volatile("pcmpgtb %mm4,%mm5"); 54 asm volatile("paddb %mm4,%mm4"); 55 asm volatile("pand %mm0,%mm5"); 56 asm volatile("pxor %mm5,%mm4"); 57 asm volatile("pxor %mm5,%mm5"); 58 asm volatile("pxor %mm6,%mm2"); 59 asm volatile("pxor %mm6,%mm4"); 60 } 61 asm volatile("movq %%mm2,%0" : "=m" (p[d])); 62 asm volatile("pxor %mm2,%mm2"); 63 asm volatile("movq %%mm4,%0" : "=m" (q[d])); 64 asm volatile("pxor %mm4,%mm4"); 65 } 66 67 kernel_fpu_end(); 68 } 69 70 const struct raid6_calls raid6_mmxx1 = { 71 .gen_syndrome = raid6_mmx1_gen_syndrome, 72 .valid = raid6_have_mmx, 73 .name = "mmxx1", 74 }; 75 76 /* 77 * Unrolled-by-2 MMX implementation 78 */ 79 static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs) 80 { 81 u8 **dptr = (u8 **)ptrs; 82 u8 *p, *q; 83 int d, z, z0; 84 85 z0 = disks - 3; /* Highest data disk */ 86 p = dptr[z0+1]; /* XOR parity */ 87 q = dptr[z0+2]; /* RS syndrome */ 88 89 kernel_fpu_begin(); 90 91 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 92 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 93 asm volatile("pxor %mm7,%mm7"); /* Zero temp */ 94 95 for ( d = 0 ; d < bytes ; d += 16 ) { 96 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 97 asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8])); 98 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 99 asm volatile("movq %mm3,%mm6"); /* Q[1] */ 100 for ( z = z0-1 ; z >= 0 ; z-- ) { 101 asm volatile("pcmpgtb %mm4,%mm5"); 102 asm volatile("pcmpgtb %mm6,%mm7"); 103 asm volatile("paddb %mm4,%mm4"); 104 asm volatile("paddb %mm6,%mm6"); 105 asm volatile("pand %mm0,%mm5"); 106 asm volatile("pand %mm0,%mm7"); 107 asm volatile("pxor %mm5,%mm4"); 108 asm volatile("pxor %mm7,%mm6"); 109 asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d])); 110 asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8])); 111 asm volatile("pxor %mm5,%mm2"); 112 asm volatile("pxor %mm7,%mm3"); 113 asm volatile("pxor %mm5,%mm4"); 114 asm volatile("pxor %mm7,%mm6"); 115 asm volatile("pxor %mm5,%mm5"); 116 asm volatile("pxor %mm7,%mm7"); 117 } 118 asm volatile("movq %%mm2,%0" : "=m" (p[d])); 119 asm volatile("movq %%mm3,%0" : "=m" (p[d+8])); 120 asm volatile("movq %%mm4,%0" : "=m" (q[d])); 121 asm volatile("movq %%mm6,%0" : "=m" (q[d+8])); 122 } 123 124 kernel_fpu_end(); 125 } 126 127 const struct raid6_calls raid6_mmxx2 = { 128 .gen_syndrome = raid6_mmx2_gen_syndrome, 129 .valid = raid6_have_mmx, 130 .name = "mmxx2", 131 }; 132