1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* -*- linux-c -*- ------------------------------------------------------- * 3 * 4 * Copyright 2002 H. Peter Anvin - All Rights Reserved 5 * 6 * ----------------------------------------------------------------------- */ 7 8 /* 9 * raid6/mmx.c 10 * 11 * MMX implementation of RAID-6 syndrome functions 12 */ 13 14 #include <asm/cpufeature.h> 15 #include <asm/fpu/api.h> 16 #include "algos.h" 17 18 /* Shared with raid6/sse1.c */ 19 const struct raid6_mmx_constants { 20 u64 x1d; 21 } raid6_mmx_constants = { 22 0x1d1d1d1d1d1d1d1dULL, 23 }; 24 25 static int raid6_have_mmx(void) 26 { 27 /* Not really "boot_cpu" but "all_cpus" */ 28 return boot_cpu_has(X86_FEATURE_MMX); 29 } 30 31 /* 32 * Plain MMX implementation 33 */ 34 static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs) 35 { 36 u8 **dptr = (u8 **)ptrs; 37 u8 *p, *q; 38 int d, z, z0; 39 40 z0 = disks - 3; /* Highest data disk */ 41 p = dptr[z0+1]; /* XOR parity */ 42 q = dptr[z0+2]; /* RS syndrome */ 43 44 kernel_fpu_begin(); 45 46 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 47 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 48 49 for ( d = 0 ; d < bytes ; d += 8 ) { 50 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 51 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 52 for ( z = z0-1 ; z >= 0 ; z-- ) { 53 asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d])); 54 asm volatile("pcmpgtb %mm4,%mm5"); 55 asm volatile("paddb %mm4,%mm4"); 56 asm volatile("pand %mm0,%mm5"); 57 asm volatile("pxor %mm5,%mm4"); 58 asm volatile("pxor %mm5,%mm5"); 59 asm volatile("pxor %mm6,%mm2"); 60 asm volatile("pxor %mm6,%mm4"); 61 } 62 asm volatile("movq %%mm2,%0" : "=m" (p[d])); 63 asm volatile("pxor %mm2,%mm2"); 64 asm volatile("movq %%mm4,%0" : "=m" (q[d])); 65 asm volatile("pxor %mm4,%mm4"); 66 } 67 68 kernel_fpu_end(); 69 } 70 71 const struct raid6_calls raid6_mmxx1 = { 72 .gen_syndrome = raid6_mmx1_gen_syndrome, 73 .valid = raid6_have_mmx, 74 .name = "mmxx1", 75 }; 76 77 /* 78 * Unrolled-by-2 MMX implementation 79 */ 80 static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs) 81 { 82 u8 **dptr = (u8 **)ptrs; 83 u8 *p, *q; 84 int d, z, z0; 85 86 z0 = disks - 3; /* Highest data disk */ 87 p = dptr[z0+1]; /* XOR parity */ 88 q = dptr[z0+2]; /* RS syndrome */ 89 90 kernel_fpu_begin(); 91 92 asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); 93 asm volatile("pxor %mm5,%mm5"); /* Zero temp */ 94 asm volatile("pxor %mm7,%mm7"); /* Zero temp */ 95 96 for ( d = 0 ; d < bytes ; d += 16 ) { 97 asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ 98 asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8])); 99 asm volatile("movq %mm2,%mm4"); /* Q[0] */ 100 asm volatile("movq %mm3,%mm6"); /* Q[1] */ 101 for ( z = z0-1 ; z >= 0 ; z-- ) { 102 asm volatile("pcmpgtb %mm4,%mm5"); 103 asm volatile("pcmpgtb %mm6,%mm7"); 104 asm volatile("paddb %mm4,%mm4"); 105 asm volatile("paddb %mm6,%mm6"); 106 asm volatile("pand %mm0,%mm5"); 107 asm volatile("pand %mm0,%mm7"); 108 asm volatile("pxor %mm5,%mm4"); 109 asm volatile("pxor %mm7,%mm6"); 110 asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d])); 111 asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8])); 112 asm volatile("pxor %mm5,%mm2"); 113 asm volatile("pxor %mm7,%mm3"); 114 asm volatile("pxor %mm5,%mm4"); 115 asm volatile("pxor %mm7,%mm6"); 116 asm volatile("pxor %mm5,%mm5"); 117 asm volatile("pxor %mm7,%mm7"); 118 } 119 asm volatile("movq %%mm2,%0" : "=m" (p[d])); 120 asm volatile("movq %%mm3,%0" : "=m" (p[d+8])); 121 asm volatile("movq %%mm4,%0" : "=m" (q[d])); 122 asm volatile("movq %%mm6,%0" : "=m" (q[d+8])); 123 } 124 125 kernel_fpu_end(); 126 } 127 128 const struct raid6_calls raid6_mmxx2 = { 129 .gen_syndrome = raid6_mmx2_gen_syndrome, 130 .valid = raid6_have_mmx, 131 .name = "mmxx2", 132 }; 133