1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2d9817ebeSThomas Gleixnermenu "IRQ subsystem" 3d9817ebeSThomas Gleixner# Options selectable by the architecture code 4c68fd4f3SThomas Gleixner 5c68fd4f3SThomas Gleixner# Make sparse irq Kconfig switch below available 62ed86b16SRob Herringconfig MAY_HAVE_SPARSE_IRQ 7fd4afaf3SJan Beulich bool 8d9817ebeSThomas Gleixner 9c940e01cSThomas Gleixner# Legacy support, required for itanic 10c940e01cSThomas Gleixnerconfig GENERIC_IRQ_LEGACY 11c940e01cSThomas Gleixner bool 12c940e01cSThomas Gleixner 13c68fd4f3SThomas Gleixner# Enable the generic irq autoprobe mechanism 14d9817ebeSThomas Gleixnerconfig GENERIC_IRQ_PROBE 15fd4afaf3SJan Beulich bool 16d9817ebeSThomas Gleixner 17c68fd4f3SThomas Gleixner# Use the generic /proc/interrupts implementation 18c78b9b65SThomas Gleixnerconfig GENERIC_IRQ_SHOW 19fd4afaf3SJan Beulich bool 20c78b9b65SThomas Gleixner 21ab7798ffSThomas Gleixner# Print level/edge extra information 22ab7798ffSThomas Gleixnerconfig GENERIC_IRQ_SHOW_LEVEL 23ab7798ffSThomas Gleixner bool 24ab7798ffSThomas Gleixner 250d3f5425SThomas Gleixner# Supports effective affinity mask 260d3f5425SThomas Gleixnerconfig GENERIC_IRQ_EFFECTIVE_AFF_MASK 270e6c027cSSamuel Holland depends on SMP 280d3f5425SThomas Gleixner bool 290d3f5425SThomas Gleixner 30c68fd4f3SThomas Gleixner# Support for delayed migration from interrupt context 31d9817ebeSThomas Gleixnerconfig GENERIC_PENDING_IRQ 32fd4afaf3SJan Beulich bool 33d9817ebeSThomas Gleixner 34*a648eb3aSThomas Gleixner# Deduce delayed migration from top-level interrupt chip flags 35*a648eb3aSThomas Gleixnerconfig GENERIC_PENDING_IRQ_CHIPFLAGS 36*a648eb3aSThomas Gleixner bool 37*a648eb3aSThomas Gleixner 38f1e0bb0aSYang Yingliang# Support for generic irq migrating off cpu before the cpu is offline. 39f1e0bb0aSYang Yingliangconfig GENERIC_IRQ_MIGRATION 40f1e0bb0aSYang Yingliang bool 41f1e0bb0aSYang Yingliang 42c68fd4f3SThomas Gleixner# Alpha specific irq affinity mechanism 43d9817ebeSThomas Gleixnerconfig AUTO_IRQ_AFFINITY 44fd4afaf3SJan Beulich bool 45d9817ebeSThomas Gleixner 46acd26bcfSThomas Gleixner# Interrupt injection mechanism 47acd26bcfSThomas Gleixnerconfig GENERIC_IRQ_INJECTION 48acd26bcfSThomas Gleixner bool 49acd26bcfSThomas Gleixner 50c68fd4f3SThomas Gleixner# Tasklet based software resend for pending interrupts on enable_irq() 51d9817ebeSThomas Gleixnerconfig HARDIRQS_SW_RESEND 52fd4afaf3SJan Beulich bool 53d9817ebeSThomas Gleixner 540521c8fbSThomas Gleixner# Edge style eoi based handler (cell) 550521c8fbSThomas Gleixnerconfig IRQ_EDGE_EOI_HANDLER 560521c8fbSThomas Gleixner bool 570521c8fbSThomas Gleixner 58c42321c7SThomas Gleixner# Generic configurable interrupt chip implementation 59c42321c7SThomas Gleixnerconfig GENERIC_IRQ_CHIP 60c42321c7SThomas Gleixner bool 61923fa4eaSNitin A Kamble select IRQ_DOMAIN 62c42321c7SThomas Gleixner 6308a543adSGrant Likely# Generic irq_domain hw <--> linux irq number translation 6408a543adSGrant Likelyconfig IRQ_DOMAIN 6508a543adSGrant Likely bool 6608a543adSGrant Likely 67b19af510SBartosz Golaszewski# Support for simulated interrupts 68b19af510SBartosz Golaszewskiconfig IRQ_SIM 69b19af510SBartosz Golaszewski bool 70b19af510SBartosz Golaszewski select IRQ_WORK 71337cbeb2SBartosz Golaszewski select IRQ_DOMAIN 72b19af510SBartosz Golaszewski 73f8264e34SJiang Liu# Support for hierarchical irq domains 74f8264e34SJiang Liuconfig IRQ_DOMAIN_HIERARCHY 75f8264e34SJiang Liu bool 76f8264e34SJiang Liu select IRQ_DOMAIN 77f8264e34SJiang Liu 78e37af801SMarc Zyngier# Support for obsolete non-mapping irq domains 79e37af801SMarc Zyngierconfig IRQ_DOMAIN_NOMAP 80e37af801SMarc Zyngier bool 81e37af801SMarc Zyngier select IRQ_DOMAIN 82e37af801SMarc Zyngier 837703b08cSDavid Daney# Support for hierarchical fasteoi+edge and fasteoi+level handlers 847703b08cSDavid Daneyconfig IRQ_FASTEOI_HIERARCHY_HANDLERS 857703b08cSDavid Daney bool 867703b08cSDavid Daney 87379b6564SQais Yousef# Generic IRQ IPI support 88379b6564SQais Yousefconfig GENERIC_IRQ_IPI 89379b6564SQais Yousef bool 900f5209feSSamuel Holland depends on SMP 91151a5351SMarc Zyngier select IRQ_DOMAIN_HIERARCHY 92379b6564SQais Yousef 93835a486cSAnup Patel# Generic IRQ IPI Mux support 94835a486cSAnup Patelconfig GENERIC_IRQ_IPI_MUX 95835a486cSAnup Patel bool 96835a486cSAnup Patel depends on SMP 97835a486cSAnup Patel 9813e7accbSThomas Gleixner# Generic MSI hierarchical interrupt domain support 99f3cf8bb0SJiang Liuconfig GENERIC_MSI_IRQ 100f3cf8bb0SJiang Liu bool 101f3cf8bb0SJiang Liu select IRQ_DOMAIN_HIERARCHY 102f3cf8bb0SJiang Liu 103aaebdf8dSJulien Grallconfig IRQ_MSI_IOMMU 104aaebdf8dSJulien Grall bool 105aaebdf8dSJulien Grall 106b2d3d61aSDaniel Lezcanoconfig IRQ_TIMINGS 107b2d3d61aSDaniel Lezcano bool 108b2d3d61aSDaniel Lezcano 1092f75d9e1SThomas Gleixnerconfig GENERIC_IRQ_MATRIX_ALLOCATOR 1102f75d9e1SThomas Gleixner bool 1112f75d9e1SThomas Gleixner 1122b5175c4SThomas Gleixnerconfig GENERIC_IRQ_RESERVATION_MODE 1132b5175c4SThomas Gleixner bool 1142b5175c4SThomas Gleixner 11599cf63c5SBitao Hu# Snapshot for interrupt statistics 11699cf63c5SBitao Huconfig GENERIC_IRQ_STAT_SNAPSHOT 11799cf63c5SBitao Hu bool 11899cf63c5SBitao Hu 119c68fd4f3SThomas Gleixner# Support forced irq threading 1208d32a307SThomas Gleixnerconfig IRQ_FORCED_THREADING 1218d32a307SThomas Gleixner bool 1228d32a307SThomas Gleixner 123d9817ebeSThomas Gleixnerconfig SPARSE_IRQ 1242ed86b16SRob Herring bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ 125a7f7f624SMasahiro Yamada help 126d9817ebeSThomas Gleixner 127d9817ebeSThomas Gleixner Sparse irq numbering is useful for distro kernels that want 128d9817ebeSThomas Gleixner to define a high CONFIG_NR_CPUS value but still want to have 129d9817ebeSThomas Gleixner low kernel memory footprint on smaller machines. 130d9817ebeSThomas Gleixner 131d9817ebeSThomas Gleixner ( Sparse irqs can also be beneficial on NUMA boxes, as they spread 132d9817ebeSThomas Gleixner out the interrupt descriptors in a more NUMA-friendly way. ) 133d9817ebeSThomas Gleixner 134d9817ebeSThomas Gleixner If you don't know what to do here, say N. 135d9817ebeSThomas Gleixner 136087cdfb6SThomas Gleixnerconfig GENERIC_IRQ_DEBUGFS 137087cdfb6SThomas Gleixner bool "Expose irq internals in debugfs" 138087cdfb6SThomas Gleixner depends on DEBUG_FS 139acd26bcfSThomas Gleixner select GENERIC_IRQ_INJECTION 140087cdfb6SThomas Gleixner default n 141a7f7f624SMasahiro Yamada help 142087cdfb6SThomas Gleixner 143087cdfb6SThomas Gleixner Exposes internal state information through debugfs. Mostly for 144087cdfb6SThomas Gleixner developers and debugging of hard to diagnose interrupt problems. 145087cdfb6SThomas Gleixner 146087cdfb6SThomas Gleixner If you don't know what to do here, say N. 147087cdfb6SThomas Gleixner 148bad6722eSEliav Farber# Clear forwarded VM interrupts during kexec. 149bad6722eSEliav Farber# This option ensures the kernel clears active states for interrupts 150bad6722eSEliav Farber# forwarded to virtual machines (VMs) during a machine kexec. 151bad6722eSEliav Farberconfig GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 152bad6722eSEliav Farber bool 153bad6722eSEliav Farber 154d9817ebeSThomas Gleixnerendmenu 155caacdbf4SPalmer Dabbelt 156caacdbf4SPalmer Dabbeltconfig GENERIC_IRQ_MULTI_HANDLER 157caacdbf4SPalmer Dabbelt bool 158caacdbf4SPalmer Dabbelt help 159caacdbf4SPalmer Dabbelt Allow to specify the low level IRQ handler at run time. 1608d15a729SMarc Zyngier 1618d15a729SMarc Zyngier# Cavium Octeon is the last system to use this deprecated option 1628d15a729SMarc Zyngier# Do not even think of enabling this on any new platform 1638d15a729SMarc Zyngierconfig DEPRECATED_IRQ_CPU_ONOFFLINE 1648d15a729SMarc Zyngier bool 1658d15a729SMarc Zyngier depends on CAVIUM_OCTEON_SOC 1668d15a729SMarc Zyngier default CAVIUM_OCTEON_SOC 167