1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2d9817ebeSThomas Gleixnermenu "IRQ subsystem" 3d9817ebeSThomas Gleixner# Options selectable by the architecture code 4c68fd4f3SThomas Gleixner 5c68fd4f3SThomas Gleixner# Make sparse irq Kconfig switch below available 62ed86b16SRob Herringconfig MAY_HAVE_SPARSE_IRQ 7fd4afaf3SJan Beulich bool 8d9817ebeSThomas Gleixner 9c940e01cSThomas Gleixner# Legacy support, required for itanic 10c940e01cSThomas Gleixnerconfig GENERIC_IRQ_LEGACY 11c940e01cSThomas Gleixner bool 12c940e01cSThomas Gleixner 13c68fd4f3SThomas Gleixner# Enable the generic irq autoprobe mechanism 14d9817ebeSThomas Gleixnerconfig GENERIC_IRQ_PROBE 15fd4afaf3SJan Beulich bool 16d9817ebeSThomas Gleixner 17c68fd4f3SThomas Gleixner# Use the generic /proc/interrupts implementation 18c78b9b65SThomas Gleixnerconfig GENERIC_IRQ_SHOW 19fd4afaf3SJan Beulich bool 20c78b9b65SThomas Gleixner 21ab7798ffSThomas Gleixner# Print level/edge extra information 22ab7798ffSThomas Gleixnerconfig GENERIC_IRQ_SHOW_LEVEL 23ab7798ffSThomas Gleixner bool 24ab7798ffSThomas Gleixner 250d3f5425SThomas Gleixner# Supports effective affinity mask 260d3f5425SThomas Gleixnerconfig GENERIC_IRQ_EFFECTIVE_AFF_MASK 270d3f5425SThomas Gleixner bool 280d3f5425SThomas Gleixner 29c68fd4f3SThomas Gleixner# Support for delayed migration from interrupt context 30d9817ebeSThomas Gleixnerconfig GENERIC_PENDING_IRQ 31fd4afaf3SJan Beulich bool 32d9817ebeSThomas Gleixner 33f1e0bb0aSYang Yingliang# Support for generic irq migrating off cpu before the cpu is offline. 34f1e0bb0aSYang Yingliangconfig GENERIC_IRQ_MIGRATION 35f1e0bb0aSYang Yingliang bool 36f1e0bb0aSYang Yingliang 37c68fd4f3SThomas Gleixner# Alpha specific irq affinity mechanism 38d9817ebeSThomas Gleixnerconfig AUTO_IRQ_AFFINITY 39fd4afaf3SJan Beulich bool 40d9817ebeSThomas Gleixner 41acd26bcfSThomas Gleixner# Interrupt injection mechanism 42acd26bcfSThomas Gleixnerconfig GENERIC_IRQ_INJECTION 43acd26bcfSThomas Gleixner bool 44acd26bcfSThomas Gleixner 45c68fd4f3SThomas Gleixner# Tasklet based software resend for pending interrupts on enable_irq() 46d9817ebeSThomas Gleixnerconfig HARDIRQS_SW_RESEND 47fd4afaf3SJan Beulich bool 48d9817ebeSThomas Gleixner 490521c8fbSThomas Gleixner# Edge style eoi based handler (cell) 500521c8fbSThomas Gleixnerconfig IRQ_EDGE_EOI_HANDLER 510521c8fbSThomas Gleixner bool 520521c8fbSThomas Gleixner 53c42321c7SThomas Gleixner# Generic configurable interrupt chip implementation 54c42321c7SThomas Gleixnerconfig GENERIC_IRQ_CHIP 55c42321c7SThomas Gleixner bool 56923fa4eaSNitin A Kamble select IRQ_DOMAIN 57c42321c7SThomas Gleixner 5808a543adSGrant Likely# Generic irq_domain hw <--> linux irq number translation 5908a543adSGrant Likelyconfig IRQ_DOMAIN 6008a543adSGrant Likely bool 6108a543adSGrant Likely 62b19af510SBartosz Golaszewski# Support for simulated interrupts 63b19af510SBartosz Golaszewskiconfig IRQ_SIM 64b19af510SBartosz Golaszewski bool 65b19af510SBartosz Golaszewski select IRQ_WORK 66337cbeb2SBartosz Golaszewski select IRQ_DOMAIN 67b19af510SBartosz Golaszewski 68f8264e34SJiang Liu# Support for hierarchical irq domains 69f8264e34SJiang Liuconfig IRQ_DOMAIN_HIERARCHY 70f8264e34SJiang Liu bool 71f8264e34SJiang Liu select IRQ_DOMAIN 72f8264e34SJiang Liu 73e37af801SMarc Zyngier# Support for obsolete non-mapping irq domains 74e37af801SMarc Zyngierconfig IRQ_DOMAIN_NOMAP 75e37af801SMarc Zyngier bool 76e37af801SMarc Zyngier select IRQ_DOMAIN 77e37af801SMarc Zyngier 787703b08cSDavid Daney# Support for hierarchical fasteoi+edge and fasteoi+level handlers 797703b08cSDavid Daneyconfig IRQ_FASTEOI_HIERARCHY_HANDLERS 807703b08cSDavid Daney bool 817703b08cSDavid Daney 82379b6564SQais Yousef# Generic IRQ IPI support 83379b6564SQais Yousefconfig GENERIC_IRQ_IPI 84379b6564SQais Yousef bool 85*0f5209feSSamuel Holland depends on SMP 86151a5351SMarc Zyngier select IRQ_DOMAIN_HIERARCHY 87379b6564SQais Yousef 88f3cf8bb0SJiang Liu# Generic MSI interrupt support 89f3cf8bb0SJiang Liuconfig GENERIC_MSI_IRQ 90f3cf8bb0SJiang Liu bool 91f3cf8bb0SJiang Liu 92f3cf8bb0SJiang Liu# Generic MSI hierarchical interrupt domain support 93f3cf8bb0SJiang Liuconfig GENERIC_MSI_IRQ_DOMAIN 94f3cf8bb0SJiang Liu bool 95f3cf8bb0SJiang Liu select IRQ_DOMAIN_HIERARCHY 96f3cf8bb0SJiang Liu select GENERIC_MSI_IRQ 97f3cf8bb0SJiang Liu 98aaebdf8dSJulien Grallconfig IRQ_MSI_IOMMU 99aaebdf8dSJulien Grall bool 100aaebdf8dSJulien Grall 101b2d3d61aSDaniel Lezcanoconfig IRQ_TIMINGS 102b2d3d61aSDaniel Lezcano bool 103b2d3d61aSDaniel Lezcano 1042f75d9e1SThomas Gleixnerconfig GENERIC_IRQ_MATRIX_ALLOCATOR 1052f75d9e1SThomas Gleixner bool 1062f75d9e1SThomas Gleixner 1072b5175c4SThomas Gleixnerconfig GENERIC_IRQ_RESERVATION_MODE 1082b5175c4SThomas Gleixner bool 1092b5175c4SThomas Gleixner 110c68fd4f3SThomas Gleixner# Support forced irq threading 1118d32a307SThomas Gleixnerconfig IRQ_FORCED_THREADING 1128d32a307SThomas Gleixner bool 1138d32a307SThomas Gleixner 114d9817ebeSThomas Gleixnerconfig SPARSE_IRQ 1152ed86b16SRob Herring bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ 116a7f7f624SMasahiro Yamada help 117d9817ebeSThomas Gleixner 118d9817ebeSThomas Gleixner Sparse irq numbering is useful for distro kernels that want 119d9817ebeSThomas Gleixner to define a high CONFIG_NR_CPUS value but still want to have 120d9817ebeSThomas Gleixner low kernel memory footprint on smaller machines. 121d9817ebeSThomas Gleixner 122d9817ebeSThomas Gleixner ( Sparse irqs can also be beneficial on NUMA boxes, as they spread 123d9817ebeSThomas Gleixner out the interrupt descriptors in a more NUMA-friendly way. ) 124d9817ebeSThomas Gleixner 125d9817ebeSThomas Gleixner If you don't know what to do here, say N. 126d9817ebeSThomas Gleixner 127087cdfb6SThomas Gleixnerconfig GENERIC_IRQ_DEBUGFS 128087cdfb6SThomas Gleixner bool "Expose irq internals in debugfs" 129087cdfb6SThomas Gleixner depends on DEBUG_FS 130acd26bcfSThomas Gleixner select GENERIC_IRQ_INJECTION 131087cdfb6SThomas Gleixner default n 132a7f7f624SMasahiro Yamada help 133087cdfb6SThomas Gleixner 134087cdfb6SThomas Gleixner Exposes internal state information through debugfs. Mostly for 135087cdfb6SThomas Gleixner developers and debugging of hard to diagnose interrupt problems. 136087cdfb6SThomas Gleixner 137087cdfb6SThomas Gleixner If you don't know what to do here, say N. 138087cdfb6SThomas Gleixner 139d9817ebeSThomas Gleixnerendmenu 140caacdbf4SPalmer Dabbelt 141caacdbf4SPalmer Dabbeltconfig GENERIC_IRQ_MULTI_HANDLER 142caacdbf4SPalmer Dabbelt bool 143caacdbf4SPalmer Dabbelt help 144caacdbf4SPalmer Dabbelt Allow to specify the low level IRQ handler at run time. 1458d15a729SMarc Zyngier 1468d15a729SMarc Zyngier# Cavium Octeon is the last system to use this deprecated option 1478d15a729SMarc Zyngier# Do not even think of enabling this on any new platform 1488d15a729SMarc Zyngierconfig DEPRECATED_IRQ_CPU_ONOFFLINE 1498d15a729SMarc Zyngier bool 1508d15a729SMarc Zyngier depends on CAVIUM_OCTEON_SOC 1518d15a729SMarc Zyngier default CAVIUM_OCTEON_SOC 152