1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch-independent dma-mapping routines 4 * 5 * Copyright (c) 2006 SUSE Linux Products GmbH 6 * Copyright (c) 2006 Tejun Heo <teheo@suse.de> 7 */ 8 #include <linux/memblock.h> /* for max_pfn */ 9 #include <linux/acpi.h> 10 #include <linux/dma-map-ops.h> 11 #include <linux/export.h> 12 #include <linux/gfp.h> 13 #include <linux/iommu-dma.h> 14 #include <linux/kmsan.h> 15 #include <linux/of_device.h> 16 #include <linux/slab.h> 17 #include <linux/vmalloc.h> 18 #include "debug.h" 19 #include "direct.h" 20 21 #define CREATE_TRACE_POINTS 22 #include <trace/events/dma.h> 23 24 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ 25 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ 26 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) 27 bool dma_default_coherent = IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT); 28 #endif 29 30 /* 31 * Managed DMA API 32 */ 33 struct dma_devres { 34 size_t size; 35 void *vaddr; 36 dma_addr_t dma_handle; 37 unsigned long attrs; 38 }; 39 40 static void dmam_release(struct device *dev, void *res) 41 { 42 struct dma_devres *this = res; 43 44 dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle, 45 this->attrs); 46 } 47 48 static int dmam_match(struct device *dev, void *res, void *match_data) 49 { 50 struct dma_devres *this = res, *match = match_data; 51 52 if (this->vaddr == match->vaddr) { 53 WARN_ON(this->size != match->size || 54 this->dma_handle != match->dma_handle); 55 return 1; 56 } 57 return 0; 58 } 59 60 /** 61 * dmam_free_coherent - Managed dma_free_coherent() 62 * @dev: Device to free coherent memory for 63 * @size: Size of allocation 64 * @vaddr: Virtual address of the memory to free 65 * @dma_handle: DMA handle of the memory to free 66 * 67 * Managed dma_free_coherent(). 68 */ 69 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, 70 dma_addr_t dma_handle) 71 { 72 struct dma_devres match_data = { size, vaddr, dma_handle }; 73 74 WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data)); 75 dma_free_coherent(dev, size, vaddr, dma_handle); 76 } 77 EXPORT_SYMBOL(dmam_free_coherent); 78 79 /** 80 * dmam_alloc_attrs - Managed dma_alloc_attrs() 81 * @dev: Device to allocate non_coherent memory for 82 * @size: Size of allocation 83 * @dma_handle: Out argument for allocated DMA handle 84 * @gfp: Allocation flags 85 * @attrs: Flags in the DMA_ATTR_* namespace. 86 * 87 * Managed dma_alloc_attrs(). Memory allocated using this function will be 88 * automatically released on driver detach. 89 * 90 * RETURNS: 91 * Pointer to allocated memory on success, NULL on failure. 92 */ 93 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 94 gfp_t gfp, unsigned long attrs) 95 { 96 struct dma_devres *dr; 97 void *vaddr; 98 99 dr = devres_alloc(dmam_release, sizeof(*dr), gfp); 100 if (!dr) 101 return NULL; 102 103 vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs); 104 if (!vaddr) { 105 devres_free(dr); 106 return NULL; 107 } 108 109 dr->vaddr = vaddr; 110 dr->dma_handle = *dma_handle; 111 dr->size = size; 112 dr->attrs = attrs; 113 114 devres_add(dev, dr); 115 116 return vaddr; 117 } 118 EXPORT_SYMBOL(dmam_alloc_attrs); 119 120 static bool dma_go_direct(struct device *dev, dma_addr_t mask, 121 const struct dma_map_ops *ops) 122 { 123 if (use_dma_iommu(dev)) 124 return false; 125 126 if (likely(!ops)) 127 return true; 128 129 #ifdef CONFIG_DMA_OPS_BYPASS 130 if (dev->dma_ops_bypass) 131 return min_not_zero(mask, dev->bus_dma_limit) >= 132 dma_direct_get_required_mask(dev); 133 #endif 134 return false; 135 } 136 137 138 /* 139 * Check if the devices uses a direct mapping for streaming DMA operations. 140 * This allows IOMMU drivers to set a bypass mode if the DMA mask is large 141 * enough. 142 */ 143 static inline bool dma_alloc_direct(struct device *dev, 144 const struct dma_map_ops *ops) 145 { 146 return dma_go_direct(dev, dev->coherent_dma_mask, ops); 147 } 148 149 static inline bool dma_map_direct(struct device *dev, 150 const struct dma_map_ops *ops) 151 { 152 return dma_go_direct(dev, *dev->dma_mask, ops); 153 } 154 155 dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, 156 enum dma_data_direction dir, unsigned long attrs) 157 { 158 const struct dma_map_ops *ops = get_dma_ops(dev); 159 bool is_mmio = attrs & DMA_ATTR_MMIO; 160 dma_addr_t addr = DMA_MAPPING_ERROR; 161 162 BUG_ON(!valid_dma_direction(dir)); 163 164 if (WARN_ON_ONCE(!dev->dma_mask)) 165 return DMA_MAPPING_ERROR; 166 167 if (!dev_is_dma_coherent(dev) && (attrs & DMA_ATTR_REQUIRE_COHERENT)) 168 return DMA_MAPPING_ERROR; 169 170 if (dma_map_direct(dev, ops) || 171 (!is_mmio && arch_dma_map_phys_direct(dev, phys + size))) 172 addr = dma_direct_map_phys(dev, phys, size, dir, attrs); 173 else if (use_dma_iommu(dev)) 174 addr = iommu_dma_map_phys(dev, phys, size, dir, attrs); 175 else if (ops->map_phys) 176 addr = ops->map_phys(dev, phys, size, dir, attrs); 177 178 if (!is_mmio) 179 kmsan_handle_dma(phys, size, dir); 180 trace_dma_map_phys(dev, phys, addr, size, dir, attrs); 181 debug_dma_map_phys(dev, phys, size, dir, addr, attrs); 182 183 return addr; 184 } 185 EXPORT_SYMBOL_GPL(dma_map_phys); 186 187 dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, 188 size_t offset, size_t size, enum dma_data_direction dir, 189 unsigned long attrs) 190 { 191 phys_addr_t phys = page_to_phys(page) + offset; 192 193 if (unlikely(attrs & DMA_ATTR_MMIO)) 194 return DMA_MAPPING_ERROR; 195 196 if (IS_ENABLED(CONFIG_DMA_API_DEBUG) && 197 WARN_ON_ONCE(is_zone_device_page(page))) 198 return DMA_MAPPING_ERROR; 199 200 return dma_map_phys(dev, phys, size, dir, attrs); 201 } 202 EXPORT_SYMBOL(dma_map_page_attrs); 203 204 void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, 205 enum dma_data_direction dir, unsigned long attrs) 206 { 207 const struct dma_map_ops *ops = get_dma_ops(dev); 208 bool is_mmio = attrs & DMA_ATTR_MMIO; 209 210 BUG_ON(!valid_dma_direction(dir)); 211 if (dma_map_direct(dev, ops) || 212 (!is_mmio && arch_dma_unmap_phys_direct(dev, addr + size))) 213 dma_direct_unmap_phys(dev, addr, size, dir, attrs); 214 else if (use_dma_iommu(dev)) 215 iommu_dma_unmap_phys(dev, addr, size, dir, attrs); 216 else if (ops->unmap_phys) 217 ops->unmap_phys(dev, addr, size, dir, attrs); 218 trace_dma_unmap_phys(dev, addr, size, dir, attrs); 219 debug_dma_unmap_phys(dev, addr, size, dir); 220 } 221 EXPORT_SYMBOL_GPL(dma_unmap_phys); 222 223 void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, 224 enum dma_data_direction dir, unsigned long attrs) 225 { 226 if (unlikely(attrs & DMA_ATTR_MMIO)) 227 return; 228 229 dma_unmap_phys(dev, addr, size, dir, attrs); 230 } 231 EXPORT_SYMBOL(dma_unmap_page_attrs); 232 233 static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, 234 int nents, enum dma_data_direction dir, unsigned long attrs) 235 { 236 const struct dma_map_ops *ops = get_dma_ops(dev); 237 int ents; 238 239 BUG_ON(!valid_dma_direction(dir)); 240 241 if (!dev_is_dma_coherent(dev) && (attrs & DMA_ATTR_REQUIRE_COHERENT)) 242 return -EOPNOTSUPP; 243 244 if (WARN_ON_ONCE(!dev->dma_mask)) 245 return 0; 246 247 if (dma_map_direct(dev, ops) || 248 arch_dma_map_sg_direct(dev, sg, nents)) 249 ents = dma_direct_map_sg(dev, sg, nents, dir, attrs); 250 else if (use_dma_iommu(dev)) 251 ents = iommu_dma_map_sg(dev, sg, nents, dir, attrs); 252 else 253 ents = ops->map_sg(dev, sg, nents, dir, attrs); 254 255 if (ents > 0) { 256 kmsan_handle_dma_sg(sg, nents, dir); 257 trace_dma_map_sg(dev, sg, nents, ents, dir, attrs); 258 debug_dma_map_sg(dev, sg, nents, ents, dir, attrs); 259 } else if (WARN_ON_ONCE(ents != -EINVAL && ents != -ENOMEM && 260 ents != -EIO && ents != -EREMOTEIO)) { 261 trace_dma_map_sg_err(dev, sg, nents, ents, dir, attrs); 262 return -EIO; 263 } 264 265 return ents; 266 } 267 268 /** 269 * dma_map_sg_attrs - Map the given buffer for DMA 270 * @dev: The device for which to perform the DMA operation 271 * @sg: The sg_table object describing the buffer 272 * @nents: Number of entries to map 273 * @dir: DMA direction 274 * @attrs: Optional DMA attributes for the map operation 275 * 276 * Maps a buffer described by a scatterlist passed in the sg argument with 277 * nents segments for the @dir DMA operation by the @dev device. 278 * 279 * Returns the number of mapped entries (which can be less than nents) 280 * on success. Zero is returned for any error. 281 * 282 * dma_unmap_sg_attrs() should be used to unmap the buffer with the 283 * original sg and original nents (not the value returned by this funciton). 284 */ 285 unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, 286 int nents, enum dma_data_direction dir, unsigned long attrs) 287 { 288 int ret; 289 290 ret = __dma_map_sg_attrs(dev, sg, nents, dir, attrs); 291 if (ret < 0) 292 return 0; 293 return ret; 294 } 295 EXPORT_SYMBOL(dma_map_sg_attrs); 296 297 /** 298 * dma_map_sgtable - Map the given buffer for DMA 299 * @dev: The device for which to perform the DMA operation 300 * @sgt: The sg_table object describing the buffer 301 * @dir: DMA direction 302 * @attrs: Optional DMA attributes for the map operation 303 * 304 * Maps a buffer described by a scatterlist stored in the given sg_table 305 * object for the @dir DMA operation by the @dev device. After success, the 306 * ownership for the buffer is transferred to the DMA domain. One has to 307 * call dma_sync_sgtable_for_cpu() or dma_unmap_sgtable() to move the 308 * ownership of the buffer back to the CPU domain before touching the 309 * buffer by the CPU. 310 * 311 * Returns 0 on success or a negative error code on error. The following 312 * error codes are supported with the given meaning: 313 * 314 * -EINVAL An invalid argument, unaligned access or other error 315 * in usage. Will not succeed if retried. 316 * -ENOMEM Insufficient resources (like memory or IOVA space) to 317 * complete the mapping. Should succeed if retried later. 318 * -EIO Legacy error code with an unknown meaning. eg. this is 319 * returned if a lower level call returned 320 * DMA_MAPPING_ERROR. 321 * -EREMOTEIO The DMA device cannot access P2PDMA memory specified 322 * in the sg_table. This will not succeed if retried. 323 */ 324 int dma_map_sgtable(struct device *dev, struct sg_table *sgt, 325 enum dma_data_direction dir, unsigned long attrs) 326 { 327 int nents; 328 329 nents = __dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); 330 if (nents < 0) 331 return nents; 332 sgt->nents = nents; 333 return 0; 334 } 335 EXPORT_SYMBOL_GPL(dma_map_sgtable); 336 337 void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, 338 int nents, enum dma_data_direction dir, 339 unsigned long attrs) 340 { 341 const struct dma_map_ops *ops = get_dma_ops(dev); 342 343 BUG_ON(!valid_dma_direction(dir)); 344 trace_dma_unmap_sg(dev, sg, nents, dir, attrs); 345 debug_dma_unmap_sg(dev, sg, nents, dir); 346 if (dma_map_direct(dev, ops) || 347 arch_dma_unmap_sg_direct(dev, sg, nents)) 348 dma_direct_unmap_sg(dev, sg, nents, dir, attrs); 349 else if (use_dma_iommu(dev)) 350 iommu_dma_unmap_sg(dev, sg, nents, dir, attrs); 351 else if (ops->unmap_sg) 352 ops->unmap_sg(dev, sg, nents, dir, attrs); 353 } 354 EXPORT_SYMBOL(dma_unmap_sg_attrs); 355 356 dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr, 357 size_t size, enum dma_data_direction dir, unsigned long attrs) 358 { 359 if (IS_ENABLED(CONFIG_DMA_API_DEBUG) && 360 WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr)))) 361 return DMA_MAPPING_ERROR; 362 363 return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO); 364 } 365 EXPORT_SYMBOL(dma_map_resource); 366 367 void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size, 368 enum dma_data_direction dir, unsigned long attrs) 369 { 370 dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO); 371 } 372 EXPORT_SYMBOL(dma_unmap_resource); 373 374 #ifdef CONFIG_DMA_NEED_SYNC 375 void __dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, size_t size, 376 enum dma_data_direction dir) 377 { 378 const struct dma_map_ops *ops = get_dma_ops(dev); 379 380 BUG_ON(!valid_dma_direction(dir)); 381 if (dma_map_direct(dev, ops)) 382 dma_direct_sync_single_for_cpu(dev, addr, size, dir); 383 else if (use_dma_iommu(dev)) 384 iommu_dma_sync_single_for_cpu(dev, addr, size, dir); 385 else if (ops->sync_single_for_cpu) 386 ops->sync_single_for_cpu(dev, addr, size, dir); 387 trace_dma_sync_single_for_cpu(dev, addr, size, dir); 388 debug_dma_sync_single_for_cpu(dev, addr, size, dir); 389 } 390 EXPORT_SYMBOL(__dma_sync_single_for_cpu); 391 392 void __dma_sync_single_for_device(struct device *dev, dma_addr_t addr, 393 size_t size, enum dma_data_direction dir) 394 { 395 const struct dma_map_ops *ops = get_dma_ops(dev); 396 397 BUG_ON(!valid_dma_direction(dir)); 398 if (dma_map_direct(dev, ops)) 399 dma_direct_sync_single_for_device(dev, addr, size, dir); 400 else if (use_dma_iommu(dev)) 401 iommu_dma_sync_single_for_device(dev, addr, size, dir); 402 else if (ops->sync_single_for_device) 403 ops->sync_single_for_device(dev, addr, size, dir); 404 trace_dma_sync_single_for_device(dev, addr, size, dir); 405 debug_dma_sync_single_for_device(dev, addr, size, dir); 406 } 407 EXPORT_SYMBOL(__dma_sync_single_for_device); 408 409 void __dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, 410 int nelems, enum dma_data_direction dir) 411 { 412 const struct dma_map_ops *ops = get_dma_ops(dev); 413 414 BUG_ON(!valid_dma_direction(dir)); 415 if (dma_map_direct(dev, ops)) 416 dma_direct_sync_sg_for_cpu(dev, sg, nelems, dir); 417 else if (use_dma_iommu(dev)) 418 iommu_dma_sync_sg_for_cpu(dev, sg, nelems, dir); 419 else if (ops->sync_sg_for_cpu) 420 ops->sync_sg_for_cpu(dev, sg, nelems, dir); 421 trace_dma_sync_sg_for_cpu(dev, sg, nelems, dir); 422 debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); 423 } 424 EXPORT_SYMBOL(__dma_sync_sg_for_cpu); 425 426 void __dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, 427 int nelems, enum dma_data_direction dir) 428 { 429 const struct dma_map_ops *ops = get_dma_ops(dev); 430 431 BUG_ON(!valid_dma_direction(dir)); 432 if (dma_map_direct(dev, ops)) 433 dma_direct_sync_sg_for_device(dev, sg, nelems, dir); 434 else if (use_dma_iommu(dev)) 435 iommu_dma_sync_sg_for_device(dev, sg, nelems, dir); 436 else if (ops->sync_sg_for_device) 437 ops->sync_sg_for_device(dev, sg, nelems, dir); 438 trace_dma_sync_sg_for_device(dev, sg, nelems, dir); 439 debug_dma_sync_sg_for_device(dev, sg, nelems, dir); 440 } 441 EXPORT_SYMBOL(__dma_sync_sg_for_device); 442 443 bool __dma_need_sync(struct device *dev, dma_addr_t dma_addr) 444 { 445 const struct dma_map_ops *ops = get_dma_ops(dev); 446 447 if (dma_map_direct(dev, ops)) 448 /* 449 * dma_skip_sync could've been reset on first SWIOTLB buffer 450 * mapping, but @dma_addr is not necessary an SWIOTLB buffer. 451 * In this case, fall back to more granular check. 452 */ 453 return dma_direct_need_sync(dev, dma_addr); 454 return true; 455 } 456 EXPORT_SYMBOL_GPL(__dma_need_sync); 457 458 /** 459 * dma_need_unmap - does this device need dma_unmap_* operations 460 * @dev: device to check 461 * 462 * If this function returns %false, drivers can skip calling dma_unmap_* after 463 * finishing an I/O. This function must be called after all mappings that might 464 * need to be unmapped have been performed. 465 */ 466 bool dma_need_unmap(struct device *dev) 467 { 468 if (!dma_map_direct(dev, get_dma_ops(dev))) 469 return true; 470 if (!dev->dma_skip_sync) 471 return true; 472 return IS_ENABLED(CONFIG_DMA_API_DEBUG); 473 } 474 EXPORT_SYMBOL_GPL(dma_need_unmap); 475 476 static void dma_setup_need_sync(struct device *dev) 477 { 478 const struct dma_map_ops *ops = get_dma_ops(dev); 479 480 if (dma_map_direct(dev, ops) || use_dma_iommu(dev)) 481 /* 482 * dma_skip_sync will be reset to %false on first SWIOTLB buffer 483 * mapping, if any. During the device initialization, it's 484 * enough to check only for the DMA coherence. 485 */ 486 dev->dma_skip_sync = dev_is_dma_coherent(dev); 487 else if (!ops->sync_single_for_device && !ops->sync_single_for_cpu && 488 !ops->sync_sg_for_device && !ops->sync_sg_for_cpu) 489 /* 490 * Synchronization is not possible when none of DMA sync ops 491 * is set. 492 */ 493 dev->dma_skip_sync = true; 494 else 495 dev->dma_skip_sync = false; 496 } 497 #else /* !CONFIG_DMA_NEED_SYNC */ 498 static inline void dma_setup_need_sync(struct device *dev) { } 499 #endif /* !CONFIG_DMA_NEED_SYNC */ 500 501 /* 502 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems 503 * that the intention is to allow exporting memory allocated via the 504 * coherent DMA APIs through the dma_buf API, which only accepts a 505 * scattertable. This presents a couple of problems: 506 * 1. Not all memory allocated via the coherent DMA APIs is backed by 507 * a struct page 508 * 2. Passing coherent DMA memory into the streaming APIs is not allowed 509 * as we will try to flush the memory through a different alias to that 510 * actually being used (and the flushes are redundant.) 511 */ 512 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, 513 void *cpu_addr, dma_addr_t dma_addr, size_t size, 514 unsigned long attrs) 515 { 516 const struct dma_map_ops *ops = get_dma_ops(dev); 517 518 if (dma_alloc_direct(dev, ops)) 519 return dma_direct_get_sgtable(dev, sgt, cpu_addr, dma_addr, 520 size, attrs); 521 if (use_dma_iommu(dev)) 522 return iommu_dma_get_sgtable(dev, sgt, cpu_addr, dma_addr, 523 size, attrs); 524 if (!ops->get_sgtable) 525 return -ENXIO; 526 return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs); 527 } 528 EXPORT_SYMBOL(dma_get_sgtable_attrs); 529 530 #ifdef CONFIG_MMU 531 /* 532 * Return the page attributes used for mapping dma_alloc_* memory, either in 533 * kernel space if remapping is needed, or to userspace through dma_mmap_*. 534 */ 535 pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs) 536 { 537 if (dev_is_dma_coherent(dev)) 538 return prot; 539 #ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE 540 if (attrs & DMA_ATTR_WRITE_COMBINE) 541 return pgprot_writecombine(prot); 542 #endif 543 return pgprot_dmacoherent(prot); 544 } 545 #endif /* CONFIG_MMU */ 546 547 /** 548 * dma_can_mmap - check if a given device supports dma_mmap_* 549 * @dev: device to check 550 * 551 * Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to 552 * map DMA allocations to userspace. 553 */ 554 bool dma_can_mmap(struct device *dev) 555 { 556 const struct dma_map_ops *ops = get_dma_ops(dev); 557 558 if (dma_alloc_direct(dev, ops)) 559 return dma_direct_can_mmap(dev); 560 if (use_dma_iommu(dev)) 561 return true; 562 return ops->mmap != NULL; 563 } 564 EXPORT_SYMBOL_GPL(dma_can_mmap); 565 566 /** 567 * dma_mmap_attrs - map a coherent DMA allocation into user space 568 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices 569 * @vma: vm_area_struct describing requested user mapping 570 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs 571 * @dma_addr: device-view address returned from dma_alloc_attrs 572 * @size: size of memory originally requested in dma_alloc_attrs 573 * @attrs: attributes of mapping properties requested in dma_alloc_attrs 574 * 575 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user 576 * space. The coherent DMA buffer must not be freed by the driver until the 577 * user space mapping has been released. 578 */ 579 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, 580 void *cpu_addr, dma_addr_t dma_addr, size_t size, 581 unsigned long attrs) 582 { 583 const struct dma_map_ops *ops = get_dma_ops(dev); 584 585 if (dma_alloc_direct(dev, ops)) 586 return dma_direct_mmap(dev, vma, cpu_addr, dma_addr, size, 587 attrs); 588 if (use_dma_iommu(dev)) 589 return iommu_dma_mmap(dev, vma, cpu_addr, dma_addr, size, 590 attrs); 591 if (!ops->mmap) 592 return -ENXIO; 593 return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); 594 } 595 EXPORT_SYMBOL(dma_mmap_attrs); 596 597 u64 dma_get_required_mask(struct device *dev) 598 { 599 const struct dma_map_ops *ops = get_dma_ops(dev); 600 601 if (dma_alloc_direct(dev, ops)) 602 return dma_direct_get_required_mask(dev); 603 604 if (use_dma_iommu(dev)) 605 return DMA_BIT_MASK(32); 606 607 if (ops->get_required_mask) 608 return ops->get_required_mask(dev); 609 610 /* 611 * We require every DMA ops implementation to at least support a 32-bit 612 * DMA mask (and use bounce buffering if that isn't supported in 613 * hardware). As the direct mapping code has its own routine to 614 * actually report an optimal mask we default to 32-bit here as that 615 * is the right thing for most IOMMUs, and at least not actively 616 * harmful in general. 617 */ 618 return DMA_BIT_MASK(32); 619 } 620 EXPORT_SYMBOL_GPL(dma_get_required_mask); 621 622 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 623 gfp_t flag, unsigned long attrs) 624 { 625 const struct dma_map_ops *ops = get_dma_ops(dev); 626 void *cpu_addr; 627 628 WARN_ON_ONCE(!dev->coherent_dma_mask); 629 630 /* 631 * DMA allocations can never be turned back into a page pointer, so 632 * requesting compound pages doesn't make sense (and can't even be 633 * supported at all by various backends). 634 */ 635 if (WARN_ON_ONCE(flag & __GFP_COMP)) 636 return NULL; 637 638 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) { 639 trace_dma_alloc(dev, cpu_addr, *dma_handle, size, 640 DMA_BIDIRECTIONAL, flag, attrs); 641 return cpu_addr; 642 } 643 644 /* let the implementation decide on the zone to allocate from: */ 645 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); 646 647 if (dma_alloc_direct(dev, ops) || arch_dma_alloc_direct(dev)) { 648 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs); 649 } else if (use_dma_iommu(dev)) { 650 cpu_addr = iommu_dma_alloc(dev, size, dma_handle, flag, attrs); 651 } else if (ops->alloc) { 652 cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); 653 } else { 654 trace_dma_alloc(dev, NULL, 0, size, DMA_BIDIRECTIONAL, flag, 655 attrs); 656 return NULL; 657 } 658 659 trace_dma_alloc(dev, cpu_addr, *dma_handle, size, DMA_BIDIRECTIONAL, 660 flag, attrs); 661 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr, attrs); 662 return cpu_addr; 663 } 664 EXPORT_SYMBOL(dma_alloc_attrs); 665 666 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, 667 dma_addr_t dma_handle, unsigned long attrs) 668 { 669 const struct dma_map_ops *ops = get_dma_ops(dev); 670 671 if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr)) 672 return; 673 /* 674 * On non-coherent platforms which implement DMA-coherent buffers via 675 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting 676 * this far in IRQ context is a) at risk of a BUG_ON() or trying to 677 * sleep on some machines, and b) an indication that the driver is 678 * probably misusing the coherent API anyway. 679 */ 680 WARN_ON(irqs_disabled()); 681 682 trace_dma_free(dev, cpu_addr, dma_handle, size, DMA_BIDIRECTIONAL, 683 attrs); 684 if (!cpu_addr) 685 return; 686 687 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); 688 if (dma_alloc_direct(dev, ops) || arch_dma_free_direct(dev, dma_handle)) 689 dma_direct_free(dev, size, cpu_addr, dma_handle, attrs); 690 else if (use_dma_iommu(dev)) 691 iommu_dma_free(dev, size, cpu_addr, dma_handle, attrs); 692 else if (ops->free) 693 ops->free(dev, size, cpu_addr, dma_handle, attrs); 694 } 695 EXPORT_SYMBOL(dma_free_attrs); 696 697 static struct page *__dma_alloc_pages(struct device *dev, size_t size, 698 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp) 699 { 700 const struct dma_map_ops *ops = get_dma_ops(dev); 701 702 if (WARN_ON_ONCE(!dev->coherent_dma_mask)) 703 return NULL; 704 if (WARN_ON_ONCE(gfp & (__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM))) 705 return NULL; 706 if (WARN_ON_ONCE(gfp & __GFP_COMP)) 707 return NULL; 708 709 size = PAGE_ALIGN(size); 710 if (dma_alloc_direct(dev, ops)) 711 return dma_direct_alloc_pages(dev, size, dma_handle, dir, gfp); 712 if (use_dma_iommu(dev)) 713 return dma_common_alloc_pages(dev, size, dma_handle, dir, gfp); 714 if (!ops->alloc_pages_op) 715 return NULL; 716 return ops->alloc_pages_op(dev, size, dma_handle, dir, gfp); 717 } 718 719 struct page *dma_alloc_pages(struct device *dev, size_t size, 720 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp) 721 { 722 struct page *page = __dma_alloc_pages(dev, size, dma_handle, dir, gfp); 723 724 if (page) { 725 trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle, 726 size, dir, gfp, 0); 727 debug_dma_alloc_pages(dev, page, size, dir, *dma_handle, 0); 728 } else { 729 trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0); 730 } 731 return page; 732 } 733 EXPORT_SYMBOL_GPL(dma_alloc_pages); 734 735 static void __dma_free_pages(struct device *dev, size_t size, struct page *page, 736 dma_addr_t dma_handle, enum dma_data_direction dir) 737 { 738 const struct dma_map_ops *ops = get_dma_ops(dev); 739 740 size = PAGE_ALIGN(size); 741 if (dma_alloc_direct(dev, ops)) 742 dma_direct_free_pages(dev, size, page, dma_handle, dir); 743 else if (use_dma_iommu(dev)) 744 dma_common_free_pages(dev, size, page, dma_handle, dir); 745 else if (ops->free_pages) 746 ops->free_pages(dev, size, page, dma_handle, dir); 747 } 748 749 void dma_free_pages(struct device *dev, size_t size, struct page *page, 750 dma_addr_t dma_handle, enum dma_data_direction dir) 751 { 752 trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0); 753 debug_dma_free_pages(dev, page, size, dir, dma_handle); 754 __dma_free_pages(dev, size, page, dma_handle, dir); 755 } 756 EXPORT_SYMBOL_GPL(dma_free_pages); 757 758 int dma_mmap_pages(struct device *dev, struct vm_area_struct *vma, 759 size_t size, struct page *page) 760 { 761 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 762 763 if (vma->vm_pgoff >= count || vma_pages(vma) > count - vma->vm_pgoff) 764 return -ENXIO; 765 return remap_pfn_range(vma, vma->vm_start, 766 page_to_pfn(page) + vma->vm_pgoff, 767 vma_pages(vma) << PAGE_SHIFT, vma->vm_page_prot); 768 } 769 EXPORT_SYMBOL_GPL(dma_mmap_pages); 770 771 static struct sg_table *alloc_single_sgt(struct device *dev, size_t size, 772 enum dma_data_direction dir, gfp_t gfp) 773 { 774 struct sg_table *sgt; 775 struct page *page; 776 777 sgt = kmalloc_obj(*sgt, gfp); 778 if (!sgt) 779 return NULL; 780 if (sg_alloc_table(sgt, 1, gfp)) 781 goto out_free_sgt; 782 page = __dma_alloc_pages(dev, size, &sgt->sgl->dma_address, dir, gfp); 783 if (!page) 784 goto out_free_table; 785 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 786 sg_dma_len(sgt->sgl) = sgt->sgl->length; 787 return sgt; 788 out_free_table: 789 sg_free_table(sgt); 790 out_free_sgt: 791 kfree(sgt); 792 return NULL; 793 } 794 795 struct sg_table *dma_alloc_noncontiguous(struct device *dev, size_t size, 796 enum dma_data_direction dir, gfp_t gfp, unsigned long attrs) 797 { 798 struct sg_table *sgt; 799 800 if (WARN_ON_ONCE(attrs & ~DMA_ATTR_ALLOC_SINGLE_PAGES)) 801 return NULL; 802 if (WARN_ON_ONCE(gfp & __GFP_COMP)) 803 return NULL; 804 805 if (use_dma_iommu(dev)) 806 sgt = iommu_dma_alloc_noncontiguous(dev, size, dir, gfp, attrs); 807 else 808 sgt = alloc_single_sgt(dev, size, dir, gfp); 809 810 if (sgt) { 811 sgt->nents = 1; 812 trace_dma_alloc_sgt(dev, sgt, size, dir, gfp, attrs); 813 debug_dma_map_sg(dev, sgt->sgl, sgt->orig_nents, 1, dir, attrs); 814 } else { 815 trace_dma_alloc_sgt_err(dev, NULL, 0, size, dir, gfp, attrs); 816 } 817 return sgt; 818 } 819 EXPORT_SYMBOL_GPL(dma_alloc_noncontiguous); 820 821 static void free_single_sgt(struct device *dev, size_t size, 822 struct sg_table *sgt, enum dma_data_direction dir) 823 { 824 __dma_free_pages(dev, size, sg_page(sgt->sgl), sgt->sgl->dma_address, 825 dir); 826 sg_free_table(sgt); 827 kfree(sgt); 828 } 829 830 void dma_free_noncontiguous(struct device *dev, size_t size, 831 struct sg_table *sgt, enum dma_data_direction dir) 832 { 833 trace_dma_free_sgt(dev, sgt, size, dir); 834 debug_dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir); 835 836 if (use_dma_iommu(dev)) 837 iommu_dma_free_noncontiguous(dev, size, sgt, dir); 838 else 839 free_single_sgt(dev, size, sgt, dir); 840 } 841 EXPORT_SYMBOL_GPL(dma_free_noncontiguous); 842 843 void *dma_vmap_noncontiguous(struct device *dev, size_t size, 844 struct sg_table *sgt) 845 { 846 847 if (use_dma_iommu(dev)) 848 return iommu_dma_vmap_noncontiguous(dev, size, sgt); 849 850 return page_address(sg_page(sgt->sgl)); 851 } 852 EXPORT_SYMBOL_GPL(dma_vmap_noncontiguous); 853 854 void dma_vunmap_noncontiguous(struct device *dev, void *vaddr) 855 { 856 if (use_dma_iommu(dev)) 857 iommu_dma_vunmap_noncontiguous(dev, vaddr); 858 } 859 EXPORT_SYMBOL_GPL(dma_vunmap_noncontiguous); 860 861 int dma_mmap_noncontiguous(struct device *dev, struct vm_area_struct *vma, 862 size_t size, struct sg_table *sgt) 863 { 864 if (use_dma_iommu(dev)) 865 return iommu_dma_mmap_noncontiguous(dev, vma, size, sgt); 866 return dma_mmap_pages(dev, vma, size, sg_page(sgt->sgl)); 867 } 868 EXPORT_SYMBOL_GPL(dma_mmap_noncontiguous); 869 870 static int dma_supported(struct device *dev, u64 mask) 871 { 872 const struct dma_map_ops *ops = get_dma_ops(dev); 873 874 if (use_dma_iommu(dev)) { 875 if (WARN_ON(ops)) 876 return false; 877 return true; 878 } 879 880 /* 881 * ->dma_supported sets and clears the bypass flag, so ignore it here 882 * and always call into the method if there is one. 883 */ 884 if (ops) { 885 if (!ops->dma_supported) 886 return true; 887 return ops->dma_supported(dev, mask); 888 } 889 890 return dma_direct_supported(dev, mask); 891 } 892 893 bool dma_pci_p2pdma_supported(struct device *dev) 894 { 895 const struct dma_map_ops *ops = get_dma_ops(dev); 896 897 /* 898 * Note: dma_ops_bypass is not checked here because P2PDMA should 899 * not be used with dma mapping ops that do not have support even 900 * if the specific device is bypassing them. 901 */ 902 903 /* if ops is not set, dma direct and default IOMMU support P2PDMA */ 904 return !ops; 905 } 906 EXPORT_SYMBOL_GPL(dma_pci_p2pdma_supported); 907 908 int dma_set_mask(struct device *dev, u64 mask) 909 { 910 /* 911 * Truncate the mask to the actually supported dma_addr_t width to 912 * avoid generating unsupportable addresses. 913 */ 914 mask = (dma_addr_t)mask; 915 916 if (!dev->dma_mask || !dma_supported(dev, mask)) 917 return -EIO; 918 919 arch_dma_set_mask(dev, mask); 920 *dev->dma_mask = mask; 921 dma_setup_need_sync(dev); 922 923 return 0; 924 } 925 EXPORT_SYMBOL(dma_set_mask); 926 927 int dma_set_coherent_mask(struct device *dev, u64 mask) 928 { 929 /* 930 * Truncate the mask to the actually supported dma_addr_t width to 931 * avoid generating unsupportable addresses. 932 */ 933 mask = (dma_addr_t)mask; 934 935 if (!dma_supported(dev, mask)) 936 return -EIO; 937 938 dev->coherent_dma_mask = mask; 939 return 0; 940 } 941 EXPORT_SYMBOL(dma_set_coherent_mask); 942 943 static bool __dma_addressing_limited(struct device *dev) 944 { 945 const struct dma_map_ops *ops = get_dma_ops(dev); 946 947 if (min_not_zero(dma_get_mask(dev), dev->bus_dma_limit) < 948 dma_get_required_mask(dev)) 949 return true; 950 951 if (unlikely(ops) || use_dma_iommu(dev)) 952 return false; 953 return !dma_direct_all_ram_mapped(dev); 954 } 955 956 /** 957 * dma_addressing_limited - return if the device is addressing limited 958 * @dev: device to check 959 * 960 * Return %true if the devices DMA mask is too small to address all memory in 961 * the system, else %false. Lack of addressing bits is the prime reason for 962 * bounce buffering, but might not be the only one. 963 */ 964 bool dma_addressing_limited(struct device *dev) 965 { 966 if (!__dma_addressing_limited(dev)) 967 return false; 968 969 dev_dbg(dev, "device is DMA addressing limited\n"); 970 return true; 971 } 972 EXPORT_SYMBOL_GPL(dma_addressing_limited); 973 974 size_t dma_max_mapping_size(struct device *dev) 975 { 976 const struct dma_map_ops *ops = get_dma_ops(dev); 977 size_t size = SIZE_MAX; 978 979 if (dma_map_direct(dev, ops)) 980 size = dma_direct_max_mapping_size(dev); 981 else if (use_dma_iommu(dev)) 982 size = iommu_dma_max_mapping_size(dev); 983 else if (ops && ops->max_mapping_size) 984 size = ops->max_mapping_size(dev); 985 986 return size; 987 } 988 EXPORT_SYMBOL_GPL(dma_max_mapping_size); 989 990 size_t dma_opt_mapping_size(struct device *dev) 991 { 992 const struct dma_map_ops *ops = get_dma_ops(dev); 993 size_t size = SIZE_MAX; 994 995 if (use_dma_iommu(dev)) 996 size = iommu_dma_opt_mapping_size(); 997 else if (ops && ops->opt_mapping_size) 998 size = ops->opt_mapping_size(); 999 1000 return min(dma_max_mapping_size(dev), size); 1001 } 1002 EXPORT_SYMBOL_GPL(dma_opt_mapping_size); 1003 1004 unsigned long dma_get_merge_boundary(struct device *dev) 1005 { 1006 const struct dma_map_ops *ops = get_dma_ops(dev); 1007 1008 if (use_dma_iommu(dev)) 1009 return iommu_dma_get_merge_boundary(dev); 1010 1011 if (!ops || !ops->get_merge_boundary) 1012 return 0; /* can't merge */ 1013 1014 return ops->get_merge_boundary(dev); 1015 } 1016 EXPORT_SYMBOL_GPL(dma_get_merge_boundary); 1017