1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Christoph Hellwig. 4 * 5 * DMA operations that map physical memory directly without using an IOMMU. 6 */ 7 #include <linux/memblock.h> /* for max_pfn */ 8 #include <linux/export.h> 9 #include <linux/mm.h> 10 #include <linux/dma-direct.h> 11 #include <linux/scatterlist.h> 12 #include <linux/dma-contiguous.h> 13 #include <linux/dma-noncoherent.h> 14 #include <linux/pfn.h> 15 #include <linux/set_memory.h> 16 #include <linux/swiotlb.h> 17 18 /* 19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but 20 * some use it for entirely different regions: 21 */ 22 #ifndef ARCH_ZONE_DMA_BITS 23 #define ARCH_ZONE_DMA_BITS 24 24 #endif 25 26 /* 27 * For AMD SEV all DMA must be to unencrypted addresses. 28 */ 29 static inline bool force_dma_unencrypted(void) 30 { 31 return sev_active(); 32 } 33 34 static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size) 35 { 36 if (!dev->dma_mask) { 37 dev_err_once(dev, "DMA map on device without dma_mask\n"); 38 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) { 39 dev_err_once(dev, 40 "overflow %pad+%zu of DMA mask %llx bus mask %llx\n", 41 &dma_addr, size, *dev->dma_mask, dev->bus_dma_mask); 42 } 43 WARN_ON_ONCE(1); 44 } 45 46 static inline dma_addr_t phys_to_dma_direct(struct device *dev, 47 phys_addr_t phys) 48 { 49 if (force_dma_unencrypted()) 50 return __phys_to_dma(dev, phys); 51 return phys_to_dma(dev, phys); 52 } 53 54 u64 dma_direct_get_required_mask(struct device *dev) 55 { 56 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT); 57 58 if (dev->bus_dma_mask && dev->bus_dma_mask < max_dma) 59 max_dma = dev->bus_dma_mask; 60 61 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1; 62 } 63 64 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask, 65 u64 *phys_mask) 66 { 67 if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask) 68 dma_mask = dev->bus_dma_mask; 69 70 if (force_dma_unencrypted()) 71 *phys_mask = __dma_to_phys(dev, dma_mask); 72 else 73 *phys_mask = dma_to_phys(dev, dma_mask); 74 75 /* 76 * Optimistically try the zone that the physical address mask falls 77 * into first. If that returns memory that isn't actually addressable 78 * we will fallback to the next lower zone and try again. 79 * 80 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding 81 * zones. 82 */ 83 if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS)) 84 return GFP_DMA; 85 if (*phys_mask <= DMA_BIT_MASK(32)) 86 return GFP_DMA32; 87 return 0; 88 } 89 90 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size) 91 { 92 return phys_to_dma_direct(dev, phys) + size - 1 <= 93 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask); 94 } 95 96 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size, 97 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 98 { 99 struct page *page = NULL; 100 u64 phys_mask; 101 102 if (attrs & DMA_ATTR_NO_WARN) 103 gfp |= __GFP_NOWARN; 104 105 /* we always manually zero the memory once we are done: */ 106 gfp &= ~__GFP_ZERO; 107 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask, 108 &phys_mask); 109 again: 110 page = dma_alloc_contiguous(dev, size, gfp); 111 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 112 dma_free_contiguous(dev, page, size); 113 page = NULL; 114 115 if (IS_ENABLED(CONFIG_ZONE_DMA32) && 116 phys_mask < DMA_BIT_MASK(64) && 117 !(gfp & (GFP_DMA32 | GFP_DMA))) { 118 gfp |= GFP_DMA32; 119 goto again; 120 } 121 122 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) { 123 gfp = (gfp & ~GFP_DMA32) | GFP_DMA; 124 goto again; 125 } 126 } 127 128 return page; 129 } 130 131 void *dma_direct_alloc_pages(struct device *dev, size_t size, 132 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 133 { 134 struct page *page; 135 void *ret; 136 137 page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs); 138 if (!page) 139 return NULL; 140 141 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) { 142 /* remove any dirty cache lines on the kernel alias */ 143 if (!PageHighMem(page)) 144 arch_dma_prep_coherent(page, size); 145 /* return the page pointer as the opaque cookie */ 146 return page; 147 } 148 149 if (PageHighMem(page)) { 150 /* 151 * Depending on the cma= arguments and per-arch setup 152 * dma_alloc_contiguous could return highmem pages. 153 * Without remapping there is no way to return them here, 154 * so log an error and fail. 155 */ 156 dev_info(dev, "Rejecting highmem page from CMA.\n"); 157 __dma_direct_free_pages(dev, size, page); 158 return NULL; 159 } 160 161 ret = page_address(page); 162 if (force_dma_unencrypted()) { 163 set_memory_decrypted((unsigned long)ret, 1 << get_order(size)); 164 *dma_handle = __phys_to_dma(dev, page_to_phys(page)); 165 } else { 166 *dma_handle = phys_to_dma(dev, page_to_phys(page)); 167 } 168 memset(ret, 0, size); 169 170 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 171 dma_alloc_need_uncached(dev, attrs)) { 172 arch_dma_prep_coherent(page, size); 173 ret = uncached_kernel_address(ret); 174 } 175 176 return ret; 177 } 178 179 void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page) 180 { 181 dma_free_contiguous(dev, page, size); 182 } 183 184 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr, 185 dma_addr_t dma_addr, unsigned long attrs) 186 { 187 unsigned int page_order = get_order(size); 188 189 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) { 190 /* cpu_addr is a struct page cookie, not a kernel address */ 191 __dma_direct_free_pages(dev, size, cpu_addr); 192 return; 193 } 194 195 if (force_dma_unencrypted()) 196 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order); 197 198 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 199 dma_alloc_need_uncached(dev, attrs)) 200 cpu_addr = cached_kernel_address(cpu_addr); 201 __dma_direct_free_pages(dev, size, virt_to_page(cpu_addr)); 202 } 203 204 void *dma_direct_alloc(struct device *dev, size_t size, 205 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 206 { 207 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 208 dma_alloc_need_uncached(dev, attrs)) 209 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs); 210 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs); 211 } 212 213 void dma_direct_free(struct device *dev, size_t size, 214 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs) 215 { 216 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) && 217 dma_alloc_need_uncached(dev, attrs)) 218 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs); 219 else 220 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); 221 } 222 223 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ 224 defined(CONFIG_SWIOTLB) 225 void dma_direct_sync_single_for_device(struct device *dev, 226 dma_addr_t addr, size_t size, enum dma_data_direction dir) 227 { 228 phys_addr_t paddr = dma_to_phys(dev, addr); 229 230 if (unlikely(is_swiotlb_buffer(paddr))) 231 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE); 232 233 if (!dev_is_dma_coherent(dev)) 234 arch_sync_dma_for_device(dev, paddr, size, dir); 235 } 236 EXPORT_SYMBOL(dma_direct_sync_single_for_device); 237 238 void dma_direct_sync_sg_for_device(struct device *dev, 239 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 240 { 241 struct scatterlist *sg; 242 int i; 243 244 for_each_sg(sgl, sg, nents, i) { 245 if (unlikely(is_swiotlb_buffer(sg_phys(sg)))) 246 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length, 247 dir, SYNC_FOR_DEVICE); 248 249 if (!dev_is_dma_coherent(dev)) 250 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, 251 dir); 252 } 253 } 254 EXPORT_SYMBOL(dma_direct_sync_sg_for_device); 255 #endif 256 257 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ 258 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \ 259 defined(CONFIG_SWIOTLB) 260 void dma_direct_sync_single_for_cpu(struct device *dev, 261 dma_addr_t addr, size_t size, enum dma_data_direction dir) 262 { 263 phys_addr_t paddr = dma_to_phys(dev, addr); 264 265 if (!dev_is_dma_coherent(dev)) { 266 arch_sync_dma_for_cpu(dev, paddr, size, dir); 267 arch_sync_dma_for_cpu_all(dev); 268 } 269 270 if (unlikely(is_swiotlb_buffer(paddr))) 271 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU); 272 } 273 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu); 274 275 void dma_direct_sync_sg_for_cpu(struct device *dev, 276 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 277 { 278 struct scatterlist *sg; 279 int i; 280 281 for_each_sg(sgl, sg, nents, i) { 282 if (!dev_is_dma_coherent(dev)) 283 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir); 284 285 if (unlikely(is_swiotlb_buffer(sg_phys(sg)))) 286 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length, dir, 287 SYNC_FOR_CPU); 288 } 289 290 if (!dev_is_dma_coherent(dev)) 291 arch_sync_dma_for_cpu_all(dev); 292 } 293 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu); 294 295 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr, 296 size_t size, enum dma_data_direction dir, unsigned long attrs) 297 { 298 phys_addr_t phys = dma_to_phys(dev, addr); 299 300 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 301 dma_direct_sync_single_for_cpu(dev, addr, size, dir); 302 303 if (unlikely(is_swiotlb_buffer(phys))) 304 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs); 305 } 306 EXPORT_SYMBOL(dma_direct_unmap_page); 307 308 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl, 309 int nents, enum dma_data_direction dir, unsigned long attrs) 310 { 311 struct scatterlist *sg; 312 int i; 313 314 for_each_sg(sgl, sg, nents, i) 315 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir, 316 attrs); 317 } 318 EXPORT_SYMBOL(dma_direct_unmap_sg); 319 #endif 320 321 static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr, 322 size_t size) 323 { 324 return swiotlb_force != SWIOTLB_FORCE && 325 dma_capable(dev, dma_addr, size); 326 } 327 328 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page, 329 unsigned long offset, size_t size, enum dma_data_direction dir, 330 unsigned long attrs) 331 { 332 phys_addr_t phys = page_to_phys(page) + offset; 333 dma_addr_t dma_addr = phys_to_dma(dev, phys); 334 335 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) && 336 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) { 337 report_addr(dev, dma_addr, size); 338 return DMA_MAPPING_ERROR; 339 } 340 341 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 342 arch_sync_dma_for_device(dev, phys, size, dir); 343 return dma_addr; 344 } 345 EXPORT_SYMBOL(dma_direct_map_page); 346 347 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, 348 enum dma_data_direction dir, unsigned long attrs) 349 { 350 int i; 351 struct scatterlist *sg; 352 353 for_each_sg(sgl, sg, nents, i) { 354 sg->dma_address = dma_direct_map_page(dev, sg_page(sg), 355 sg->offset, sg->length, dir, attrs); 356 if (sg->dma_address == DMA_MAPPING_ERROR) 357 goto out_unmap; 358 sg_dma_len(sg) = sg->length; 359 } 360 361 return nents; 362 363 out_unmap: 364 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC); 365 return 0; 366 } 367 EXPORT_SYMBOL(dma_direct_map_sg); 368 369 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, 370 size_t size, enum dma_data_direction dir, unsigned long attrs) 371 { 372 dma_addr_t dma_addr = paddr; 373 374 if (unlikely(!dma_direct_possible(dev, dma_addr, size))) { 375 report_addr(dev, dma_addr, size); 376 return DMA_MAPPING_ERROR; 377 } 378 379 return dma_addr; 380 } 381 EXPORT_SYMBOL(dma_direct_map_resource); 382 383 /* 384 * Because 32-bit DMA masks are so common we expect every architecture to be 385 * able to satisfy them - either by not supporting more physical memory, or by 386 * providing a ZONE_DMA32. If neither is the case, the architecture needs to 387 * use an IOMMU instead of the direct mapping. 388 */ 389 int dma_direct_supported(struct device *dev, u64 mask) 390 { 391 u64 min_mask; 392 393 if (IS_ENABLED(CONFIG_ZONE_DMA)) 394 min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS); 395 else 396 min_mask = DMA_BIT_MASK(32); 397 398 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT); 399 400 /* 401 * This check needs to be against the actual bit mask value, so 402 * use __phys_to_dma() here so that the SME encryption mask isn't 403 * part of the check. 404 */ 405 return mask >= __phys_to_dma(dev, min_mask); 406 } 407 408 size_t dma_direct_max_mapping_size(struct device *dev) 409 { 410 size_t size = SIZE_MAX; 411 412 /* If SWIOTLB is active, use its maximum mapping size */ 413 if (is_swiotlb_active()) 414 size = swiotlb_max_mapping_size(dev); 415 416 return size; 417 } 418