1 /* 2 * linux/include/video/vga.h -- standard VGA chipset interaction 3 * 4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> 5 * 6 * Copyright history from vga16fb.c: 7 * Copyright 1999 Ben Pfaff and Petr Vandrovec 8 * Based on VGA info at http://www.osdever.net/FreeVGA/home.htm 9 * Based on VESA framebuffer (c) 1998 Gerd Knorr 10 * 11 * This file is subject to the terms and conditions of the GNU General 12 * Public License. See the file COPYING in the main directory of this 13 * archive for more details. 14 * 15 */ 16 17 #ifndef __linux_video_vga_h__ 18 #define __linux_video_vga_h__ 19 20 #include <linux/types.h> 21 #include <linux/io.h> 22 #include <asm/vga.h> 23 #include <asm/byteorder.h> 24 25 #define VGA_FB_PHYS_BASE 0xA0000 /* VGA framebuffer I/O base */ 26 #define VGA_FB_PHYS_SIZE 65536 /* VGA framebuffer I/O size */ 27 28 /* Some of the code below is taken from SVGAlib. The original, 29 unmodified copyright notice for that code is below. */ 30 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */ 31 /* */ 32 /* This library is free software; you can redistribute it and/or */ 33 /* modify it without any restrictions. This library is distributed */ 34 /* in the hope that it will be useful, but without any warranty. */ 35 36 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */ 37 /* partially copyrighted (C) 1993 by Hartmut Schirmer */ 38 39 /* VGA data register ports */ 40 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ 41 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ 42 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */ 43 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */ 44 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */ 45 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */ 46 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */ 47 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */ 48 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */ 49 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ 50 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ 51 #define VGA_PEL_D 0x3C9 /* PEL Data Register */ 52 #define VGA_PEL_MSK 0x3C6 /* PEL mask register */ 53 54 /* EGA-specific registers */ 55 #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */ 56 #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */ 57 58 /* VGA index register ports */ 59 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ 60 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ 61 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ 62 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */ 63 #define VGA_SEQ_I 0x3C4 /* Sequencer Index */ 64 #define VGA_PEL_IW 0x3C8 /* PEL Write Index */ 65 #define VGA_PEL_IR 0x3C7 /* PEL Read Index */ 66 67 /* standard VGA indexes max counts */ 68 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */ 69 #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */ 70 #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */ 71 #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */ 72 #define VGA_MIS_C 0x01 /* Number of Misc Output Register */ 73 74 /* VGA misc register bit masks */ 75 #define VGA_MIS_COLOR 0x01 76 #define VGA_MIS_ENB_MEM_ACCESS 0x02 77 #define VGA_MIS_DCLK_28322_720 0x04 78 #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08) 79 #define VGA_MIS_SEL_HIGH_PAGE 0x20 80 81 /* VGA CRT controller register indices */ 82 #define VGA_CRTC_H_TOTAL 0 83 #define VGA_CRTC_H_DISP 1 84 #define VGA_CRTC_H_BLANK_START 2 85 #define VGA_CRTC_H_BLANK_END 3 86 #define VGA_CRTC_H_SYNC_START 4 87 #define VGA_CRTC_H_SYNC_END 5 88 #define VGA_CRTC_V_TOTAL 6 89 #define VGA_CRTC_OVERFLOW 7 90 #define VGA_CRTC_PRESET_ROW 8 91 #define VGA_CRTC_MAX_SCAN 9 92 #define VGA_CRTC_CURSOR_START 0x0A 93 #define VGA_CRTC_CURSOR_END 0x0B 94 #define VGA_CRTC_START_HI 0x0C 95 #define VGA_CRTC_START_LO 0x0D 96 #define VGA_CRTC_CURSOR_HI 0x0E 97 #define VGA_CRTC_CURSOR_LO 0x0F 98 #define VGA_CRTC_V_SYNC_START 0x10 99 #define VGA_CRTC_V_SYNC_END 0x11 100 #define VGA_CRTC_V_DISP_END 0x12 101 #define VGA_CRTC_OFFSET 0x13 102 #define VGA_CRTC_UNDERLINE 0x14 103 #define VGA_CRTC_V_BLANK_START 0x15 104 #define VGA_CRTC_V_BLANK_END 0x16 105 #define VGA_CRTC_MODE 0x17 106 #define VGA_CRTC_LINE_COMPARE 0x18 107 #define VGA_CRTC_REGS VGA_CRT_C 108 109 /* VGA CRT controller bit masks */ 110 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */ 111 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80 112 113 /* VGA attribute controller register indices */ 114 #define VGA_ATC_PALETTE0 0x00 115 #define VGA_ATC_PALETTE1 0x01 116 #define VGA_ATC_PALETTE2 0x02 117 #define VGA_ATC_PALETTE3 0x03 118 #define VGA_ATC_PALETTE4 0x04 119 #define VGA_ATC_PALETTE5 0x05 120 #define VGA_ATC_PALETTE6 0x06 121 #define VGA_ATC_PALETTE7 0x07 122 #define VGA_ATC_PALETTE8 0x08 123 #define VGA_ATC_PALETTE9 0x09 124 #define VGA_ATC_PALETTEA 0x0A 125 #define VGA_ATC_PALETTEB 0x0B 126 #define VGA_ATC_PALETTEC 0x0C 127 #define VGA_ATC_PALETTED 0x0D 128 #define VGA_ATC_PALETTEE 0x0E 129 #define VGA_ATC_PALETTEF 0x0F 130 #define VGA_ATC_MODE 0x10 131 #define VGA_ATC_OVERSCAN 0x11 132 #define VGA_ATC_PLANE_ENABLE 0x12 133 #define VGA_ATC_PEL 0x13 134 #define VGA_ATC_COLOR_PAGE 0x14 135 136 #define VGA_AR_ENABLE_DISPLAY 0x20 137 138 /* VGA sequencer register indices */ 139 #define VGA_SEQ_RESET 0x00 140 #define VGA_SEQ_CLOCK_MODE 0x01 141 #define VGA_SEQ_PLANE_WRITE 0x02 142 #define VGA_SEQ_CHARACTER_MAP 0x03 143 #define VGA_SEQ_MEMORY_MODE 0x04 144 145 /* VGA sequencer register bit masks */ 146 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */ 147 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */ 148 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */ 149 #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */ 150 #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */ 151 #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */ 152 153 /* VGA graphics controller register indices */ 154 #define VGA_GFX_SR_VALUE 0x00 155 #define VGA_GFX_SR_ENABLE 0x01 156 #define VGA_GFX_COMPARE_VALUE 0x02 157 #define VGA_GFX_DATA_ROTATE 0x03 158 #define VGA_GFX_PLANE_READ 0x04 159 #define VGA_GFX_MODE 0x05 160 #define VGA_GFX_MISC 0x06 161 #define VGA_GFX_COMPARE_MASK 0x07 162 #define VGA_GFX_BIT_MASK 0x08 163 164 /* VGA graphics controller bit masks */ 165 #define VGA_GR06_GRAPHICS_MODE 0x01 166 167 /* macro for composing an 8-bit VGA register index and value 168 * into a single 16-bit quantity */ 169 #define VGA_OUT16VAL(v, r) (((v) << 8) | (r)) 170 171 /* decide whether we should enable the faster 16-bit VGA register writes */ 172 #ifdef __LITTLE_ENDIAN 173 #define VGA_OUTW_WRITE 174 #endif 175 176 /* VGA State Save and Restore */ 177 #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */ 178 #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */ 179 #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */ 180 #define VGA_SAVE_FONTS 7 /* save/restore all fonts */ 181 #define VGA_SAVE_MODE 8 /* save/restore video mode */ 182 #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */ 183 184 struct vgastate { 185 void __iomem *vgabase; /* mmio base, if supported */ 186 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ 187 __u32 memsize; /* VGA window size, 0 for default 64K */ 188 __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */ 189 __u32 depth; /* current fb depth, not important */ 190 __u32 num_attr; /* number of att registers, 0 for default */ 191 __u32 num_crtc; /* number of crt registers, 0 for default */ 192 __u32 num_gfx; /* number of gfx registers, 0 for default */ 193 __u32 num_seq; /* number of seq registers, 0 for default */ 194 void *vidstate; 195 }; 196 197 extern int save_vga(struct vgastate *state); 198 extern int restore_vga(struct vgastate *state); 199 200 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) 201 { 202 return readb (regbase + port); 203 } 204 205 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) 206 { 207 writeb (val, regbase + port); 208 } 209 210 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, 211 unsigned char reg, unsigned char val) 212 { 213 writew (VGA_OUT16VAL (val, reg), regbase + port); 214 } 215 216 /* 217 * generic VGA port read/write 218 */ 219 #ifdef CONFIG_HAS_IOPORT 220 221 static inline unsigned char vga_io_r (unsigned short port) 222 { 223 return inb_p(port); 224 } 225 226 static inline void vga_io_w (unsigned short port, unsigned char val) 227 { 228 outb_p(val, port); 229 } 230 231 static inline void vga_io_w_fast (unsigned short port, unsigned char reg, 232 unsigned char val) 233 { 234 outw(VGA_OUT16VAL (val, reg), port); 235 } 236 237 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) 238 { 239 if (regbase) 240 return vga_mm_r (regbase, port); 241 else 242 return vga_io_r (port); 243 } 244 245 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) 246 { 247 if (regbase) 248 vga_mm_w (regbase, port, val); 249 else 250 vga_io_w (port, val); 251 } 252 253 254 static inline void vga_w_fast (void __iomem *regbase, unsigned short port, 255 unsigned char reg, unsigned char val) 256 { 257 if (regbase) 258 vga_mm_w_fast (regbase, port, reg, val); 259 else 260 vga_io_w_fast (port, reg, val); 261 } 262 #else /* CONFIG_HAS_IOPORT */ 263 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) 264 { 265 return vga_mm_r (regbase, port); 266 } 267 268 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) 269 { 270 vga_mm_w (regbase, port, val); 271 } 272 273 274 static inline void vga_w_fast (void __iomem *regbase, unsigned short port, 275 unsigned char reg, unsigned char val) 276 { 277 vga_mm_w_fast (regbase, port, reg, val); 278 } 279 #endif /* CONFIG_HAS_IOPORT */ 280 281 /* 282 * VGA CRTC register read/write 283 */ 284 285 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) 286 { 287 vga_w (regbase, VGA_CRT_IC, reg); 288 return vga_r (regbase, VGA_CRT_DC); 289 } 290 291 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 292 { 293 #ifdef VGA_OUTW_WRITE 294 vga_w_fast (regbase, VGA_CRT_IC, reg, val); 295 #else 296 vga_w (regbase, VGA_CRT_IC, reg); 297 vga_w (regbase, VGA_CRT_DC, val); 298 #endif /* VGA_OUTW_WRITE */ 299 } 300 301 #ifdef CONFIG_HAS_IOPORT 302 static inline unsigned char vga_io_rcrt (unsigned char reg) 303 { 304 vga_io_w (VGA_CRT_IC, reg); 305 return vga_io_r (VGA_CRT_DC); 306 } 307 308 static inline void vga_io_wcrt (unsigned char reg, unsigned char val) 309 { 310 #ifdef VGA_OUTW_WRITE 311 vga_io_w_fast (VGA_CRT_IC, reg, val); 312 #else 313 vga_io_w (VGA_CRT_IC, reg); 314 vga_io_w (VGA_CRT_DC, val); 315 #endif /* VGA_OUTW_WRITE */ 316 } 317 #endif /* CONFIG_HAS_IOPORT */ 318 319 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) 320 { 321 vga_mm_w (regbase, VGA_CRT_IC, reg); 322 return vga_mm_r (regbase, VGA_CRT_DC); 323 } 324 325 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 326 { 327 #ifdef VGA_OUTW_WRITE 328 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); 329 #else 330 vga_mm_w (regbase, VGA_CRT_IC, reg); 331 vga_mm_w (regbase, VGA_CRT_DC, val); 332 #endif /* VGA_OUTW_WRITE */ 333 } 334 335 336 /* 337 * VGA sequencer register read/write 338 */ 339 340 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) 341 { 342 vga_w (regbase, VGA_SEQ_I, reg); 343 return vga_r (regbase, VGA_SEQ_D); 344 } 345 346 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 347 { 348 #ifdef VGA_OUTW_WRITE 349 vga_w_fast (regbase, VGA_SEQ_I, reg, val); 350 #else 351 vga_w (regbase, VGA_SEQ_I, reg); 352 vga_w (regbase, VGA_SEQ_D, val); 353 #endif /* VGA_OUTW_WRITE */ 354 } 355 356 #ifdef CONFIG_HAS_IOPORT 357 static inline unsigned char vga_io_rseq (unsigned char reg) 358 { 359 vga_io_w (VGA_SEQ_I, reg); 360 return vga_io_r (VGA_SEQ_D); 361 } 362 363 static inline void vga_io_wseq (unsigned char reg, unsigned char val) 364 { 365 #ifdef VGA_OUTW_WRITE 366 vga_io_w_fast (VGA_SEQ_I, reg, val); 367 #else 368 vga_io_w (VGA_SEQ_I, reg); 369 vga_io_w (VGA_SEQ_D, val); 370 #endif /* VGA_OUTW_WRITE */ 371 } 372 #endif /* CONFIG_HAS_IOPORT */ 373 374 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) 375 { 376 vga_mm_w (regbase, VGA_SEQ_I, reg); 377 return vga_mm_r (regbase, VGA_SEQ_D); 378 } 379 380 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 381 { 382 #ifdef VGA_OUTW_WRITE 383 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); 384 #else 385 vga_mm_w (regbase, VGA_SEQ_I, reg); 386 vga_mm_w (regbase, VGA_SEQ_D, val); 387 #endif /* VGA_OUTW_WRITE */ 388 } 389 390 /* 391 * VGA graphics controller register read/write 392 */ 393 394 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) 395 { 396 vga_w (regbase, VGA_GFX_I, reg); 397 return vga_r (regbase, VGA_GFX_D); 398 } 399 400 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 401 { 402 #ifdef VGA_OUTW_WRITE 403 vga_w_fast (regbase, VGA_GFX_I, reg, val); 404 #else 405 vga_w (regbase, VGA_GFX_I, reg); 406 vga_w (regbase, VGA_GFX_D, val); 407 #endif /* VGA_OUTW_WRITE */ 408 } 409 410 #ifdef CONFIG_HAS_IOPORT 411 static inline unsigned char vga_io_rgfx (unsigned char reg) 412 { 413 vga_io_w (VGA_GFX_I, reg); 414 return vga_io_r (VGA_GFX_D); 415 } 416 417 static inline void vga_io_wgfx (unsigned char reg, unsigned char val) 418 { 419 #ifdef VGA_OUTW_WRITE 420 vga_io_w_fast (VGA_GFX_I, reg, val); 421 #else 422 vga_io_w (VGA_GFX_I, reg); 423 vga_io_w (VGA_GFX_D, val); 424 #endif /* VGA_OUTW_WRITE */ 425 } 426 #endif /* CONFIG_HAS_IOPORT */ 427 428 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) 429 { 430 vga_mm_w (regbase, VGA_GFX_I, reg); 431 return vga_mm_r (regbase, VGA_GFX_D); 432 } 433 434 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 435 { 436 #ifdef VGA_OUTW_WRITE 437 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); 438 #else 439 vga_mm_w (regbase, VGA_GFX_I, reg); 440 vga_mm_w (regbase, VGA_GFX_D, val); 441 #endif /* VGA_OUTW_WRITE */ 442 } 443 444 445 /* 446 * VGA attribute controller register read/write 447 */ 448 449 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) 450 { 451 vga_w (regbase, VGA_ATT_IW, reg); 452 return vga_r (regbase, VGA_ATT_R); 453 } 454 455 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 456 { 457 vga_w (regbase, VGA_ATT_IW, reg); 458 vga_w (regbase, VGA_ATT_W, val); 459 } 460 461 #ifdef CONFIG_HAS_IOPORT 462 static inline unsigned char vga_io_rattr (unsigned char reg) 463 { 464 vga_io_w (VGA_ATT_IW, reg); 465 return vga_io_r (VGA_ATT_R); 466 } 467 468 static inline void vga_io_wattr (unsigned char reg, unsigned char val) 469 { 470 vga_io_w (VGA_ATT_IW, reg); 471 vga_io_w (VGA_ATT_W, val); 472 } 473 #endif /* CONFIG_HAS_IOPORT */ 474 475 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) 476 { 477 vga_mm_w (regbase, VGA_ATT_IW, reg); 478 return vga_mm_r (regbase, VGA_ATT_R); 479 } 480 481 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 482 { 483 vga_mm_w (regbase, VGA_ATT_IW, reg); 484 vga_mm_w (regbase, VGA_ATT_W, val); 485 } 486 487 #endif /* __linux_video_vga_h__ */ 488