xref: /linux/include/video/atmel_lcdc.h (revision 1a59d1b8e05ea6ab45f7e18897de1ef0e6bc3da6)
1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
214340586SNicolas Ferre /*
314340586SNicolas Ferre  *  Header file for AT91/AT32 LCD Controller
414340586SNicolas Ferre  *
514340586SNicolas Ferre  *  Data structure and register user interface
614340586SNicolas Ferre  *
714340586SNicolas Ferre  *  Copyright (C) 2007 Atmel Corporation
814340586SNicolas Ferre  */
914340586SNicolas Ferre #ifndef __ATMEL_LCDC_H__
1014340586SNicolas Ferre #define __ATMEL_LCDC_H__
1114340586SNicolas Ferre 
1244ccac13SAdrian Bunk #include <linux/workqueue.h>
13fd085801SNicolas Ferre 
14fd085801SNicolas Ferre /* Way LCD wires are connected to the chip:
15fd085801SNicolas Ferre  * Some Atmel chips use BGR color mode (instead of standard RGB)
16fd085801SNicolas Ferre  * A swapped wiring onboard can bring to RGB mode.
17fd085801SNicolas Ferre  */
18fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_BGR	0
19fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_RGB	1
20fd085801SNicolas Ferre 
21fd085801SNicolas Ferre 
22a9a84c37SDavid Brownell  /* LCD Controller info data structure, stored in device platform_data */
238af2c286SJean-Christophe PLAGNIOL-VILLARD struct atmel_lcdfb_pdata {
2414340586SNicolas Ferre 	unsigned int		guard_time;
25a9a84c37SDavid Brownell 	bool			lcdcon_is_backlight;
267cdcdb69SAndreas Bießmann 	bool			lcdcon_pol_negative;
27a9a84c37SDavid Brownell 	u8			default_bpp;
28fd085801SNicolas Ferre 	u8			lcd_wiring_mode;
2914340586SNicolas Ferre 	unsigned int		default_lcdcon2;
3014340586SNicolas Ferre 	unsigned int		default_dmacon;
31ce3b64f5SJean-Christophe PLAGNIOL-VILLARD 	void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on);
3214340586SNicolas Ferre 	struct fb_monspecs	*default_monspecs;
33ce3b64f5SJean-Christophe PLAGNIOL-VILLARD 
34ce3b64f5SJean-Christophe PLAGNIOL-VILLARD 	struct list_head	pwr_gpios;
3514340586SNicolas Ferre };
3614340586SNicolas Ferre 
3714340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR1	0x00
3814340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR2	0x04
3914340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT1	0x08
4014340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT2	0x0c
4114340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD1	0x10
4214340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD2	0x14
4314340586SNicolas Ferre 
4414340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMCFG	0x18
4514340586SNicolas Ferre #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
4614340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH_OFFSET	24
4714340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
4814340586SNicolas Ferre 
4914340586SNicolas Ferre #define ATMEL_LCDC_DMACON	0x1c
5014340586SNicolas Ferre #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
5114340586SNicolas Ferre #define	ATMEL_LCDC_DMARST	(0x1 << 1)
5214340586SNicolas Ferre #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
5314340586SNicolas Ferre #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
5414340586SNicolas Ferre #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
5514340586SNicolas Ferre 
5614340586SNicolas Ferre #define ATMEL_LCDC_DMA2DCFG	0x20
5714340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC_OFFSET	0
5814340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC		(0xffff)
5914340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
6014340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
6114340586SNicolas Ferre 
6214340586SNicolas Ferre #define ATMEL_LCDC_LCDCON1	0x0800
6314340586SNicolas Ferre #define	ATMEL_LCDC_BYPASS	(1     <<  0)
6414340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL_OFFSET	12
6514340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
6614340586SNicolas Ferre #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
6714340586SNicolas Ferre 
6814340586SNicolas Ferre #define ATMEL_LCDC_LCDCON2	0x0804
6914340586SNicolas Ferre #define	ATMEL_LCDC_DISTYPE	(3 << 0)
7014340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
7114340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
7214340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
7314340586SNicolas Ferre #define	ATMEL_LCDC_SCANMOD	(1 << 2)
7414340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
7514340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
7614340586SNicolas Ferre #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
7714340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
7814340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
7914340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
8014340586SNicolas Ferre #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
8114340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
8214340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
8314340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
8414340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
8514340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
8614340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
8714340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
8814340586SNicolas Ferre #define	ATMEL_LCDC_INVVD	(1 << 8)
8914340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
9014340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
9114340586SNicolas Ferre #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
9214340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
9314340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
9414340586SNicolas Ferre #define	ATMEL_LCDC_INVLINE	(1 << 10)
9514340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
9614340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
9714340586SNicolas Ferre #define	ATMEL_LCDC_INVCLK	(1 << 11)
9814340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
9914340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
10014340586SNicolas Ferre #define	ATMEL_LCDC_INVDVAL	(1 << 12)
10114340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
10214340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
10314340586SNicolas Ferre #define	ATMEL_LCDC_CLKMOD	(1 << 15)
10414340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
10514340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
10614340586SNicolas Ferre #define	ATMEL_LCDC_MEMOR	(1 << 31)
10714340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
10814340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
10914340586SNicolas Ferre 
11014340586SNicolas Ferre #define ATMEL_LCDC_TIM1		0x0808
111162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VFP		(0xffU <<  0)
11214340586SNicolas Ferre #define	ATMEL_LCDC_VBP_OFFSET		8
113162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
11414340586SNicolas Ferre #define	ATMEL_LCDC_VPW_OFFSET		16
115162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
11614340586SNicolas Ferre #define	ATMEL_LCDC_VHDLY_OFFSET		24
117162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
11814340586SNicolas Ferre 
11914340586SNicolas Ferre #define ATMEL_LCDC_TIM2		0x080c
120162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
12114340586SNicolas Ferre #define	ATMEL_LCDC_HPW_OFFSET		8
122162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
12314340586SNicolas Ferre #define	ATMEL_LCDC_HFP_OFFSET		21
124162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
12514340586SNicolas Ferre 
12614340586SNicolas Ferre #define ATMEL_LCDC_LCDFRMCFG	0x0810
12714340586SNicolas Ferre #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
12814340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL_OFFSET	21
12914340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
13014340586SNicolas Ferre 
13114340586SNicolas Ferre #define ATMEL_LCDC_FIFO		0x0814
13214340586SNicolas Ferre #define	ATMEL_LCDC_FIFOTH	(0xffff)
13314340586SNicolas Ferre 
13414340586SNicolas Ferre #define ATMEL_LCDC_MVAL		0x0818
13514340586SNicolas Ferre 
13614340586SNicolas Ferre #define ATMEL_LCDC_DP1_2	0x081c
13714340586SNicolas Ferre #define ATMEL_LCDC_DP4_7	0x0820
13814340586SNicolas Ferre #define ATMEL_LCDC_DP3_5	0x0824
13914340586SNicolas Ferre #define ATMEL_LCDC_DP2_3	0x0828
14014340586SNicolas Ferre #define ATMEL_LCDC_DP5_7	0x082c
14114340586SNicolas Ferre #define ATMEL_LCDC_DP3_4	0x0830
14214340586SNicolas Ferre #define ATMEL_LCDC_DP4_5	0x0834
14314340586SNicolas Ferre #define ATMEL_LCDC_DP6_7	0x0838
14414340586SNicolas Ferre #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
14514340586SNicolas Ferre #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
14614340586SNicolas Ferre #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
14714340586SNicolas Ferre #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
14814340586SNicolas Ferre #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
14914340586SNicolas Ferre #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
15014340586SNicolas Ferre #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
15114340586SNicolas Ferre #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
15214340586SNicolas Ferre 
15314340586SNicolas Ferre #define ATMEL_LCDC_PWRCON	0x083c
15414340586SNicolas Ferre #define	ATMEL_LCDC_PWR		(1    <<  0)
15514340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT_OFFSET	1
15614340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
15714340586SNicolas Ferre #define	ATMEL_LCDC_BUSY		(1    << 31)
15814340586SNicolas Ferre 
15914340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_CTR	0x0840
16014340586SNicolas Ferre #define	ATMEL_LCDC_PS		(3 << 0)
16114340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
16214340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
16314340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
16414340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
16514340586SNicolas Ferre #define	ATMEL_LCDC_POL		(1 << 2)
16614340586SNicolas Ferre #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
16714340586SNicolas Ferre #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
16814340586SNicolas Ferre #define	ATMEL_LCDC_ENA		(1 << 3)
16914340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
17014340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
17114340586SNicolas Ferre 
17214340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_VAL	0x0844
17314340586SNicolas Ferre #define	ATMEL_LCDC_CVAL	(0xff)
17414340586SNicolas Ferre 
17514340586SNicolas Ferre #define ATMEL_LCDC_IER		0x0848
17614340586SNicolas Ferre #define ATMEL_LCDC_IDR		0x084c
17714340586SNicolas Ferre #define ATMEL_LCDC_IMR		0x0850
17814340586SNicolas Ferre #define ATMEL_LCDC_ISR		0x0854
17914340586SNicolas Ferre #define ATMEL_LCDC_ICR		0x0858
18014340586SNicolas Ferre #define	ATMEL_LCDC_LNI		(1 << 0)
18114340586SNicolas Ferre #define	ATMEL_LCDC_LSTLNI	(1 << 1)
18214340586SNicolas Ferre #define	ATMEL_LCDC_EOFI		(1 << 2)
18314340586SNicolas Ferre #define	ATMEL_LCDC_UFLWI	(1 << 4)
18414340586SNicolas Ferre #define	ATMEL_LCDC_OWRI		(1 << 5)
18514340586SNicolas Ferre #define	ATMEL_LCDC_MERI		(1 << 6)
18614340586SNicolas Ferre 
18714340586SNicolas Ferre #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
18814340586SNicolas Ferre 
18914340586SNicolas Ferre #endif /* __ATMEL_LCDC_H__ */
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